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registers.hh
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38  * Authors: Gabe Black
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40 
41 #ifndef __ARCH_X86_REGISTERS_HH__
42 #define __ARCH_X86_REGISTERS_HH__
43 
45 #include "arch/generic/vec_reg.hh"
46 #include "arch/x86/generated/max_inst_regs.hh"
47 #include "arch/x86/regs/int.hh"
48 #include "arch/x86/regs/ccr.hh"
49 #include "arch/x86/regs/misc.hh"
50 #include "arch/x86/x86_traits.hh"
51 
52 namespace X86ISA
53 {
55 using X86ISAInst::MaxInstDestRegs;
58 
60 const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs + NumImplicitIntRegs;
61 const int NumCCRegs = NUM_CCREGS;
62 
63 // Each 128 bit xmm register is broken into two effective 64 bit registers.
64 // Add 8 for the indices that are mapped over the fp stack
65 const int NumFloatRegs =
67 
68 // These enumerate all the registers for dependence tracking.
70  // FP_Reg_Base must be large enough to be bigger than any integer
71  // register index which has the IntFoldBit (1 << 6) set. To be safe
72  // we just start at (1 << 7) == 128.
73  FP_Reg_Base = 128,
76  Max_Reg_Index = Misc_Reg_Base + NumMiscRegs
77 };
78 
79 const int NumVecRegs = 1; // Not applicable to x86
80  // (1 to prevent warnings)
81 const int NumVecPredRegs = 1; // Not applicable to x86
82  // (1 to prevent warnings)
83 
84 // semantically meaningful register indices
85 //There is no such register in X86
86 const int ZeroReg = NUM_INTREGS;
87 const int StackPointerReg = INTREG_RSP;
88 //X86 doesn't seem to have a link register
89 const int ReturnAddressReg = 0;
90 const int ReturnValueReg = INTREG_RAX;
91 const int FramePointerReg = INTREG_RBP;
92 
93 // Some OS syscalls use a second register (rdx) to return a second
94 // value
95 const int SyscallPseudoReturnReg = INTREG_RDX;
96 
97 // Not applicable to x86
104 
105 // Not applicable to x86
111 
112 } // namespace X86ISA
113 
114 #endif // __ARCH_X86_REGFILE_HH__
constexpr unsigned DummyNumVecElemPerVecReg
Definition: vec_reg.hh:664
Vector Register Abstraction This generic class is the model in a particularization of MVC...
Definition: vec_reg.hh:160
const int ReturnValueReg
Definition: registers.hh:90
constexpr bool DummyVecPredRegHasPackedRepr
Dummy type aliases and constants for architectures that do not implement vector predicate registers...
const int NumMicroFpRegs
Definition: x86_traits.hh:59
VecRegT< DummyVecElem, DummyNumVecElemPerVecReg, true > DummyConstVecReg
Definition: vec_reg.hh:666
uint32_t DummyVecElem
Dummy type aliases and constants for architectures that do not implement vector registers.
Definition: vec_reg.hh:663
const int NumVecPredRegs
Definition: registers.hh:81
const int MaxInstSrcRegs
Definition: registers.hh:59
const int NumFloatRegs
Definition: registers.hh:65
DummyVecPredReg::Container DummyVecPredRegContainer
constexpr size_t DummyVecPredRegSizeBits
::DummyVecElem VecElem
Definition: registers.hh:98
const int StackPointerReg
Definition: registers.hh:87
const int NumMMXRegs
Definition: x86_traits.hh:57
const int ReturnAddressReg
Definition: registers.hh:89
const int MaxMiscDestRegs
Definition: registers.hh:70
const int FramePointerReg
Definition: registers.hh:91
Predicate register view.
Definition: vec_pred_reg.hh:70
constexpr unsigned NumVecElemPerVecReg
Definition: registers.hh:102
const int NumXMMRegs
Definition: x86_traits.hh:58
constexpr bool VecPredRegHasPackedRepr
Definition: registers.hh:110
constexpr size_t VecRegSizeBytes
Definition: registers.hh:103
VecRegT< DummyVecElem, DummyNumVecElemPerVecReg, false > DummyVecReg
Definition: vec_reg.hh:665
DummyVecReg::Container DummyVecRegContainer
Definition: vec_reg.hh:667
const int NumVecRegs
Definition: registers.hh:79
DependenceTags
Definition: registers.hh:69
const int NumImplicitIntRegs
Definition: x86_traits.hh:49
const int NumCCRegs
Definition: registers.hh:61
const int NumMicroIntRegs
Definition: x86_traits.hh:47
constexpr size_t VecPredRegSizeBits
Definition: registers.hh:109
const int SyscallPseudoReturnReg
Definition: registers.hh:95
This is exposed globally, independent of the ISA.
Definition: acpi.hh:57
VecPredRegT< DummyVecElem, DummyNumVecElemPerVecReg, DummyVecPredRegHasPackedRepr, true > DummyConstVecPredReg
Vector Registers layout specification.
const int ZeroReg
Definition: registers.hh:86
Generic predicate register container.
Definition: vec_pred_reg.hh:51
const int NumIntRegs
Definition: registers.hh:60
VecPredRegT< DummyVecElem, DummyNumVecElemPerVecReg, DummyVecPredRegHasPackedRepr, false > DummyVecPredReg
Vector Register Abstraction This generic class is a view in a particularization of MVC...
Definition: vec_reg.hh:174
const int NumMiscRegs
Definition: registers.hh:57
const int NumIntArchRegs
Definition: registers.hh:59
constexpr size_t DummyVecRegSizeBytes
Definition: vec_reg.hh:668

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