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gem5
v20.1.0.0
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#include "base/logging.hh"#include "base/trace.hh"#include "config/the_isa.hh"#include "debug/TimeSync.hh"#include "sim/eventq.hh"#include "sim/full_system.hh"#include "sim/root.hh"Go to the source code of this file.
Variables | |
| bool | FullSystem |
| The FullSystem variable can be used to determine the current mode of simulation. More... | |
| unsigned int | FullSystemInt |
| In addition to the boolean flag we make use of an unsigned int since the CPU instruction decoder makes use of the variable in switch statements. More... | |
| bool FullSystem |
The FullSystem variable can be used to determine the current mode of simulation.
Definition at line 132 of file root.cc.
Referenced by PowerISA::RemoteGDB::acc(), SparcISA::RemoteGDB::acc(), MipsISA::RemoteGDB::acc(), RiscvISA::RemoteGDB::acc(), X86ISA::RemoteGDB::acc(), ArmISA::RemoteGDB::acc(), PseudoInst::addsymbol(), PseudoInst::arm(), BaseSimpleCPU::BaseSimpleCPU(), MiscRegOp64::checkEL1Trap(), BaseCPU::checkInterrupts(), Minor::Execute::checkInterrupts(), ArmISA::ISA::clear(), ArmISA::ISA::clear32(), DefaultCommit< Impl >::commit(), O3ThreadContext< Impl >::copyArchRegs(), SimpleThread::copyState(), X86ISA::TLB::finalizePhysical(), SparcISA::getArgument(), ArmISA::getArgument(), ArmSystem::getArmSystem(), ArmISA::ISA::getCurSveVecLenInBits(), ThreadState::getPhysProxy(), Minor::Execute::hasInterrupt(), ArmSystem::haveLPAE(), ArmSystem::haveSecurity(), ArmSystem::haveSemihosting(), ArmSystem::haveVirtualization(), ArmISA::ISA::MiscRegLUTEntryInitializer::highest(), ArmSystem::highestEL(), ArmSystem::highestELIs64(), ArmISA::ISA::initializeMiscRegMetadata(), ThreadState::initMemProxies(), Iris::ThreadContext::initMemProxies(), PseudoInst::initParam(), FullO3CPU< O3CPUImpl >::insertThread(), X86ISA::inUserMode(), FaultBase::invoke(), SparcISA::SparcFaultBase::invoke(), X86ISA::X86FaultBase::invoke(), MipsISA::MipsFaultBase::invoke(), X86ISA::X86Trap::invoke(), RiscvISA::RiscvFault::invoke(), GenericPageTableFault::invoke(), MipsISA::ResetFault::invoke(), MipsISA::CoprocessorUnusableFault::invoke(), MipsISA::AddressFault< TlbInvalidFault >::invoke(), X86ISA::InvalidOpcode::invoke(), SparcISA::FastInstructionAccessMMUMiss::invoke(), ArmISA::ArmFault::invoke(), SparcISA::FastDataAccessMMUMiss::invoke(), SparcISA::SpillNNormal::invoke(), MipsISA::TlbFault< TlbInvalidFault >::invoke(), SparcISA::FillNNormal::invoke(), SparcISA::TrapInstruction::invoke(), X86ISA::PageFault::invoke(), ArmISA::Reset::invoke(), ArmISA::UndefinedInstruction::invoke(), ArmISA::SupervisorCall::invoke(), ArmISA::SecureMonitorCall::invoke(), ArmISA::ArmSev::invoke(), ArmISA::ISA::ISA(), PseudoInst::loadsymbol(), MinorCPU::MinorCPU(), ArmSemihosting::portProxy(), BaseSimpleCPU::postExecute(), BaseCPU::postInterrupt(), PseudoInst::readfile(), RubyPort::PioRequestPort::recvRangeChange(), BaseCPU::registerThreadContexts(), X86ISA::Interrupts::requestInterrupt(), ThreadState::serialize(), Root::serialize(), CheckerCPU::setSystem(), DefaultDecode< Impl >::squash(), takeOverFrom(), FullO3CPU< O3CPUImpl >::tick(), DefaultFetch< Impl >::tick(), Trace::ExeTracerRecord::traceInst(), X86ISA::TLB::translate(), RiscvISA::TLB::translate(), X86ISA::GpuTLB::translate(), MipsISA::TLB::translateAtomic(), PowerISA::TLB::translateAtomic(), ArmISA::TLB::translateAtomic(), ArmISA::TLB::translateComplete(), SparcISA::TLB::translateData(), MipsISA::TLB::translateFunctional(), RiscvISA::TLB::translateFunctional(), X86ISA::TLB::translateFunctional(), PowerISA::TLB::translateFunctional(), SparcISA::TLB::translateFunctional(), ArmISA::TLB::translateFunctional(), SparcISA::TLB::translateInst(), ThreadState::unserialize(), and Checker< O3CPUImpl >::verify().