gem5  v20.1.0.0
isa.cc
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37 
38 #include "arch/arm/isa.hh"
39 
40 #include "arch/arm/faults.hh"
41 #include "arch/arm/htm.hh"
42 #include "arch/arm/interrupts.hh"
43 #include "arch/arm/pmu.hh"
44 #include "arch/arm/self_debug.hh"
45 #include "arch/arm/system.hh"
46 #include "arch/arm/tlb.hh"
47 #include "arch/arm/tlbi_op.hh"
48 #include "cpu/base.hh"
49 #include "cpu/checker/cpu.hh"
50 #include "debug/Arm.hh"
51 #include "debug/MiscRegs.hh"
52 #include "dev/arm/generic_timer.hh"
53 #include "dev/arm/gic_v3.hh"
54 #include "dev/arm/gic_v3_cpu_interface.hh"
55 #include "params/ArmISA.hh"
56 #include "sim/faults.hh"
57 #include "sim/stat_control.hh"
58 #include "sim/system.hh"
59 
60 namespace ArmISA
61 {
62 
63 ISA::ISA(Params *p) : BaseISA(p), system(NULL),
64  _decoderFlavor(p->decoderFlavor), _vecRegRenameMode(Enums::Full),
65  pmu(p->pmu), impdefAsNop(p->impdef_nop),
66  afterStartup(false)
67 {
68  miscRegs[MISCREG_SCTLR_RST] = 0;
69 
70  // Hook up a dummy device if we haven't been configured with a
71  // real PMU. By using a dummy device, we don't need to check that
72  // the PMU exist every time we try to access a PMU register.
73  if (!pmu)
74  pmu = &dummyDevice;
75 
76  // Give all ISA devices a pointer to this ISA
77  pmu->setISA(this);
78 
79  system = dynamic_cast<ArmSystem *>(p->system);
80 
81  // Cache system-level properties
82  if (FullSystem && system) {
83  highestELIs64 = system->highestELIs64();
84  haveSecurity = system->haveSecurity();
85  haveLPAE = system->haveLPAE();
86  haveCrypto = system->haveCrypto();
87  haveVirtualization = system->haveVirtualization();
88  haveLargeAsid64 = system->haveLargeAsid64();
89  physAddrRange = system->physAddrRange();
90  haveSVE = system->haveSVE();
91  havePAN = system->havePAN();
92  haveSecEL2 = system->haveSecEL2();
93  sveVL = system->sveVL();
94  haveLSE = system->haveLSE();
95  haveTME = system->haveTME();
96  } else {
97  highestELIs64 = true; // ArmSystem::highestELIs64 does the same
98  haveSecurity = haveLPAE = haveVirtualization = false;
99  haveCrypto = true;
100  haveLargeAsid64 = false;
101  physAddrRange = 32; // dummy value
102  haveSVE = true;
103  havePAN = false;
104  haveSecEL2 = true;
105  sveVL = p->sve_vl_se;
106  haveLSE = true;
107  haveTME = true;
108  }
109 
110  // Initial rename mode depends on highestEL
111  const_cast<Enums::VecRegRenameMode&>(_vecRegRenameMode) =
112  highestELIs64 ? Enums::Full : Enums::Elem;
113 
114  selfDebug = new SelfDebug();
115  initializeMiscRegMetadata();
116  preUnflattenMiscReg();
117 
118  clear();
119 }
120 
121 std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS);
122 
123 const ArmISAParams *
124 ISA::params() const
125 {
126  return dynamic_cast<const Params *>(_params);
127 }
128 
129 void
130 ISA::clear()
131 {
132  const Params *p(params());
133 
134  // Invalidate cached copies of miscregs in the TLBs
135  if (tc) {
136  getITBPtr(tc)->invalidateMiscReg();
137  getDTBPtr(tc)->invalidateMiscReg();
138  }
139 
140  SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
141  memset(miscRegs, 0, sizeof(miscRegs));
142 
143  initID32(p);
144 
145  // We always initialize AArch64 ID registers even
146  // if we are in AArch32. This is done since if we
147  // are in SE mode we don't know if our ArmProcess is
148  // AArch32 or AArch64
149  initID64(p);
150 
151  // Start with an event in the mailbox
152  miscRegs[MISCREG_SEV_MAILBOX] = 1;
153 
154  // Separate Instruction and Data TLBs
155  miscRegs[MISCREG_TLBTR] = 1;
156 
157  MVFR0 mvfr0 = 0;
158  mvfr0.advSimdRegisters = 2;
159  mvfr0.singlePrecision = 2;
160  mvfr0.doublePrecision = 2;
161  mvfr0.vfpExceptionTrapping = 0;
162  mvfr0.divide = 1;
163  mvfr0.squareRoot = 1;
164  mvfr0.shortVectors = 1;
165  mvfr0.roundingModes = 1;
166  miscRegs[MISCREG_MVFR0] = mvfr0;
167 
168  MVFR1 mvfr1 = 0;
169  mvfr1.flushToZero = 1;
170  mvfr1.defaultNaN = 1;
171  mvfr1.advSimdLoadStore = 1;
172  mvfr1.advSimdInteger = 1;
173  mvfr1.advSimdSinglePrecision = 1;
174  mvfr1.advSimdHalfPrecision = 1;
175  mvfr1.vfpHalfPrecision = 1;
176  miscRegs[MISCREG_MVFR1] = mvfr1;
177 
178  // Reset values of PRRR and NMRR are implementation dependent
179 
180  // @todo: PRRR and NMRR in secure state?
181  miscRegs[MISCREG_PRRR_NS] =
182  (1 << 19) | // 19
183  (0 << 18) | // 18
184  (0 << 17) | // 17
185  (1 << 16) | // 16
186  (2 << 14) | // 15:14
187  (0 << 12) | // 13:12
188  (2 << 10) | // 11:10
189  (2 << 8) | // 9:8
190  (2 << 6) | // 7:6
191  (2 << 4) | // 5:4
192  (1 << 2) | // 3:2
193  0; // 1:0
194 
195  miscRegs[MISCREG_NMRR_NS] =
196  (1 << 30) | // 31:30
197  (0 << 26) | // 27:26
198  (0 << 24) | // 25:24
199  (3 << 22) | // 23:22
200  (2 << 20) | // 21:20
201  (0 << 18) | // 19:18
202  (0 << 16) | // 17:16
203  (1 << 14) | // 15:14
204  (0 << 12) | // 13:12
205  (2 << 10) | // 11:10
206  (0 << 8) | // 9:8
207  (3 << 6) | // 7:6
208  (2 << 4) | // 5:4
209  (0 << 2) | // 3:2
210  0; // 1:0
211 
212  if (FullSystem && system->highestELIs64()) {
213  // Initialize AArch64 state
214  clear64(p);
215  return;
216  }
217 
218  // Initialize AArch32 state...
219  clear32(p, sctlr_rst);
220 }
221 
222 void
223 ISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst)
224 {
225  CPSR cpsr = 0;
226  cpsr.mode = MODE_USER;
227 
228  if (FullSystem) {
229  miscRegs[MISCREG_MVBAR] = system->resetAddr();
230  }
231 
232  miscRegs[MISCREG_CPSR] = cpsr;
233  updateRegMap(cpsr);
234 
235  SCTLR sctlr = 0;
236  sctlr.te = (bool) sctlr_rst.te;
237  sctlr.nmfi = (bool) sctlr_rst.nmfi;
238  sctlr.v = (bool) sctlr_rst.v;
239  sctlr.u = 1;
240  sctlr.xp = 1;
241  sctlr.rao2 = 1;
242  sctlr.rao3 = 1;
243  sctlr.rao4 = 0xf; // SCTLR[6:3]
244  sctlr.uci = 1;
245  sctlr.dze = 1;
246  miscRegs[MISCREG_SCTLR_NS] = sctlr;
247  miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
248  miscRegs[MISCREG_HCPTR] = 0;
249 
250  miscRegs[MISCREG_CPACR] = 0;
251 
252  miscRegs[MISCREG_FPSID] = p->fpsid;
253 
254  if (haveLPAE) {
255  TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
256  ttbcr.eae = 0;
257  miscRegs[MISCREG_TTBCR_NS] = ttbcr;
258  // Enforce consistency with system-level settings
259  miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5;
260  }
261 
262  if (haveSecurity) {
263  miscRegs[MISCREG_SCTLR_S] = sctlr;
264  miscRegs[MISCREG_SCR] = 0;
265  miscRegs[MISCREG_VBAR_S] = 0;
266  } else {
267  // we're always non-secure
268  miscRegs[MISCREG_SCR] = 1;
269  }
270 
271  //XXX We need to initialize the rest of the state.
272 }
273 
274 void
275 ISA::clear64(const ArmISAParams *p)
276 {
277  CPSR cpsr = 0;
278  Addr rvbar = system->resetAddr();
279  switch (system->highestEL()) {
280  // Set initial EL to highest implemented EL using associated stack
281  // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
282  // value
283  case EL3:
284  cpsr.mode = MODE_EL3H;
285  miscRegs[MISCREG_RVBAR_EL3] = rvbar;
286  break;
287  case EL2:
288  cpsr.mode = MODE_EL2H;
289  miscRegs[MISCREG_RVBAR_EL2] = rvbar;
290  break;
291  case EL1:
292  cpsr.mode = MODE_EL1H;
293  miscRegs[MISCREG_RVBAR_EL1] = rvbar;
294  break;
295  default:
296  panic("Invalid highest implemented exception level");
297  break;
298  }
299 
300  // Initialize rest of CPSR
301  cpsr.daif = 0xf; // Mask all interrupts
302  cpsr.ss = 0;
303  cpsr.il = 0;
304  miscRegs[MISCREG_CPSR] = cpsr;
305  updateRegMap(cpsr);
306 
307  // Initialize other control registers
308  miscRegs[MISCREG_MPIDR_EL1] = 0x80000000;
309  if (haveSecurity) {
310  miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830;
311  miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields
312  } else if (haveVirtualization) {
313  // also MISCREG_SCTLR_EL2 (by mapping)
314  miscRegs[MISCREG_HSCTLR] = 0x30c50830;
315  } else {
316  // also MISCREG_SCTLR_EL1 (by mapping)
317  miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init
318  // Always non-secure
319  miscRegs[MISCREG_SCR_EL3] = 1;
320  }
321 }
322 
323 void
324 ISA::initID32(const ArmISAParams *p)
325 {
326  // Initialize configurable default values
327 
328  uint32_t midr;
329  if (p->midr != 0x0)
330  midr = p->midr;
331  else if (highestELIs64)
332  // Cortex-A57 TRM r0p0 MIDR
333  midr = 0x410fd070;
334  else
335  // Cortex-A15 TRM r0p0 MIDR
336  midr = 0x410fc0f0;
337 
338  miscRegs[MISCREG_MIDR] = midr;
339  miscRegs[MISCREG_MIDR_EL1] = midr;
340  miscRegs[MISCREG_VPIDR] = midr;
341 
342  miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
343  miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
344  miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
345  miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
346  miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
347  miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
348 
349  miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
350  miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
351  miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
352  miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
353 
354  miscRegs[MISCREG_ID_ISAR5] = insertBits(
355  miscRegs[MISCREG_ID_ISAR5], 19, 4,
356  haveCrypto ? 0x1112 : 0x0);
357 }
358 
359 void
360 ISA::initID64(const ArmISAParams *p)
361 {
362  // Initialize configurable id registers
363  miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1;
364  miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1;
365  miscRegs[MISCREG_ID_AA64DFR0_EL1] =
366  (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
367  (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3
368 
369  miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1;
370  miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1;
371  miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1;
372  miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1;
373  miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1;
374  miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1;
375 
376  miscRegs[MISCREG_ID_DFR0_EL1] =
377  (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3
378 
379  miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1];
380 
381  // SVE
382  miscRegs[MISCREG_ID_AA64ZFR0_EL1] = 0; // SVEver 0
383  if (haveSecurity) {
384  miscRegs[MISCREG_ZCR_EL3] = sveVL - 1;
385  } else if (haveVirtualization) {
386  miscRegs[MISCREG_ZCR_EL2] = sveVL - 1;
387  } else {
388  miscRegs[MISCREG_ZCR_EL1] = sveVL - 1;
389  }
390 
391  // Enforce consistency with system-level settings...
392 
393  // EL3
394  miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
395  miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
396  haveSecurity ? 0x2 : 0x0);
397  // EL2
398  miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
399  miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8,
400  haveVirtualization ? 0x2 : 0x0);
401  // SVE
402  miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
403  miscRegs[MISCREG_ID_AA64PFR0_EL1], 35, 32,
404  haveSVE ? 0x1 : 0x0);
405  // SecEL2
406  miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
407  miscRegs[MISCREG_ID_AA64PFR0_EL1], 39, 36,
408  haveSecEL2 ? 0x1 : 0x0);
409  miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
410  miscRegs[MISCREG_ID_AA64ISAR0_EL1], 39, 36,
411  haveSecEL2 ? 0x1 : 0x0);
412  // Large ASID support
413  miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
414  miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
415  haveLargeAsid64 ? 0x2 : 0x0);
416  // Physical address size
417  miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
418  miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
419  encodePhysAddrRange64(physAddrRange));
420  // Crypto
421  miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
422  miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4,
423  haveCrypto ? 0x1112 : 0x0);
424  // LSE
425  miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
426  miscRegs[MISCREG_ID_AA64ISAR0_EL1], 23, 20,
427  haveLSE ? 0x2 : 0x0);
428  // PAN
429  miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
430  miscRegs[MISCREG_ID_AA64MMFR1_EL1], 23, 20,
431  havePAN ? 0x1 : 0x0);
432  // TME
433  miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
434  miscRegs[MISCREG_ID_AA64ISAR0_EL1], 27, 24,
435  haveTME ? 0x1 : 0x0);
436 }
437 
438 void
439 ISA::startup()
440 {
441  BaseISA::startup();
442 
443  if (tc) {
444  setupThreadContext();
445 
446  if (haveTME) {
447  std::unique_ptr<BaseHTMCheckpoint> cpt(new HTMCheckpoint());
448  tc->setHtmCheckpointPtr(std::move(cpt));
449  }
450  }
451 
452  afterStartup = true;
453 }
454 
455 void
456 ISA::setupThreadContext()
457 {
458  pmu->setThreadContext(tc);
459 
460  if (!system)
461  return;
462 
463  selfDebug->init(tc);
464 
465  Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC());
466  if (!gicv3)
467  return;
468 
469  if (!gicv3CpuInterface)
470  gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
471 
472  gicv3CpuInterface->setISA(this);
473  gicv3CpuInterface->setThreadContext(tc);
474 }
475 
476 void
477 ISA::takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc)
478 {
479  tc = new_tc;
480  setupThreadContext();
481 }
482 
483 RegVal
484 ISA::readMiscRegNoEffect(int misc_reg) const
485 {
486  assert(misc_reg < NumMiscRegs);
487 
488  const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
489  const auto &map = getMiscIndices(misc_reg);
490  int lower = map.first, upper = map.second;
491  // NB!: apply architectural masks according to desired register,
492  // despite possibly getting value from different (mapped) register.
493  auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32))
494  |(miscRegs[upper] << 32));
495  if (val & reg.res0()) {
496  DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n",
497  miscRegName[misc_reg], val & reg.res0());
498  }
499  if ((val & reg.res1()) != reg.res1()) {
500  DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n",
501  miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1());
502  }
503  return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao
504 }
505 
506 
507 RegVal
508 ISA::readMiscReg(int misc_reg)
509 {
510  CPSR cpsr = 0;
511  PCState pc = 0;
512  SCR scr = 0;
513 
514  if (misc_reg == MISCREG_CPSR) {
515  cpsr = miscRegs[misc_reg];
516  pc = tc->pcState();
517  cpsr.j = pc.jazelle() ? 1 : 0;
518  cpsr.t = pc.thumb() ? 1 : 0;
519  return cpsr;
520  }
521 
522 #ifndef NDEBUG
523  if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
524  if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
525  warn("Unimplemented system register %s read.\n",
526  miscRegName[misc_reg]);
527  else
528  panic("Unimplemented system register %s read.\n",
529  miscRegName[misc_reg]);
530  }
531 #endif
532  misc_reg = redirectRegVHE(tc, misc_reg);
533 
534  switch (unflattenMiscReg(misc_reg)) {
535  case MISCREG_HCR:
536  case MISCREG_HCR2:
537  if (!haveVirtualization)
538  return 0;
539  break;
540  case MISCREG_CPACR:
541  {
542  const uint32_t ones = (uint32_t)(-1);
543  CPACR cpacrMask = 0;
544  // Only cp10, cp11, and ase are implemented, nothing else should
545  // be readable? (straight copy from the write code)
546  cpacrMask.cp10 = ones;
547  cpacrMask.cp11 = ones;
548  cpacrMask.asedis = ones;
549 
550  // Security Extensions may limit the readability of CPACR
551  if (haveSecurity) {
552  scr = readMiscRegNoEffect(MISCREG_SCR);
553  cpsr = readMiscRegNoEffect(MISCREG_CPSR);
554  if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
555  NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
556  // NB: Skipping the full loop, here
557  if (!nsacr.cp10) cpacrMask.cp10 = 0;
558  if (!nsacr.cp11) cpacrMask.cp11 = 0;
559  }
560  }
561  RegVal val = readMiscRegNoEffect(MISCREG_CPACR);
562  val &= cpacrMask;
563  DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n",
564  miscRegName[misc_reg], val);
565  return val;
566  }
567  case MISCREG_MPIDR:
568  case MISCREG_MPIDR_EL1:
569  return readMPIDR(system, tc);
570  case MISCREG_VMPIDR:
571  case MISCREG_VMPIDR_EL2:
572  // top bit defined as RES1
573  return readMiscRegNoEffect(misc_reg) | 0x80000000;
574  case MISCREG_ID_AFR0: // not implemented, so alias MIDR
575  case MISCREG_REVIDR: // not implemented, so alias MIDR
576  case MISCREG_MIDR:
577  cpsr = readMiscRegNoEffect(MISCREG_CPSR);
578  scr = readMiscRegNoEffect(MISCREG_SCR);
579  if ((cpsr.mode == MODE_HYP) || isSecure(tc)) {
580  return readMiscRegNoEffect(misc_reg);
581  } else {
582  return readMiscRegNoEffect(MISCREG_VPIDR);
583  }
584  break;
585  case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI
586  case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI
587  case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI
588  case MISCREG_AIDR: // AUX ID set to 0
589  case MISCREG_TCMTR: // No TCM's
590  return 0;
591 
592  case MISCREG_CLIDR:
593  warn_once("The clidr register always reports 0 caches.\n");
594  warn_once("clidr LoUIS field of 0b001 to match current "
595  "ARM implementations.\n");
596  return 0x00200000;
597  case MISCREG_CCSIDR:
598  warn_once("The ccsidr register isn't implemented and "
599  "always reads as 0.\n");
600  break;
601  case MISCREG_CTR: // AArch32, ARMv7, top bit set
602  case MISCREG_CTR_EL0: // AArch64
603  {
604  //all caches have the same line size in gem5
605  //4 byte words in ARM
606  unsigned lineSizeWords =
607  tc->getSystemPtr()->cacheLineSize() / 4;
608  unsigned log2LineSizeWords = 0;
609 
610  while (lineSizeWords >>= 1) {
611  ++log2LineSizeWords;
612  }
613 
614  CTR ctr = 0;
615  //log2 of minimun i-cache line size (words)
616  ctr.iCacheLineSize = log2LineSizeWords;
617  //b11 - gem5 uses pipt
618  ctr.l1IndexPolicy = 0x3;
619  //log2 of minimum d-cache line size (words)
620  ctr.dCacheLineSize = log2LineSizeWords;
621  //log2 of max reservation size (words)
622  ctr.erg = log2LineSizeWords;
623  //log2 of max writeback size (words)
624  ctr.cwg = log2LineSizeWords;
625  //b100 - gem5 format is ARMv7
626  ctr.format = 0x4;
627 
628  return ctr;
629  }
630  case MISCREG_ACTLR:
631  warn("Not doing anything for miscreg ACTLR\n");
632  break;
633 
634  case MISCREG_PMXEVTYPER_PMCCFILTR:
635  case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
636  case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
637  case MISCREG_PMCR ... MISCREG_PMOVSSET:
638  return pmu->readMiscReg(misc_reg);
639 
640  case MISCREG_CPSR_Q:
641  panic("shouldn't be reading this register seperately\n");
642  case MISCREG_FPSCR_QC:
643  return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
644  case MISCREG_FPSCR_EXC:
645  return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
646  case MISCREG_FPSR:
647  {
648  const uint32_t ones = (uint32_t)(-1);
649  FPSCR fpscrMask = 0;
650  fpscrMask.ioc = ones;
651  fpscrMask.dzc = ones;
652  fpscrMask.ofc = ones;
653  fpscrMask.ufc = ones;
654  fpscrMask.ixc = ones;
655  fpscrMask.idc = ones;
656  fpscrMask.qc = ones;
657  fpscrMask.v = ones;
658  fpscrMask.c = ones;
659  fpscrMask.z = ones;
660  fpscrMask.n = ones;
661  return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
662  }
663  case MISCREG_FPCR:
664  {
665  const uint32_t ones = (uint32_t)(-1);
666  FPSCR fpscrMask = 0;
667  fpscrMask.len = ones;
668  fpscrMask.fz16 = ones;
669  fpscrMask.stride = ones;
670  fpscrMask.rMode = ones;
671  fpscrMask.fz = ones;
672  fpscrMask.dn = ones;
673  fpscrMask.ahp = ones;
674  return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
675  }
676  case MISCREG_NZCV:
677  {
678  CPSR cpsr = 0;
679  cpsr.nz = tc->readCCReg(CCREG_NZ);
680  cpsr.c = tc->readCCReg(CCREG_C);
681  cpsr.v = tc->readCCReg(CCREG_V);
682  return cpsr;
683  }
684  case MISCREG_DAIF:
685  {
686  CPSR cpsr = 0;
687  cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif;
688  return cpsr;
689  }
690  case MISCREG_SP_EL0:
691  {
692  return tc->readIntReg(INTREG_SP0);
693  }
694  case MISCREG_SP_EL1:
695  {
696  return tc->readIntReg(INTREG_SP1);
697  }
698  case MISCREG_SP_EL2:
699  {
700  return tc->readIntReg(INTREG_SP2);
701  }
702  case MISCREG_SPSEL:
703  {
704  return miscRegs[MISCREG_CPSR] & 0x1;
705  }
706  case MISCREG_CURRENTEL:
707  {
708  return miscRegs[MISCREG_CPSR] & 0xc;
709  }
710  case MISCREG_PAN:
711  {
712  return miscRegs[MISCREG_CPSR] & 0x400000;
713  }
714  case MISCREG_L2CTLR:
715  {
716  // mostly unimplemented, just set NumCPUs field from sim and return
717  L2CTLR l2ctlr = 0;
718  // b00:1CPU to b11:4CPUs
719  l2ctlr.numCPUs = tc->getSystemPtr()->threads.size() - 1;
720  return l2ctlr;
721  }
722  case MISCREG_DBGDIDR:
723  /* For now just implement the version number.
724  * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
725  */
726  return 0x5 << 16;
727  case MISCREG_DBGDSCRint:
728  return readMiscRegNoEffect(MISCREG_DBGDSCRint);
729  case MISCREG_ISR:
730  {
731  auto ic = dynamic_cast<ArmISA::Interrupts *>(
732  tc->getCpuPtr()->getInterruptController(tc->threadId()));
733  return ic->getISR(
734  readMiscRegNoEffect(MISCREG_HCR),
735  readMiscRegNoEffect(MISCREG_CPSR),
736  readMiscRegNoEffect(MISCREG_SCR));
737  }
738  case MISCREG_ISR_EL1:
739  {
740  auto ic = dynamic_cast<ArmISA::Interrupts *>(
741  tc->getCpuPtr()->getInterruptController(tc->threadId()));
742  return ic->getISR(
743  readMiscRegNoEffect(MISCREG_HCR_EL2),
744  readMiscRegNoEffect(MISCREG_CPSR),
745  readMiscRegNoEffect(MISCREG_SCR_EL3));
746  }
747  case MISCREG_DCZID_EL0:
748  return 0x04; // DC ZVA clear 64-byte chunks
749  case MISCREG_HCPTR:
750  {
751  RegVal val = readMiscRegNoEffect(misc_reg);
752  // The trap bit associated with CP14 is defined as RAZ
753  val &= ~(1 << 14);
754  // If a CP bit in NSACR is 0 then the corresponding bit in
755  // HCPTR is RAO/WI
756  bool secure_lookup = haveSecurity && isSecure(tc);
757  if (!secure_lookup) {
758  RegVal mask = readMiscRegNoEffect(MISCREG_NSACR);
759  val |= (mask ^ 0x7FFF) & 0xBFFF;
760  }
761  // Set the bits for unimplemented coprocessors to RAO/WI
762  val |= 0x33FF;
763  return (val);
764  }
765  case MISCREG_HDFAR: // alias for secure DFAR
766  return readMiscRegNoEffect(MISCREG_DFAR_S);
767  case MISCREG_HIFAR: // alias for secure IFAR
768  return readMiscRegNoEffect(MISCREG_IFAR_S);
769 
770  case MISCREG_ID_PFR0:
771  // !ThumbEE | !Jazelle | Thumb | ARM
772  return 0x00000031;
773  case MISCREG_ID_PFR1:
774  { // Timer | Virti | !M Profile | TrustZone | ARMv4
775  bool haveTimer = (system->getGenericTimer() != NULL);
776  return 0x00000001
777  | (haveSecurity ? 0x00000010 : 0x0)
778  | (haveVirtualization ? 0x00001000 : 0x0)
779  | (haveTimer ? 0x00010000 : 0x0);
780  }
781  case MISCREG_ID_AA64PFR0_EL1:
782  return 0x0000000000000002 | // AArch{64,32} supported at EL0
783  0x0000000000000020 | // EL1
784  (haveVirtualization ? 0x0000000000000200 : 0) | // EL2
785  (haveSecurity ? 0x0000000000002000 : 0) | // EL3
786  (haveSVE ? 0x0000000100000000 : 0) | // SVE
787  (haveSecEL2 ? 0x0000001000000000 : 0) | // SecEL2
788  (gicv3CpuInterface ? 0x0000000001000000 : 0);
789  case MISCREG_ID_AA64PFR1_EL1:
790  return 0; // bits [63:0] RES0 (reserved for future use)
791 
792  // Generic Timer registers
793  case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
794  case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
795  return getGenericTimer().readMiscReg(misc_reg);
796 
797  case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15:
798  case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3:
799  case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
800  return getGICv3CPUInterface().readMiscReg(misc_reg);
801 
802  default:
803  break;
804 
805  }
806  return readMiscRegNoEffect(misc_reg);
807 }
808 
809 void
810 ISA::setMiscRegNoEffect(int misc_reg, RegVal val)
811 {
812  assert(misc_reg < NumMiscRegs);
813 
814  const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
815  const auto &map = getMiscIndices(misc_reg);
816  int lower = map.first, upper = map.second;
817 
818  auto v = (val & ~reg.wi()) | reg.rao();
819  if (upper > 0) {
820  miscRegs[lower] = bits(v, 31, 0);
821  miscRegs[upper] = bits(v, 63, 32);
822  DPRINTF(MiscRegs, "Writing MiscReg %s (%d %d:%d) : %#x\n",
823  miscRegName[misc_reg], misc_reg, lower, upper, v);
824  } else {
825  miscRegs[lower] = v;
826  DPRINTF(MiscRegs, "Writing MiscReg %s (%d %d) : %#x\n",
827  miscRegName[misc_reg], misc_reg, lower, v);
828  }
829 }
830 
831 void
832 ISA::setMiscReg(int misc_reg, RegVal val)
833 {
834 
835  RegVal newVal = val;
836  bool secure_lookup;
837  SCR scr;
838 
839  if (misc_reg == MISCREG_CPSR) {
840  updateRegMap(val);
841 
842 
843  CPSR old_cpsr = miscRegs[MISCREG_CPSR];
844  int old_mode = old_cpsr.mode;
845  CPSR cpsr = val;
846  if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) {
847  getITBPtr(tc)->invalidateMiscReg();
848  getDTBPtr(tc)->invalidateMiscReg();
849  }
850 
851  if (cpsr.pan != old_cpsr.pan) {
852  getDTBPtr(tc)->invalidateMiscReg();
853  }
854 
855  DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
856  miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
857  PCState pc = tc->pcState();
858  pc.nextThumb(cpsr.t);
859  pc.nextJazelle(cpsr.j);
860  pc.illegalExec(cpsr.il == 1);
861  selfDebug->setDebugMask(cpsr.d == 1);
862 
863  tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits() >> 7) - 1);
864 
865  // Follow slightly different semantics if a CheckerCPU object
866  // is connected
867  CheckerCPU *checker = tc->getCheckerCpuPtr();
868  if (checker) {
869  tc->pcStateNoRecord(pc);
870  } else {
871  tc->pcState(pc);
872  }
873  } else {
874 #ifndef NDEBUG
875  if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
876  if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
877  warn("Unimplemented system register %s write with %#x.\n",
878  miscRegName[misc_reg], val);
879  else
880  panic("Unimplemented system register %s write with %#x.\n",
881  miscRegName[misc_reg], val);
882  }
883 #endif
884  misc_reg = redirectRegVHE(tc, misc_reg);
885 
886  switch (unflattenMiscReg(misc_reg)) {
887  case MISCREG_CPACR:
888  {
889 
890  const uint32_t ones = (uint32_t)(-1);
891  CPACR cpacrMask = 0;
892  // Only cp10, cp11, and ase are implemented, nothing else should
893  // be writable
894  cpacrMask.cp10 = ones;
895  cpacrMask.cp11 = ones;
896  cpacrMask.asedis = ones;
897 
898  // Security Extensions may limit the writability of CPACR
899  if (haveSecurity) {
900  scr = readMiscRegNoEffect(MISCREG_SCR);
901  CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
902  if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
903  NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
904  // NB: Skipping the full loop, here
905  if (!nsacr.cp10) cpacrMask.cp10 = 0;
906  if (!nsacr.cp11) cpacrMask.cp11 = 0;
907  }
908  }
909 
910  RegVal old_val = readMiscRegNoEffect(MISCREG_CPACR);
911  newVal &= cpacrMask;
912  newVal |= old_val & ~cpacrMask;
913  DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
914  miscRegName[misc_reg], newVal);
915  }
916  break;
917  case MISCREG_CPACR_EL1:
918  {
919  const uint32_t ones = (uint32_t)(-1);
920  CPACR cpacrMask = 0;
921  cpacrMask.tta = ones;
922  cpacrMask.fpen = ones;
923  if (haveSVE) {
924  cpacrMask.zen = ones;
925  }
926  newVal &= cpacrMask;
927  DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
928  miscRegName[misc_reg], newVal);
929  }
930  break;
931  case MISCREG_CPTR_EL2:
932  {
933  const uint32_t ones = (uint32_t)(-1);
934  CPTR cptrMask = 0;
935  cptrMask.tcpac = ones;
936  cptrMask.tta = ones;
937  cptrMask.tfp = ones;
938  if (haveSVE) {
939  cptrMask.tz = ones;
940  }
941  newVal &= cptrMask;
942  cptrMask = 0;
943  cptrMask.res1_13_12_el2 = ones;
944  cptrMask.res1_7_0_el2 = ones;
945  if (!haveSVE) {
946  cptrMask.res1_8_el2 = ones;
947  }
948  cptrMask.res1_9_el2 = ones;
949  newVal |= cptrMask;
950  DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
951  miscRegName[misc_reg], newVal);
952  }
953  break;
954  case MISCREG_CPTR_EL3:
955  {
956  const uint32_t ones = (uint32_t)(-1);
957  CPTR cptrMask = 0;
958  cptrMask.tcpac = ones;
959  cptrMask.tta = ones;
960  cptrMask.tfp = ones;
961  if (haveSVE) {
962  cptrMask.ez = ones;
963  }
964  newVal &= cptrMask;
965  DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
966  miscRegName[misc_reg], newVal);
967  }
968  break;
969  case MISCREG_CSSELR:
970  warn_once("The csselr register isn't implemented.\n");
971  return;
972 
973  case MISCREG_DC_ZVA_Xt:
974  warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
975  return;
976 
977  case MISCREG_FPSCR:
978  {
979  const uint32_t ones = (uint32_t)(-1);
980  FPSCR fpscrMask = 0;
981  fpscrMask.ioc = ones;
982  fpscrMask.dzc = ones;
983  fpscrMask.ofc = ones;
984  fpscrMask.ufc = ones;
985  fpscrMask.ixc = ones;
986  fpscrMask.idc = ones;
987  fpscrMask.ioe = ones;
988  fpscrMask.dze = ones;
989  fpscrMask.ofe = ones;
990  fpscrMask.ufe = ones;
991  fpscrMask.ixe = ones;
992  fpscrMask.ide = ones;
993  fpscrMask.len = ones;
994  fpscrMask.fz16 = ones;
995  fpscrMask.stride = ones;
996  fpscrMask.rMode = ones;
997  fpscrMask.fz = ones;
998  fpscrMask.dn = ones;
999  fpscrMask.ahp = ones;
1000  fpscrMask.qc = ones;
1001  fpscrMask.v = ones;
1002  fpscrMask.c = ones;
1003  fpscrMask.z = ones;
1004  fpscrMask.n = ones;
1005  newVal = (newVal & (uint32_t)fpscrMask) |
1006  (readMiscRegNoEffect(MISCREG_FPSCR) &
1007  ~(uint32_t)fpscrMask);
1008  tc->getDecoderPtr()->setContext(newVal);
1009  }
1010  break;
1011  case MISCREG_FPSR:
1012  {
1013  const uint32_t ones = (uint32_t)(-1);
1014  FPSCR fpscrMask = 0;
1015  fpscrMask.ioc = ones;
1016  fpscrMask.dzc = ones;
1017  fpscrMask.ofc = ones;
1018  fpscrMask.ufc = ones;
1019  fpscrMask.ixc = ones;
1020  fpscrMask.idc = ones;
1021  fpscrMask.qc = ones;
1022  fpscrMask.v = ones;
1023  fpscrMask.c = ones;
1024  fpscrMask.z = ones;
1025  fpscrMask.n = ones;
1026  newVal = (newVal & (uint32_t)fpscrMask) |
1027  (readMiscRegNoEffect(MISCREG_FPSCR) &
1028  ~(uint32_t)fpscrMask);
1029  misc_reg = MISCREG_FPSCR;
1030  }
1031  break;
1032  case MISCREG_FPCR:
1033  {
1034  const uint32_t ones = (uint32_t)(-1);
1035  FPSCR fpscrMask = 0;
1036  fpscrMask.len = ones;
1037  fpscrMask.fz16 = ones;
1038  fpscrMask.stride = ones;
1039  fpscrMask.rMode = ones;
1040  fpscrMask.fz = ones;
1041  fpscrMask.dn = ones;
1042  fpscrMask.ahp = ones;
1043  newVal = (newVal & (uint32_t)fpscrMask) |
1044  (readMiscRegNoEffect(MISCREG_FPSCR) &
1045  ~(uint32_t)fpscrMask);
1046  misc_reg = MISCREG_FPSCR;
1047  }
1048  break;
1049  case MISCREG_CPSR_Q:
1050  {
1051  assert(!(newVal & ~CpsrMaskQ));
1052  newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal;
1053  misc_reg = MISCREG_CPSR;
1054  }
1055  break;
1056  case MISCREG_FPSCR_QC:
1057  {
1058  newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
1059  (newVal & FpscrQcMask);
1060  misc_reg = MISCREG_FPSCR;
1061  }
1062  break;
1063  case MISCREG_FPSCR_EXC:
1064  {
1065  newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
1066  (newVal & FpscrExcMask);
1067  misc_reg = MISCREG_FPSCR;
1068  }
1069  break;
1070  case MISCREG_FPEXC:
1071  {
1072  // vfpv3 architecture, section B.6.1 of DDI04068
1073  // bit 29 - valid only if fpexc[31] is 0
1074  const uint32_t fpexcMask = 0x60000000;
1075  newVal = (newVal & fpexcMask) |
1076  (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask);
1077  }
1078  break;
1079  case MISCREG_HCR2:
1080  if (!haveVirtualization)
1081  return;
1082  break;
1083  case MISCREG_HCR:
1084  {
1085  const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
1086  selfDebug->setenableTDETGE((HCR)val, mdcr);
1087  if (!haveVirtualization)
1088  return;
1089  }
1090  break;
1091 
1092  case MISCREG_HDCR:
1093  {
1094  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1095  selfDebug->setenableTDETGE(hcr, (HDCR)val);
1096  }
1097  break;
1098  case MISCREG_DBGOSLAR:
1099  {
1100  OSL r = tc->readMiscReg(MISCREG_DBGOSLSR);
1101  const uint32_t temp = (val == 0xC5ACCE55)? 0x1 : 0x0;
1102  selfDebug->updateOSLock((RegVal) temp);
1103  r.oslk = bits(temp,0);
1104  tc->setMiscReg(MISCREG_DBGOSLSR, r);
1105  }
1106  break;
1107  case MISCREG_DBGBCR0:
1108  selfDebug->updateDBGBCR(0, val);
1109  break;
1110  case MISCREG_DBGBCR1:
1111  selfDebug->updateDBGBCR(1, val);
1112  break;
1113  case MISCREG_DBGBCR2:
1114  selfDebug->updateDBGBCR(2, val);
1115  break;
1116  case MISCREG_DBGBCR3:
1117  selfDebug->updateDBGBCR(3, val);
1118  break;
1119  case MISCREG_DBGBCR4:
1120  selfDebug->updateDBGBCR(4, val);
1121  break;
1122  case MISCREG_DBGBCR5:
1123  selfDebug->updateDBGBCR(5, val);
1124  break;
1125  case MISCREG_DBGBCR6:
1126  selfDebug->updateDBGBCR(6, val);
1127  break;
1128  case MISCREG_DBGBCR7:
1129  selfDebug->updateDBGBCR(7, val);
1130  break;
1131  case MISCREG_DBGBCR8:
1132  selfDebug->updateDBGBCR(8, val);
1133  break;
1134  case MISCREG_DBGBCR9:
1135  selfDebug->updateDBGBCR(9, val);
1136  break;
1137  case MISCREG_DBGBCR10:
1138  selfDebug->updateDBGBCR(10, val);
1139  break;
1140  case MISCREG_DBGBCR11:
1141  selfDebug->updateDBGBCR(11, val);
1142  break;
1143  case MISCREG_DBGBCR12:
1144  selfDebug->updateDBGBCR(12, val);
1145  break;
1146  case MISCREG_DBGBCR13:
1147  selfDebug->updateDBGBCR(13, val);
1148  break;
1149  case MISCREG_DBGBCR14:
1150  selfDebug->updateDBGBCR(14, val);
1151  break;
1152  case MISCREG_DBGBCR15:
1153  selfDebug->updateDBGBCR(15, val);
1154  break;
1155  case MISCREG_DBGWCR0:
1156  selfDebug->updateDBGWCR(0, val);
1157  break;
1158  case MISCREG_DBGWCR1:
1159  selfDebug->updateDBGWCR(1, val);
1160  break;
1161  case MISCREG_DBGWCR2:
1162  selfDebug->updateDBGWCR(2, val);
1163  break;
1164  case MISCREG_DBGWCR3:
1165  selfDebug->updateDBGWCR(3, val);
1166  break;
1167  case MISCREG_DBGWCR4:
1168  selfDebug->updateDBGWCR(4, val);
1169  break;
1170  case MISCREG_DBGWCR5:
1171  selfDebug->updateDBGWCR(5, val);
1172  break;
1173  case MISCREG_DBGWCR6:
1174  selfDebug->updateDBGWCR(6, val);
1175  break;
1176  case MISCREG_DBGWCR7:
1177  selfDebug->updateDBGWCR(7, val);
1178  break;
1179  case MISCREG_DBGWCR8:
1180  selfDebug->updateDBGWCR(8, val);
1181  break;
1182  case MISCREG_DBGWCR9:
1183  selfDebug->updateDBGWCR(9, val);
1184  break;
1185  case MISCREG_DBGWCR10:
1186  selfDebug->updateDBGWCR(10, val);
1187  break;
1188  case MISCREG_DBGWCR11:
1189  selfDebug->updateDBGWCR(11, val);
1190  break;
1191  case MISCREG_DBGWCR12:
1192  selfDebug->updateDBGWCR(12, val);
1193  break;
1194  case MISCREG_DBGWCR13:
1195  selfDebug->updateDBGWCR(13, val);
1196  break;
1197  case MISCREG_DBGWCR14:
1198  selfDebug->updateDBGWCR(14, val);
1199  break;
1200  case MISCREG_DBGWCR15:
1201  selfDebug->updateDBGWCR(15, val);
1202  break;
1203 
1204  case MISCREG_MDCR_EL2:
1205  {
1206  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1207  selfDebug->setenableTDETGE(hcr, (HDCR)val);
1208  }
1209  break;
1210  case MISCREG_SDCR:
1211  case MISCREG_MDCR_EL3:
1212  {
1213  selfDebug->setbSDD(val);
1214  }
1215  break;
1216  case MISCREG_DBGDSCRext:
1217  {
1218  selfDebug->setMDBGen(val);
1219  DBGDS32 r = tc->readMiscReg(MISCREG_DBGDSCRint);
1220  DBGDS32 v = val;
1221  r.moe = v.moe;
1222  r.udccdis = v.udccdis;
1223  r.mdbgen = v.mdbgen;
1224  tc->setMiscReg(MISCREG_DBGDSCRint, r);
1225  r = tc->readMiscReg(MISCREG_DBGDSCRint);
1226  }
1227 
1228  break;
1229  case MISCREG_MDSCR_EL1:
1230  {
1231  selfDebug->setMDSCRvals(val);
1232  }
1233  break;
1234 
1235  case MISCREG_OSLAR_EL1:
1236  {
1237  selfDebug->updateOSLock(val);
1238  OSL r = tc->readMiscReg(MISCREG_OSLSR_EL1);
1239  r.oslk = bits(val, 0);
1240  r.oslm_3 = 1;
1241  tc->setMiscReg(MISCREG_OSLSR_EL1, r);
1242  }
1243  break;
1244 
1245  case MISCREG_DBGBCR0_EL1:
1246  selfDebug->updateDBGBCR(0, val);
1247  break;
1248  case MISCREG_DBGBCR1_EL1:
1249  selfDebug->updateDBGBCR(1, val);
1250  break;
1251  case MISCREG_DBGBCR2_EL1:
1252  selfDebug->updateDBGBCR(2, val);
1253  break;
1254  case MISCREG_DBGBCR3_EL1:
1255  selfDebug->updateDBGBCR(3, val);
1256  break;
1257  case MISCREG_DBGBCR4_EL1:
1258  selfDebug->updateDBGBCR(4, val);
1259  break;
1260  case MISCREG_DBGBCR5_EL1:
1261  selfDebug->updateDBGBCR(5, val);
1262  break;
1263  case MISCREG_DBGBCR6_EL1:
1264  selfDebug->updateDBGBCR(6, val);
1265  break;
1266  case MISCREG_DBGBCR7_EL1:
1267  selfDebug->updateDBGBCR(7, val);
1268  break;
1269  case MISCREG_DBGBCR8_EL1:
1270  selfDebug->updateDBGBCR(8, val);
1271  break;
1272  case MISCREG_DBGBCR9_EL1:
1273  selfDebug->updateDBGBCR(9, val);
1274  break;
1275  case MISCREG_DBGBCR10_EL1:
1276  selfDebug->updateDBGBCR(10, val);
1277  break;
1278  case MISCREG_DBGBCR11_EL1:
1279  selfDebug->updateDBGBCR(11, val);
1280  break;
1281  case MISCREG_DBGBCR12_EL1:
1282  selfDebug->updateDBGBCR(12, val);
1283  break;
1284  case MISCREG_DBGBCR13_EL1:
1285  selfDebug->updateDBGBCR(13, val);
1286  break;
1287  case MISCREG_DBGBCR14_EL1:
1288  selfDebug->updateDBGBCR(14, val);
1289  break;
1290  case MISCREG_DBGBCR15_EL1:
1291  selfDebug->updateDBGBCR(15, val);
1292  break;
1293  case MISCREG_DBGWCR0_EL1:
1294  selfDebug->updateDBGWCR(0, val);
1295  break;
1296  case MISCREG_DBGWCR1_EL1:
1297  selfDebug->updateDBGWCR(1, val);
1298  break;
1299  case MISCREG_DBGWCR2_EL1:
1300  selfDebug->updateDBGWCR(2, val);
1301  break;
1302  case MISCREG_DBGWCR3_EL1:
1303  selfDebug->updateDBGWCR(3, val);
1304  break;
1305  case MISCREG_DBGWCR4_EL1:
1306  selfDebug->updateDBGWCR(4, val);
1307  break;
1308  case MISCREG_DBGWCR5_EL1:
1309  selfDebug->updateDBGWCR(5, val);
1310  break;
1311  case MISCREG_DBGWCR6_EL1:
1312  selfDebug->updateDBGWCR(6, val);
1313  break;
1314  case MISCREG_DBGWCR7_EL1:
1315  selfDebug->updateDBGWCR(7, val);
1316  break;
1317  case MISCREG_DBGWCR8_EL1:
1318  selfDebug->updateDBGWCR(8, val);
1319  break;
1320  case MISCREG_DBGWCR9_EL1:
1321  selfDebug->updateDBGWCR(9, val);
1322  break;
1323  case MISCREG_DBGWCR10_EL1:
1324  selfDebug->updateDBGWCR(10, val);
1325  break;
1326  case MISCREG_DBGWCR11_EL1:
1327  selfDebug->updateDBGWCR(11, val);
1328  break;
1329  case MISCREG_DBGWCR12_EL1:
1330  selfDebug->updateDBGWCR(12, val);
1331  break;
1332  case MISCREG_DBGWCR13_EL1:
1333  selfDebug->updateDBGWCR(13, val);
1334  break;
1335  case MISCREG_DBGWCR14_EL1:
1336  selfDebug->updateDBGWCR(14, val);
1337  break;
1338  case MISCREG_DBGWCR15_EL1:
1339  selfDebug->updateDBGWCR(15, val);
1340  break;
1341  case MISCREG_IFSR:
1342  {
1343  // ARM ARM (ARM DDI 0406C.b) B4.1.96
1344  const uint32_t ifsrMask =
1345  mask(31, 13) | mask(11, 11) | mask(8, 6);
1346  newVal = newVal & ~ifsrMask;
1347  }
1348  break;
1349  case MISCREG_DFSR:
1350  {
1351  // ARM ARM (ARM DDI 0406C.b) B4.1.52
1352  const uint32_t dfsrMask = mask(31, 14) | mask(8, 8);
1353  newVal = newVal & ~dfsrMask;
1354  }
1355  break;
1356  case MISCREG_AMAIR0:
1357  case MISCREG_AMAIR1:
1358  {
1359  // ARM ARM (ARM DDI 0406C.b) B4.1.5
1360  // Valid only with LPAE
1361  if (!haveLPAE)
1362  return;
1363  DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal);
1364  }
1365  break;
1366  case MISCREG_SCR:
1367  getITBPtr(tc)->invalidateMiscReg();
1368  getDTBPtr(tc)->invalidateMiscReg();
1369  break;
1370  case MISCREG_SCTLR:
1371  {
1372  DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
1373  scr = readMiscRegNoEffect(MISCREG_SCR);
1374 
1375  MiscRegIndex sctlr_idx;
1376  if (haveSecurity && !highestELIs64 && !scr.ns) {
1377  sctlr_idx = MISCREG_SCTLR_S;
1378  } else {
1379  sctlr_idx = MISCREG_SCTLR_NS;
1380  }
1381 
1382  SCTLR sctlr = miscRegs[sctlr_idx];
1383  SCTLR new_sctlr = newVal;
1384  new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization;
1385  miscRegs[sctlr_idx] = (RegVal)new_sctlr;
1386  getITBPtr(tc)->invalidateMiscReg();
1387  getDTBPtr(tc)->invalidateMiscReg();
1388  }
1389  case MISCREG_MIDR:
1390  case MISCREG_ID_PFR0:
1391  case MISCREG_ID_PFR1:
1392  case MISCREG_ID_DFR0:
1393  case MISCREG_ID_MMFR0:
1394  case MISCREG_ID_MMFR1:
1395  case MISCREG_ID_MMFR2:
1396  case MISCREG_ID_MMFR3:
1397  case MISCREG_ID_ISAR0:
1398  case MISCREG_ID_ISAR1:
1399  case MISCREG_ID_ISAR2:
1400  case MISCREG_ID_ISAR3:
1401  case MISCREG_ID_ISAR4:
1402  case MISCREG_ID_ISAR5:
1403 
1404  case MISCREG_MPIDR:
1405  case MISCREG_FPSID:
1406  case MISCREG_TLBTR:
1407  case MISCREG_MVFR0:
1408  case MISCREG_MVFR1:
1409 
1410  case MISCREG_ID_AA64AFR0_EL1:
1411  case MISCREG_ID_AA64AFR1_EL1:
1412  case MISCREG_ID_AA64DFR0_EL1:
1413  case MISCREG_ID_AA64DFR1_EL1:
1414  case MISCREG_ID_AA64ISAR0_EL1:
1415  case MISCREG_ID_AA64ISAR1_EL1:
1416  case MISCREG_ID_AA64MMFR0_EL1:
1417  case MISCREG_ID_AA64MMFR1_EL1:
1418  case MISCREG_ID_AA64MMFR2_EL1:
1419  case MISCREG_ID_AA64PFR0_EL1:
1420  case MISCREG_ID_AA64PFR1_EL1:
1421  // ID registers are constants.
1422  return;
1423 
1424  // TLB Invalidate All
1425  case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
1426  {
1427  assert32();
1428  scr = readMiscReg(MISCREG_SCR);
1429 
1430  TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1431  tlbiOp(tc);
1432  return;
1433  }
1434  // TLB Invalidate All, Inner Shareable
1435  case MISCREG_TLBIALLIS:
1436  {
1437  assert32();
1438  scr = readMiscReg(MISCREG_SCR);
1439 
1440  TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1441  tlbiOp.broadcast(tc);
1442  return;
1443  }
1444  // Instruction TLB Invalidate All
1445  case MISCREG_ITLBIALL:
1446  {
1447  assert32();
1448  scr = readMiscReg(MISCREG_SCR);
1449 
1450  ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1451  tlbiOp(tc);
1452  return;
1453  }
1454  // Data TLB Invalidate All
1455  case MISCREG_DTLBIALL:
1456  {
1457  assert32();
1458  scr = readMiscReg(MISCREG_SCR);
1459 
1460  DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1461  tlbiOp(tc);
1462  return;
1463  }
1464  // TLB Invalidate by VA
1465  // mcr tlbimval(is) is invalidating all matching entries
1466  // regardless of the level of lookup, since in gem5 we cache
1467  // in the tlb the last level of lookup only.
1468  case MISCREG_TLBIMVA:
1469  case MISCREG_TLBIMVAL:
1470  {
1471  assert32();
1472  scr = readMiscReg(MISCREG_SCR);
1473 
1474  TLBIMVA tlbiOp(EL1,
1475  haveSecurity && !scr.ns,
1476  mbits(newVal, 31, 12),
1477  bits(newVal, 7,0));
1478 
1479  tlbiOp(tc);
1480  return;
1481  }
1482  // TLB Invalidate by VA, Inner Shareable
1483  case MISCREG_TLBIMVAIS:
1484  case MISCREG_TLBIMVALIS:
1485  {
1486  assert32();
1487  scr = readMiscReg(MISCREG_SCR);
1488 
1489  TLBIMVA tlbiOp(EL1,
1490  haveSecurity && !scr.ns,
1491  mbits(newVal, 31, 12),
1492  bits(newVal, 7,0));
1493 
1494  tlbiOp.broadcast(tc);
1495  return;
1496  }
1497  // TLB Invalidate by ASID match
1498  case MISCREG_TLBIASID:
1499  {
1500  assert32();
1501  scr = readMiscReg(MISCREG_SCR);
1502 
1503  TLBIASID tlbiOp(EL1,
1504  haveSecurity && !scr.ns,
1505  bits(newVal, 7,0));
1506 
1507  tlbiOp(tc);
1508  return;
1509  }
1510  // TLB Invalidate by ASID match, Inner Shareable
1511  case MISCREG_TLBIASIDIS:
1512  {
1513  assert32();
1514  scr = readMiscReg(MISCREG_SCR);
1515 
1516  TLBIASID tlbiOp(EL1,
1517  haveSecurity && !scr.ns,
1518  bits(newVal, 7,0));
1519 
1520  tlbiOp.broadcast(tc);
1521  return;
1522  }
1523  // mcr tlbimvaal(is) is invalidating all matching entries
1524  // regardless of the level of lookup, since in gem5 we cache
1525  // in the tlb the last level of lookup only.
1526  // TLB Invalidate by VA, All ASID
1527  case MISCREG_TLBIMVAA:
1528  case MISCREG_TLBIMVAAL:
1529  {
1530  assert32();
1531  scr = readMiscReg(MISCREG_SCR);
1532 
1533  TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1534  mbits(newVal, 31,12));
1535 
1536  tlbiOp(tc);
1537  return;
1538  }
1539  // TLB Invalidate by VA, All ASID, Inner Shareable
1540  case MISCREG_TLBIMVAAIS:
1541  case MISCREG_TLBIMVAALIS:
1542  {
1543  assert32();
1544  scr = readMiscReg(MISCREG_SCR);
1545 
1546  TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1547  mbits(newVal, 31,12));
1548 
1549  tlbiOp.broadcast(tc);
1550  return;
1551  }
1552  // mcr tlbimvalh(is) is invalidating all matching entries
1553  // regardless of the level of lookup, since in gem5 we cache
1554  // in the tlb the last level of lookup only.
1555  // TLB Invalidate by VA, Hyp mode
1556  case MISCREG_TLBIMVAH:
1557  case MISCREG_TLBIMVALH:
1558  {
1559  assert32();
1560  scr = readMiscReg(MISCREG_SCR);
1561 
1562  TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns,
1563  mbits(newVal, 31,12));
1564 
1565  tlbiOp(tc);
1566  return;
1567  }
1568  // TLB Invalidate by VA, Hyp mode, Inner Shareable
1569  case MISCREG_TLBIMVAHIS:
1570  case MISCREG_TLBIMVALHIS:
1571  {
1572  assert32();
1573  scr = readMiscReg(MISCREG_SCR);
1574 
1575  TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns,
1576  mbits(newVal, 31,12));
1577 
1578  tlbiOp.broadcast(tc);
1579  return;
1580  }
1581  // mcr tlbiipas2l(is) is invalidating all matching entries
1582  // regardless of the level of lookup, since in gem5 we cache
1583  // in the tlb the last level of lookup only.
1584  // TLB Invalidate by Intermediate Physical Address, Stage 2
1585  case MISCREG_TLBIIPAS2:
1586  case MISCREG_TLBIIPAS2L:
1587  {
1588  assert32();
1589  scr = readMiscReg(MISCREG_SCR);
1590 
1591  TLBIIPA tlbiOp(EL1,
1592  haveSecurity && !scr.ns,
1593  static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1594 
1595  tlbiOp(tc);
1596  return;
1597  }
1598  // TLB Invalidate by Intermediate Physical Address, Stage 2,
1599  // Inner Shareable
1600  case MISCREG_TLBIIPAS2IS:
1601  case MISCREG_TLBIIPAS2LIS:
1602  {
1603  assert32();
1604  scr = readMiscReg(MISCREG_SCR);
1605 
1606  TLBIIPA tlbiOp(EL1,
1607  haveSecurity && !scr.ns,
1608  static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1609 
1610  tlbiOp.broadcast(tc);
1611  return;
1612  }
1613  // Instruction TLB Invalidate by VA
1614  case MISCREG_ITLBIMVA:
1615  {
1616  assert32();
1617  scr = readMiscReg(MISCREG_SCR);
1618 
1619  ITLBIMVA tlbiOp(EL1,
1620  haveSecurity && !scr.ns,
1621  mbits(newVal, 31, 12),
1622  bits(newVal, 7,0));
1623 
1624  tlbiOp(tc);
1625  return;
1626  }
1627  // Data TLB Invalidate by VA
1628  case MISCREG_DTLBIMVA:
1629  {
1630  assert32();
1631  scr = readMiscReg(MISCREG_SCR);
1632 
1633  DTLBIMVA tlbiOp(EL1,
1634  haveSecurity && !scr.ns,
1635  mbits(newVal, 31, 12),
1636  bits(newVal, 7,0));
1637 
1638  tlbiOp(tc);
1639  return;
1640  }
1641  // Instruction TLB Invalidate by ASID match
1642  case MISCREG_ITLBIASID:
1643  {
1644  assert32();
1645  scr = readMiscReg(MISCREG_SCR);
1646 
1647  ITLBIASID tlbiOp(EL1,
1648  haveSecurity && !scr.ns,
1649  bits(newVal, 7,0));
1650 
1651  tlbiOp(tc);
1652  return;
1653  }
1654  // Data TLB Invalidate by ASID match
1655  case MISCREG_DTLBIASID:
1656  {
1657  assert32();
1658  scr = readMiscReg(MISCREG_SCR);
1659 
1660  DTLBIASID tlbiOp(EL1,
1661  haveSecurity && !scr.ns,
1662  bits(newVal, 7,0));
1663 
1664  tlbiOp(tc);
1665  return;
1666  }
1667  // TLB Invalidate All, Non-Secure Non-Hyp
1668  case MISCREG_TLBIALLNSNH:
1669  {
1670  assert32();
1671 
1672  TLBIALLN tlbiOp(EL1);
1673  tlbiOp(tc);
1674  return;
1675  }
1676  // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable
1677  case MISCREG_TLBIALLNSNHIS:
1678  {
1679  assert32();
1680 
1681  TLBIALLN tlbiOp(EL1);
1682  tlbiOp.broadcast(tc);
1683  return;
1684  }
1685  // TLB Invalidate All, Hyp mode
1686  case MISCREG_TLBIALLH:
1687  {
1688  assert32();
1689 
1690  TLBIALLN tlbiOp(EL2);
1691  tlbiOp(tc);
1692  return;
1693  }
1694  // TLB Invalidate All, Hyp mode, Inner Shareable
1695  case MISCREG_TLBIALLHIS:
1696  {
1697  assert32();
1698 
1699  TLBIALLN tlbiOp(EL2);
1700  tlbiOp.broadcast(tc);
1701  return;
1702  }
1703  // AArch64 TLB Invalidate All, EL3
1704  case MISCREG_TLBI_ALLE3:
1705  {
1706  assert64();
1707 
1708  TLBIALL tlbiOp(EL3, true);
1709  tlbiOp(tc);
1710  return;
1711  }
1712  // AArch64 TLB Invalidate All, EL3, Inner Shareable
1713  case MISCREG_TLBI_ALLE3IS:
1714  {
1715  assert64();
1716 
1717  TLBIALL tlbiOp(EL3, true);
1718  tlbiOp.broadcast(tc);
1719  return;
1720  }
1721  // AArch64 TLB Invalidate All, EL2, Inner Shareable
1722  case MISCREG_TLBI_ALLE2:
1723  case MISCREG_TLBI_ALLE2IS:
1724  {
1725  assert64();
1726  scr = readMiscReg(MISCREG_SCR);
1727 
1728  TLBIALL tlbiOp(EL2, haveSecurity && !scr.ns);
1729  tlbiOp(tc);
1730  return;
1731  }
1732  // AArch64 TLB Invalidate All, EL1
1733  case MISCREG_TLBI_ALLE1:
1734  case MISCREG_TLBI_VMALLS12E1:
1735  // @todo: handle VMID and stage 2 to enable Virtualization
1736  {
1737  assert64();
1738  scr = readMiscReg(MISCREG_SCR);
1739 
1740  TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1741  tlbiOp(tc);
1742  return;
1743  }
1744  case MISCREG_TLBI_VMALLE1:
1745  // @todo: handle VMID and stage 2 to enable Virtualization
1746  {
1747  assert64();
1748  scr = readMiscReg(MISCREG_SCR);
1749 
1750  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1751  bool is_host = (hcr.tge && hcr.e2h);
1752  ExceptionLevel target_el = is_host ? EL2 : EL1;
1753  TLBIALL tlbiOp(target_el, haveSecurity && !scr.ns);
1754  tlbiOp(tc);
1755  return;
1756  }
1757  // AArch64 TLB Invalidate All, EL1, Inner Shareable
1758  case MISCREG_TLBI_ALLE1IS:
1759  case MISCREG_TLBI_VMALLS12E1IS:
1760  // @todo: handle VMID and stage 2 to enable Virtualization
1761  {
1762  assert64();
1763  scr = readMiscReg(MISCREG_SCR);
1764 
1765  TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1766  tlbiOp.broadcast(tc);
1767  return;
1768  }
1769  case MISCREG_TLBI_VMALLE1IS:
1770  // @todo: handle VMID and stage 2 to enable Virtualization
1771  {
1772  assert64();
1773  scr = readMiscReg(MISCREG_SCR);
1774 
1775  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1776  bool is_host = (hcr.tge && hcr.e2h);
1777  ExceptionLevel target_el = is_host ? EL2 : EL1;
1778  TLBIALL tlbiOp(target_el, haveSecurity && !scr.ns);
1779  tlbiOp.broadcast(tc);
1780  return;
1781  }
1782  // VAEx(IS) and VALEx(IS) are the same because TLBs
1783  // only store entries
1784  // from the last level of translation table walks
1785  // @todo: handle VMID to enable Virtualization
1786  // AArch64 TLB Invalidate by VA, EL3
1787  case MISCREG_TLBI_VAE3_Xt:
1788  case MISCREG_TLBI_VALE3_Xt:
1789  {
1790  assert64();
1791 
1792  TLBIMVA tlbiOp(EL3, true,
1793  static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1794  0xbeef);
1795  tlbiOp(tc);
1796  return;
1797  }
1798  // AArch64 TLB Invalidate by VA, EL3, Inner Shareable
1799  case MISCREG_TLBI_VAE3IS_Xt:
1800  case MISCREG_TLBI_VALE3IS_Xt:
1801  {
1802  assert64();
1803 
1804  TLBIMVA tlbiOp(EL3, true,
1805  static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1806  0xbeef);
1807 
1808  tlbiOp.broadcast(tc);
1809  return;
1810  }
1811  // AArch64 TLB Invalidate by VA, EL2
1812  case MISCREG_TLBI_VAE2_Xt:
1813  case MISCREG_TLBI_VALE2_Xt:
1814  {
1815  assert64();
1816  scr = readMiscReg(MISCREG_SCR);
1817 
1818  TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
1819  static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1820  0xbeef);
1821  tlbiOp(tc);
1822  return;
1823  }
1824  // AArch64 TLB Invalidate by VA, EL2, Inner Shareable
1825  case MISCREG_TLBI_VAE2IS_Xt:
1826  case MISCREG_TLBI_VALE2IS_Xt:
1827  {
1828  assert64();
1829  scr = readMiscReg(MISCREG_SCR);
1830 
1831  TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
1832  static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1833  0xbeef);
1834 
1835  tlbiOp.broadcast(tc);
1836  return;
1837  }
1838  // AArch64 TLB Invalidate by VA, EL1
1839  case MISCREG_TLBI_VAE1_Xt:
1840  case MISCREG_TLBI_VALE1_Xt:
1841  {
1842  assert64();
1843  scr = readMiscReg(MISCREG_SCR);
1844  auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1845  bits(newVal, 55, 48);
1846 
1847  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1848  bool is_host = (hcr.tge && hcr.e2h);
1849  ExceptionLevel target_el = is_host ? EL2 : EL1;
1850  TLBIMVA tlbiOp(target_el, haveSecurity && !scr.ns,
1851  static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1852  asid);
1853 
1854  tlbiOp(tc);
1855  return;
1856  }
1857  // AArch64 TLB Invalidate by VA, EL1, Inner Shareable
1858  case MISCREG_TLBI_VAE1IS_Xt:
1859  case MISCREG_TLBI_VALE1IS_Xt:
1860  {
1861  assert64();
1862  scr = readMiscReg(MISCREG_SCR);
1863  auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1864  bits(newVal, 55, 48);
1865 
1866  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1867  bool is_host = (hcr.tge && hcr.e2h);
1868  ExceptionLevel target_el = is_host ? EL2 : EL1;
1869  TLBIMVA tlbiOp(target_el, haveSecurity && !scr.ns,
1870  static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1871  asid);
1872 
1873  tlbiOp.broadcast(tc);
1874  return;
1875  }
1876  // AArch64 TLB Invalidate by ASID, EL1
1877  // @todo: handle VMID to enable Virtualization
1878  case MISCREG_TLBI_ASIDE1_Xt:
1879  {
1880  assert64();
1881  scr = readMiscReg(MISCREG_SCR);
1882  auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1883  bits(newVal, 55, 48);
1884 
1885  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1886  bool is_host = (hcr.tge && hcr.e2h);
1887  ExceptionLevel target_el = is_host ? EL2 : EL1;
1888  TLBIASID tlbiOp(target_el, haveSecurity && !scr.ns, asid);
1889  tlbiOp(tc);
1890  return;
1891  }
1892  // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable
1893  case MISCREG_TLBI_ASIDE1IS_Xt:
1894  {
1895  assert64();
1896  scr = readMiscReg(MISCREG_SCR);
1897  auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1898  bits(newVal, 55, 48);
1899 
1900  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1901  bool is_host = (hcr.tge && hcr.e2h);
1902  ExceptionLevel target_el = is_host ? EL2 : EL1;
1903  TLBIASID tlbiOp(target_el, haveSecurity && !scr.ns, asid);
1904  tlbiOp.broadcast(tc);
1905  return;
1906  }
1907  // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1908  // entries from the last level of translation table walks
1909  // AArch64 TLB Invalidate by VA, All ASID, EL1
1910  case MISCREG_TLBI_VAAE1_Xt:
1911  case MISCREG_TLBI_VAALE1_Xt:
1912  {
1913  assert64();
1914  scr = readMiscReg(MISCREG_SCR);
1915 
1916  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1917  bool is_host = (hcr.tge && hcr.e2h);
1918  ExceptionLevel target_el = is_host ? EL2 : EL1;
1919  TLBIMVAA tlbiOp(target_el, haveSecurity && !scr.ns,
1920  static_cast<Addr>(bits(newVal, 43, 0)) << 12);
1921 
1922  tlbiOp(tc);
1923  return;
1924  }
1925  // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable
1926  case MISCREG_TLBI_VAAE1IS_Xt:
1927  case MISCREG_TLBI_VAALE1IS_Xt:
1928  {
1929  assert64();
1930  scr = readMiscReg(MISCREG_SCR);
1931 
1932  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1933  bool is_host = (hcr.tge && hcr.e2h);
1934  ExceptionLevel target_el = is_host ? EL2 : EL1;
1935  TLBIMVAA tlbiOp(target_el, haveSecurity && !scr.ns,
1936  static_cast<Addr>(bits(newVal, 43, 0)) << 12);
1937 
1938  tlbiOp.broadcast(tc);
1939  return;
1940  }
1941  // AArch64 TLB Invalidate by Intermediate Physical Address,
1942  // Stage 2, EL1
1943  case MISCREG_TLBI_IPAS2E1_Xt:
1944  case MISCREG_TLBI_IPAS2LE1_Xt:
1945  {
1946  assert64();
1947  scr = readMiscReg(MISCREG_SCR);
1948 
1949  TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
1950  static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1951 
1952  tlbiOp(tc);
1953  return;
1954  }
1955  // AArch64 TLB Invalidate by Intermediate Physical Address,
1956  // Stage 2, EL1, Inner Shareable
1957  case MISCREG_TLBI_IPAS2E1IS_Xt:
1958  case MISCREG_TLBI_IPAS2LE1IS_Xt:
1959  {
1960  assert64();
1961  scr = readMiscReg(MISCREG_SCR);
1962 
1963  TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
1964  static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1965 
1966  tlbiOp.broadcast(tc);
1967  return;
1968  }
1969  case MISCREG_ACTLR:
1970  warn("Not doing anything for write of miscreg ACTLR\n");
1971  break;
1972 
1973  case MISCREG_PMXEVTYPER_PMCCFILTR:
1974  case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
1975  case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
1976  case MISCREG_PMCR ... MISCREG_PMOVSSET:
1977  pmu->setMiscReg(misc_reg, newVal);
1978  break;
1979 
1980 
1981  case MISCREG_HSTR: // TJDBX, now redifined to be RES0
1982  {
1983  HSTR hstrMask = 0;
1984  hstrMask.tjdbx = 1;
1985  newVal &= ~((uint32_t) hstrMask);
1986  break;
1987  }
1988  case MISCREG_HCPTR:
1989  {
1990  // If a CP bit in NSACR is 0 then the corresponding bit in
1991  // HCPTR is RAO/WI. Same applies to NSASEDIS
1992  secure_lookup = haveSecurity && isSecure(tc);
1993  if (!secure_lookup) {
1994  RegVal oldValue = readMiscRegNoEffect(MISCREG_HCPTR);
1995  RegVal mask =
1996  (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF;
1997  newVal = (newVal & ~mask) | (oldValue & mask);
1998  }
1999  break;
2000  }
2001  case MISCREG_HDFAR: // alias for secure DFAR
2002  misc_reg = MISCREG_DFAR_S;
2003  break;
2004  case MISCREG_HIFAR: // alias for secure IFAR
2005  misc_reg = MISCREG_IFAR_S;
2006  break;
2007  case MISCREG_ATS1CPR:
2008  addressTranslation(TLB::S1CTran, BaseTLB::Read, 0, val);
2009  return;
2010  case MISCREG_ATS1CPW:
2011  addressTranslation(TLB::S1CTran, BaseTLB::Write, 0, val);
2012  return;
2013  case MISCREG_ATS1CUR:
2014  addressTranslation(TLB::S1CTran, BaseTLB::Read,
2015  TLB::UserMode, val);
2016  return;
2017  case MISCREG_ATS1CUW:
2018  addressTranslation(TLB::S1CTran, BaseTLB::Write,
2019  TLB::UserMode, val);
2020  return;
2021  case MISCREG_ATS12NSOPR:
2022  if (!haveSecurity)
2023  panic("Security Extensions required for ATS12NSOPR");
2024  addressTranslation(TLB::S1S2NsTran, BaseTLB::Read, 0, val);
2025  return;
2026  case MISCREG_ATS12NSOPW:
2027  if (!haveSecurity)
2028  panic("Security Extensions required for ATS12NSOPW");
2029  addressTranslation(TLB::S1S2NsTran, BaseTLB::Write, 0, val);
2030  return;
2031  case MISCREG_ATS12NSOUR:
2032  if (!haveSecurity)
2033  panic("Security Extensions required for ATS12NSOUR");
2034  addressTranslation(TLB::S1S2NsTran, BaseTLB::Read,
2035  TLB::UserMode, val);
2036  return;
2037  case MISCREG_ATS12NSOUW:
2038  if (!haveSecurity)
2039  panic("Security Extensions required for ATS12NSOUW");
2040  addressTranslation(TLB::S1S2NsTran, BaseTLB::Write,
2041  TLB::UserMode, val);
2042  return;
2043  case MISCREG_ATS1HR:
2044  addressTranslation(TLB::HypMode, BaseTLB::Read, 0, val);
2045  return;
2046  case MISCREG_ATS1HW:
2047  addressTranslation(TLB::HypMode, BaseTLB::Write, 0, val);
2048  return;
2049  case MISCREG_TTBCR:
2050  {
2051  TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
2052  const uint32_t ones = (uint32_t)(-1);
2053  TTBCR ttbcrMask = 0;
2054  TTBCR ttbcrNew = newVal;
2055 
2056  // ARM DDI 0406C.b, ARMv7-32
2057  ttbcrMask.n = ones; // T0SZ
2058  if (haveSecurity) {
2059  ttbcrMask.pd0 = ones;
2060  ttbcrMask.pd1 = ones;
2061  }
2062  ttbcrMask.epd0 = ones;
2063  ttbcrMask.irgn0 = ones;
2064  ttbcrMask.orgn0 = ones;
2065  ttbcrMask.sh0 = ones;
2066  ttbcrMask.ps = ones; // T1SZ
2067  ttbcrMask.a1 = ones;
2068  ttbcrMask.epd1 = ones;
2069  ttbcrMask.irgn1 = ones;
2070  ttbcrMask.orgn1 = ones;
2071  ttbcrMask.sh1 = ones;
2072  if (haveLPAE)
2073  ttbcrMask.eae = ones;
2074 
2075  if (haveLPAE && ttbcrNew.eae) {
2076  newVal = newVal & ttbcrMask;
2077  } else {
2078  newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
2079  }
2080  // Invalidate TLB MiscReg
2081  getITBPtr(tc)->invalidateMiscReg();
2082  getDTBPtr(tc)->invalidateMiscReg();
2083  break;
2084  }
2085  case MISCREG_TTBR0:
2086  case MISCREG_TTBR1:
2087  {
2088  TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
2089  if (haveLPAE) {
2090  if (ttbcr.eae) {
2091  // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
2092  // ARMv8 AArch32 bit 63-56 only
2093  uint64_t ttbrMask = mask(63,56) | mask(47,40);
2094  newVal = (newVal & (~ttbrMask));
2095  }
2096  }
2097  // Invalidate TLB MiscReg
2098  getITBPtr(tc)->invalidateMiscReg();
2099  getDTBPtr(tc)->invalidateMiscReg();
2100  break;
2101  }
2102  case MISCREG_SCTLR_EL1:
2103  case MISCREG_CONTEXTIDR:
2104  case MISCREG_PRRR:
2105  case MISCREG_NMRR:
2106  case MISCREG_MAIR0:
2107  case MISCREG_MAIR1:
2108  case MISCREG_DACR:
2109  case MISCREG_VTTBR:
2110  case MISCREG_SCR_EL3:
2111  case MISCREG_TCR_EL1:
2112  case MISCREG_TCR_EL2:
2113  case MISCREG_TCR_EL3:
2114  case MISCREG_SCTLR_EL2:
2115  case MISCREG_SCTLR_EL3:
2116  case MISCREG_HSCTLR:
2117  case MISCREG_TTBR0_EL1:
2118  case MISCREG_TTBR1_EL1:
2119  case MISCREG_TTBR0_EL2:
2120  case MISCREG_TTBR1_EL2:
2121  case MISCREG_TTBR0_EL3:
2122  getITBPtr(tc)->invalidateMiscReg();
2123  getDTBPtr(tc)->invalidateMiscReg();
2124  break;
2125  case MISCREG_HCR_EL2:
2126  {
2127  const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
2128  selfDebug->setenableTDETGE((HCR)val, mdcr);
2129  getITBPtr(tc)->invalidateMiscReg();
2130  getDTBPtr(tc)->invalidateMiscReg();
2131  }
2132  break;
2133  case MISCREG_NZCV:
2134  {
2135  CPSR cpsr = val;
2136 
2137  tc->setCCReg(CCREG_NZ, cpsr.nz);
2138  tc->setCCReg(CCREG_C, cpsr.c);
2139  tc->setCCReg(CCREG_V, cpsr.v);
2140  }
2141  break;
2142  case MISCREG_DAIF:
2143  {
2144  CPSR cpsr = miscRegs[MISCREG_CPSR];
2145  cpsr.daif = (uint8_t) ((CPSR) newVal).daif;
2146  newVal = cpsr;
2147  misc_reg = MISCREG_CPSR;
2148  }
2149  break;
2150  case MISCREG_SP_EL0:
2151  tc->setIntReg(INTREG_SP0, newVal);
2152  break;
2153  case MISCREG_SP_EL1:
2154  tc->setIntReg(INTREG_SP1, newVal);
2155  break;
2156  case MISCREG_SP_EL2:
2157  tc->setIntReg(INTREG_SP2, newVal);
2158  break;
2159  case MISCREG_SPSEL:
2160  {
2161  CPSR cpsr = miscRegs[MISCREG_CPSR];
2162  cpsr.sp = (uint8_t) ((CPSR) newVal).sp;
2163  newVal = cpsr;
2164  misc_reg = MISCREG_CPSR;
2165  }
2166  break;
2167  case MISCREG_CURRENTEL:
2168  {
2169  CPSR cpsr = miscRegs[MISCREG_CPSR];
2170  cpsr.el = (uint8_t) ((CPSR) newVal).el;
2171  newVal = cpsr;
2172  misc_reg = MISCREG_CPSR;
2173  }
2174  break;
2175  case MISCREG_PAN:
2176  {
2177  // PAN is affecting data accesses
2178  getDTBPtr(tc)->invalidateMiscReg();
2179 
2180  CPSR cpsr = miscRegs[MISCREG_CPSR];
2181  cpsr.pan = (uint8_t) ((CPSR) newVal).pan;
2182  newVal = cpsr;
2183  misc_reg = MISCREG_CPSR;
2184  }
2185  break;
2186  case MISCREG_AT_S1E1R_Xt:
2187  addressTranslation64(TLB::S1E1Tran, BaseTLB::Read, 0, val);
2188  return;
2189  case MISCREG_AT_S1E1W_Xt:
2190  addressTranslation64(TLB::S1E1Tran, BaseTLB::Write, 0, val);
2191  return;
2192  case MISCREG_AT_S1E0R_Xt:
2193  addressTranslation64(TLB::S1E0Tran, BaseTLB::Read,
2194  TLB::UserMode, val);
2195  return;
2196  case MISCREG_AT_S1E0W_Xt:
2197  addressTranslation64(TLB::S1E0Tran, BaseTLB::Write,
2198  TLB::UserMode, val);
2199  return;
2200  case MISCREG_AT_S1E2R_Xt:
2201  addressTranslation64(TLB::S1E2Tran, BaseTLB::Read, 0, val);
2202  return;
2203  case MISCREG_AT_S1E2W_Xt:
2204  addressTranslation64(TLB::S1E2Tran, BaseTLB::Write, 0, val);
2205  return;
2206  case MISCREG_AT_S12E1R_Xt:
2207  addressTranslation64(TLB::S12E1Tran, BaseTLB::Read, 0, val);
2208  return;
2209  case MISCREG_AT_S12E1W_Xt:
2210  addressTranslation64(TLB::S12E1Tran, BaseTLB::Write, 0, val);
2211  return;
2212  case MISCREG_AT_S12E0R_Xt:
2213  addressTranslation64(TLB::S12E0Tran, BaseTLB::Read,
2214  TLB::UserMode, val);
2215  return;
2216  case MISCREG_AT_S12E0W_Xt:
2217  addressTranslation64(TLB::S12E0Tran, BaseTLB::Write,
2218  TLB::UserMode, val);
2219  return;
2220  case MISCREG_AT_S1E3R_Xt:
2221  addressTranslation64(TLB::S1E3Tran, BaseTLB::Read, 0, val);
2222  return;
2223  case MISCREG_AT_S1E3W_Xt:
2224  addressTranslation64(TLB::S1E3Tran, BaseTLB::Write, 0, val);
2225  return;
2226  case MISCREG_SPSR_EL3:
2227  case MISCREG_SPSR_EL2:
2228  case MISCREG_SPSR_EL1:
2229  {
2230  RegVal spsr_mask = havePAN ?
2231  ~(0x2 << 22) : ~(0x3 << 22);
2232 
2233  newVal = val & spsr_mask;
2234  break;
2235  }
2236  case MISCREG_L2CTLR:
2237  warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
2238  miscRegName[misc_reg], uint32_t(val));
2239  break;
2240 
2241  // Generic Timer registers
2242  case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
2243  case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
2244  getGenericTimer().setMiscReg(misc_reg, newVal);
2245  break;
2246  case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15:
2247  case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3:
2248  case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
2249  getGICv3CPUInterface().setMiscReg(misc_reg, newVal);
2250  return;
2251  case MISCREG_ZCR_EL3:
2252  case MISCREG_ZCR_EL2:
2253  case MISCREG_ZCR_EL1:
2254  tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits() >> 7) - 1);
2255  break;
2256  }
2257  }
2258  setMiscRegNoEffect(misc_reg, newVal);
2259 }
2260 
2261 BaseISADevice &
2262 ISA::getGenericTimer()
2263 {
2264  // We only need to create an ISA interface the first time we try
2265  // to access the timer.
2266  if (timer)
2267  return *timer.get();
2268 
2269  assert(system);
2270  GenericTimer *generic_timer(system->getGenericTimer());
2271  if (!generic_timer) {
2272  panic("Trying to get a generic timer from a system that hasn't "
2273  "been configured to use a generic timer.\n");
2274  }
2275 
2276  timer.reset(new GenericTimerISA(*generic_timer, tc->contextId()));
2277  timer->setThreadContext(tc);
2278 
2279  return *timer.get();
2280 }
2281 
2282 BaseISADevice &
2283 ISA::getGICv3CPUInterface()
2284 {
2285  panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!");
2286  return *gicv3CpuInterface.get();
2287 }
2288 
2289 unsigned
2290 ISA::getCurSveVecLenInBits() const
2291 {
2292  if (!FullSystem) {
2293  return sveVL * 128;
2294  }
2295 
2296  panic_if(!tc,
2297  "A ThreadContext is needed to determine the SVE vector length "
2298  "in full-system mode");
2299 
2300  CPSR cpsr = miscRegs[MISCREG_CPSR];
2301  ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
2302 
2303  unsigned len = 0;
2304 
2305  if (el == EL1 || (el == EL0 && !ELIsInHost(tc, el))) {
2306  len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL1]).len;
2307  }
2308 
2309  if (el == EL2 || (el == EL0 && ELIsInHost(tc, el))) {
2310  len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len;
2311  } else if (haveVirtualization && !isSecure(tc) &&
2312  (el == EL0 || el == EL1)) {
2313  len = std::min(
2314  len,
2315  static_cast<unsigned>(
2316  static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len));
2317  }
2318 
2319  if (el == EL3) {
2320  len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len;
2321  } else if (haveSecurity) {
2322  len = std::min(
2323  len,
2324  static_cast<unsigned>(
2325  static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len));
2326  }
2327 
2328  len = std::min(len, sveVL - 1);
2329 
2330  return (len + 1) * 128;
2331 }
2332 
2333 void
2334 ISA::zeroSveVecRegUpperPart(VecRegContainer &vc, unsigned eCount)
2335 {
2336  auto vv = vc.as<uint64_t>();
2337  for (int i = 2; i < eCount; ++i) {
2338  vv[i] = 0;
2339  }
2340 }
2341 
2342 void
2343 ISA::addressTranslation64(TLB::ArmTranslationType tran_type,
2344  BaseTLB::Mode mode, Request::Flags flags, RegVal val)
2345 {
2346  // If we're in timing mode then doing the translation in
2347  // functional mode then we're slightly distorting performance
2348  // results obtained from simulations. The translation should be
2349  // done in the same mode the core is running in. NOTE: This
2350  // can't be an atomic translation because that causes problems
2351  // with unexpected atomic snoop requests.
2352  warn_once("Doing AT (address translation) in functional mode! Fix Me!\n");
2353 
2354  auto req = std::make_shared<Request>(
2355  val, 0, flags, Request::funcRequestorId,
2356  tc->pcState().pc(), tc->contextId());
2357 
2358  Fault fault = getDTBPtr(tc)->translateFunctional(
2359  req, tc, mode, tran_type);
2360 
2361  PAR par = 0;
2362  if (fault == NoFault) {
2363  Addr paddr = req->getPaddr();
2364  uint64_t attr = getDTBPtr(tc)->getAttr();
2365  uint64_t attr1 = attr >> 56;
2366  if (!attr1 || attr1 ==0x44) {
2367  attr |= 0x100;
2368  attr &= ~ uint64_t(0x80);
2369  }
2370  par = (paddr & mask(47, 12)) | attr;
2371  DPRINTF(MiscRegs,
2372  "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
2373  val, par);
2374  } else {
2375  ArmFault *arm_fault = static_cast<ArmFault *>(fault.get());
2376  arm_fault->update(tc);
2377  // Set fault bit and FSR
2378  FSR fsr = arm_fault->getFsr(tc);
2379 
2380  par.f = 1; // F bit
2381  par.fst = fsr.status; // FST
2382  par.ptw = (arm_fault->iss() >> 7) & 0x1; // S1PTW
2383  par.s = arm_fault->isStage2() ? 1 : 0; // S
2384 
2385  DPRINTF(MiscRegs,
2386  "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
2387  val, fsr, par);
2388  }
2389  setMiscRegNoEffect(MISCREG_PAR_EL1, par);
2390  return;
2391 }
2392 
2393 void
2394 ISA::addressTranslation(TLB::ArmTranslationType tran_type,
2395  BaseTLB::Mode mode, Request::Flags flags, RegVal val)
2396 {
2397  // If we're in timing mode then doing the translation in
2398  // functional mode then we're slightly distorting performance
2399  // results obtained from simulations. The translation should be
2400  // done in the same mode the core is running in. NOTE: This
2401  // can't be an atomic translation because that causes problems
2402  // with unexpected atomic snoop requests.
2403  warn_once("Doing AT (address translation) in functional mode! Fix Me!\n");
2404 
2405  auto req = std::make_shared<Request>(
2406  val, 0, flags, Request::funcRequestorId,
2407  tc->pcState().pc(), tc->contextId());
2408 
2409  Fault fault = getDTBPtr(tc)->translateFunctional(
2410  req, tc, mode, tran_type);
2411 
2412  PAR par = 0;
2413  if (fault == NoFault) {
2414  Addr paddr = req->getPaddr();
2415  TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
2416  HCR hcr = readMiscRegNoEffect(MISCREG_HCR);
2417 
2418  uint8_t max_paddr_bit = 0;
2419  if (haveLPAE && (ttbcr.eae || tran_type & TLB::HypMode ||
2420  ((tran_type & TLB::S1S2NsTran) && hcr.vm) )) {
2421 
2422  max_paddr_bit = 39;
2423  } else {
2424  max_paddr_bit = 31;
2425  }
2426 
2427  par = (paddr & mask(max_paddr_bit, 12)) |
2428  (getDTBPtr(tc)->getAttr());
2429 
2430  DPRINTF(MiscRegs,
2431  "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
2432  val, par);
2433  } else {
2434  ArmFault *arm_fault = static_cast<ArmFault *>(fault.get());
2435  arm_fault->update(tc);
2436  // Set fault bit and FSR
2437  FSR fsr = arm_fault->getFsr(tc);
2438 
2439  par.f = 0x1; // F bit
2440  par.lpae = fsr.lpae;
2441  par.ptw = (arm_fault->iss() >> 7) & 0x1;
2442  par.s = arm_fault->isStage2() ? 1 : 0;
2443 
2444  if (par.lpae) {
2445  // LPAE - rearange fault status
2446  par.fst = fsr.status;
2447  } else {
2448  // VMSA - rearange fault status
2449  par.fs4_0 = fsr.fsLow | (fsr.fsHigh << 5);
2450  par.fs5 = fsr.ext;
2451  }
2452  DPRINTF(MiscRegs,
2453  "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
2454  val, fsr, par);
2455  }
2456  setMiscRegNoEffect(MISCREG_PAR, par);
2457  return;
2458 }
2459 
2460 ISA::MiscRegLUTEntryInitializer::chain
2461 ISA::MiscRegLUTEntryInitializer::highest(ArmSystem *const sys) const
2462 {
2463  switch (FullSystem ? sys->highestEL() : EL1) {
2464  case EL0:
2465  case EL1: priv(); break;
2466  case EL2: hyp(); break;
2467  case EL3: mon(); break;
2468  }
2469  return *this;
2470 }
2471 
2472 } // namespace ArmISA
2473 
2474 ArmISA::ISA *
2475 ArmISAParams::create()
2476 {
2477  return new ArmISA::ISA(this);
2478 }
ArmISA::ISA::setupThreadContext
void setupThreadContext()
Definition: isa.cc:456
ArmISA::MISCREG_TLBIALLIS
@ MISCREG_TLBIALLIS
Definition: miscregs.hh:315
ArmISA::SelfDebug
Definition: self_debug.hh:273
ArmISA::MISCREG_AT_S1E3R_Xt
@ MISCREG_AT_S1E3R_Xt
Definition: miscregs.hh:668
ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gic_v3_cpu_interface.hh
ArmISA::MISCREG_DBGBCR3_EL1
@ MISCREG_DBGBCR3_EL1
Definition: miscregs.hh:471
ArmISA::MISCREG_DBGDSCRint
@ MISCREG_DBGDSCRint
Definition: miscregs.hh:92
ArmISA::MISCREG_DBGOSLAR
@ MISCREG_DBGOSLAR
Definition: miscregs.hh:183
ArmISA::MISCREG_ID_AA64MMFR2_EL1
@ MISCREG_ID_AA64MMFR2_EL1
Definition: miscregs.hh:814
ArmISA::ELIsInHost
bool ELIsInHost(ThreadContext *tc, ExceptionLevel el)
Returns true if the current exception level el is executing a Host OS or an application of a Host OS ...
Definition: utility.cc:392
GenericTimerISA
Definition: generic_timer.hh:378
ArmISA::MISCREG_ICC_IGRPEN1_EL3
@ MISCREG_ICC_IGRPEN1_EL3
Definition: miscregs.hh:874
ArmISA::MISCREG_TLBI_IPAS2E1IS_Xt
@ MISCREG_TLBI_IPAS2E1IS_Xt
Definition: miscregs.hh:682
ArmISA::MISCREG_ID_AA64AFR1_EL1
@ MISCREG_ID_AA64AFR1_EL1
Definition: miscregs.hh:558
ArmISA::MISCREG_ATS12NSOPR
@ MISCREG_ATS12NSOPR
Definition: miscregs.hh:302
ArmISA::encodePhysAddrRange64
uint8_t encodePhysAddrRange64(int pa_size)
Returns the encoding corresponding to the specified n.
Definition: utility.cc:1404
ArmISA::MISCREG_AT_S1E3W_Xt
@ MISCREG_AT_S1E3W_Xt
Definition: miscregs.hh:669
ArmISA::MISCREG_DBGBCR9
@ MISCREG_DBGBCR9
Definition: miscregs.hh:127
ArmISA::MISCREG_VBAR_S
@ MISCREG_VBAR_S
Definition: miscregs.hh:387
ArmISA::MISCREG_ATS1HR
@ MISCREG_ATS1HR
Definition: miscregs.hh:313
ArmISA::ISA::getMiscIndices
std::pair< int, int > getMiscIndices(int misc_reg) const
Definition: isa.hh:785
ArmISA::MODE_HYP
@ MODE_HYP
Definition: types.hh:642
ArmISA::MISCREG_TLBIMVAAIS
@ MISCREG_TLBIMVAAIS
Definition: miscregs.hh:318
ArmISA::MISCREG_DBGBCR2_EL1
@ MISCREG_DBGBCR2_EL1
Definition: miscregs.hh:470
ArmISA::ISA::initializeMiscRegMetadata
void initializeMiscRegMetadata()
Definition: miscregs.cc:3384
warn
#define warn(...)
Definition: logging.hh:239
ArmISA::MISCREG_ID_AA64ISAR1_EL1
@ MISCREG_ID_AA64ISAR1_EL1
Definition: miscregs.hh:560
ArmISA::MISCREG_IMPLEMENTED
@ MISCREG_IMPLEMENTED
Definition: miscregs.hh:1092
ArmISA::SelfDebug::init
void init(ThreadContext *tc)
Definition: self_debug.cc:330
ArmISA::MISCREG_DBGWCR4_EL1
@ MISCREG_DBGWCR4_EL1
Definition: miscregs.hh:504
ArmISA::EL2
@ EL2
Definition: types.hh:624
ArmISA::ISA::clear
void clear()
Definition: isa.cc:130
ArmISA::MISCREG_ZCR_EL2
@ MISCREG_ZCR_EL2
Definition: miscregs.hh:1048
ArmISA::MISCREG_DBGWCR7_EL1
@ MISCREG_DBGWCR7_EL1
Definition: miscregs.hh:507
ArmISA::TLB::UserMode
@ UserMode
Definition: tlb.hh:115
ArmISA::MISCREG_HCPTR
@ MISCREG_HCPTR
Definition: miscregs.hh:245
system.hh
ArmISA::MISCREG_TTBR0
@ MISCREG_TTBR0
Definition: miscregs.hh:248
ArmISA::MISCREG_DBGBCR14
@ MISCREG_DBGBCR14
Definition: miscregs.hh:132
ArmISA::MISCREG_CTR_EL0
@ MISCREG_CTR_EL0
Definition: miscregs.hh:567
ArmISA::CCREG_NZ
@ CCREG_NZ
Definition: ccregs.hh:45
BaseTLB::Read
@ Read
Definition: tlb.hh:57
ArmISA::daif
Bitfield< 9, 6 > daif
Definition: miscregs_types.hh:66
ArmISA::MISCREG_TLBIMVAHIS
@ MISCREG_TLBIMVAHIS
Definition: miscregs.hh:336
ArmISA::MISCREG_PMEVCNTR0_EL0
@ MISCREG_PMEVCNTR0_EL0
Definition: miscregs.hh:782
ArmISA::MISCREG_DBGWCR0
@ MISCREG_DBGWCR0
Definition: miscregs.hh:150
ArmSystem::haveCrypto
bool haveCrypto() const
Returns true if this system implements the Crypto Extension.
Definition: system.hh:175
ArmISA::MISCREG_OSLAR_EL1
@ MISCREG_OSLAR_EL1
Definition: miscregs.hh:522
ArmSystem::physAddrRange
uint8_t physAddrRange() const
Returns the supported physical address range in bits.
Definition: system.hh:251
ArmISA::MISCREG_DBGWCR9_EL1
@ MISCREG_DBGWCR9_EL1
Definition: miscregs.hh:509
ArmISA::MISCREG_DBGWCR0_EL1
@ MISCREG_DBGWCR0_EL1
Definition: miscregs.hh:500
ArmISA::MISCREG_TLBI_VAALE1IS_Xt
@ MISCREG_TLBI_VAALE1IS_Xt
Definition: miscregs.hh:675
ArmISA::BaseISADevice
Base class for devices that use the MiscReg interfaces.
Definition: isa_device.hh:58
ArmISA::MISCREG_AIDR
@ MISCREG_AIDR
Definition: miscregs.hh:223
ArmISA::preUnflattenMiscReg
void preUnflattenMiscReg()
Definition: miscregs.cc:1347
ArmISA::TLB::ArmTranslationType
ArmTranslationType
Definition: tlb.hh:118
ArmISA::ArmFault::iss
virtual uint32_t iss() const =0
ArmSystem::highestELIs64
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:204
ArmISA::MISCREG_PAR_EL1
@ MISCREG_PAR_EL1
Definition: miscregs.hh:647
ArmISA::ISA::miscRegs
RegVal miscRegs[NumMiscRegs]
Definition: isa.hh:412
ArmSystem::resetAddr
Addr resetAddr() const
Returns the reset address if the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:219
ArmISA::MISCREG_DBGWCR11_EL1
@ MISCREG_DBGWCR11_EL1
Definition: miscregs.hh:511
warn_once
#define warn_once(...)
Definition: logging.hh:243
ArmISA::MISCREG_ID_AA64ZFR0_EL1
@ MISCREG_ID_AA64ZFR0_EL1
Definition: miscregs.hh:1046
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
ArmISA::MISCREG_ID_AA64ISAR0_EL1
@ MISCREG_ID_AA64ISAR0_EL1
Definition: miscregs.hh:559
ArmISA::MISCREG_VMPIDR_EL2
@ MISCREG_VMPIDR_EL2
Definition: miscregs.hh:570
ArmISA::MISCREG_CNTFRQ_EL0
@ MISCREG_CNTFRQ_EL0
Definition: miscregs.hh:745
ArmISA::ISA::haveLPAE
bool haveLPAE
Definition: isa.hh:90
Loader::Arm
@ Arm
Definition: object_file.hh:52
ArmISA::EL0
@ EL0
Definition: types.hh:622
ArmISA::MISCREG_TLBIMVAL
@ MISCREG_TLBIMVAL
Definition: miscregs.hh:331
ArmISA::MISCREG_DBGWCR14_EL1
@ MISCREG_DBGWCR14_EL1
Definition: miscregs.hh:514
ArmISA::MISCREG_TTBCR_NS
@ MISCREG_TTBCR_NS
Definition: miscregs.hh:255
ArmISA::MISCREG_TLBI_VAAE1IS_Xt
@ MISCREG_TLBI_VAAE1IS_Xt
Definition: miscregs.hh:673
ArmISA::MODE_EL3H
@ MODE_EL3H
Definition: types.hh:635
ArmISA::MISCREG_ITLBIMVA
@ MISCREG_ITLBIMVA
Definition: miscregs.hh:322
Flags< FlagsType >
ArmISA::MISCREG_DBGBCR15_EL1
@ MISCREG_DBGBCR15_EL1
Definition: miscregs.hh:483
ArmISA::MISCREG_DBGWCR2_EL1
@ MISCREG_DBGWCR2_EL1
Definition: miscregs.hh:502
ArmISA::SelfDebug::setMDBGen
void setMDBGen(RegVal val)
Definition: self_debug.hh:387
ArmISA::ISA::gicv3CpuInterface
std::unique_ptr< BaseISADevice > gicv3CpuInterface
Definition: isa.hh:85
ArmISA::MISCREG_ID_MMFR0
@ MISCREG_ID_MMFR0
Definition: miscregs.hh:211
ArmISA::MISCREG_JMCR
@ MISCREG_JMCR
Definition: miscregs.hh:198
ArmISA::MISCREG_DBGWCR15_EL1
@ MISCREG_DBGWCR15_EL1
Definition: miscregs.hh:515
ArmISA::BaseISADevice::setThreadContext
virtual void setThreadContext(ThreadContext *tc)
Definition: isa_device.hh:65
ArmISA::MISCREG_CURRENTEL
@ MISCREG_CURRENTEL
Definition: miscregs.hh:610
ArmISA::MISCREG_ATS1CPR
@ MISCREG_ATS1CPR
Definition: miscregs.hh:298
ArmISA::MISCREG_FPSR
@ MISCREG_FPSR
Definition: miscregs.hh:614
ArmISA::MISCREG_JIDR
@ MISCREG_JIDR
Definition: miscregs.hh:195
ArmISA::MISCREG_TTBR0_EL1
@ MISCREG_TTBR0_EL1
Definition: miscregs.hh:589
ArmISA::MISCREG_ICH_AP0R0_EL2
@ MISCREG_ICH_AP0R0_EL2
Definition: miscregs.hh:877
ArmISA::MISCREG_DAIF
@ MISCREG_DAIF
Definition: miscregs.hh:612
ArmISA::MISCREG_TLBIMVA
@ MISCREG_TLBIMVA
Definition: miscregs.hh:328
ArmISA::MISCREG_ID_MMFR2
@ MISCREG_ID_MMFR2
Definition: miscregs.hh:213
ArmISA::MISCREG_DCZID_EL0
@ MISCREG_DCZID_EL0
Definition: miscregs.hh:568
ThreadContext::setIntReg
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
ArmISA::MISCREG_TLBIMVAIS
@ MISCREG_TLBIMVAIS
Definition: miscregs.hh:316
ArmISA::MISCREG_TLBI_VMALLE1
@ MISCREG_TLBI_VMALLE1
Definition: miscregs.hh:676
BaseTLB::Mode
Mode
Definition: tlb.hh:57
ArmISA::MISCREG_CLIDR
@ MISCREG_CLIDR
Definition: miscregs.hh:222
ArmISA::MISCREG_REVIDR
@ MISCREG_REVIDR
Definition: miscregs.hh:206
ArmISA::MISCREG_DBGBCR5_EL1
@ MISCREG_DBGBCR5_EL1
Definition: miscregs.hh:473
ArmISA::MISCREG_TLBI_VMALLS12E1
@ MISCREG_TLBI_VMALLS12E1
Definition: miscregs.hh:695
ArmISA::MISCREG_TLBI_VALE3IS_Xt
@ MISCREG_TLBI_VALE3IS_Xt
Definition: miscregs.hh:698
ArmISA::MISCREG_ICC_PMR_EL1
@ MISCREG_ICC_PMR_EL1
Definition: miscregs.hh:829
ArmISA::SelfDebug::updateDBGWCR
void updateDBGWCR(int index, DBGWCR val)
Definition: self_debug.hh:411
ArmISA::MISCREG_PMOVSSET_EL0
@ MISCREG_PMOVSSET_EL0
Definition: miscregs.hh:717
ArmISA::MISCREG_CPACR
@ MISCREG_CPACR
Definition: miscregs.hh:235
ArmISA::ISA::setMiscReg
void setMiscReg(int misc_reg, RegVal val)
Definition: isa.cc:832
ArmISA::TLB::HypMode
@ HypMode
Definition: tlb.hh:121
ArmISA::MISCREG_NMRR_NS
@ MISCREG_NMRR_NS
Definition: miscregs.hh:370
ArmISA::MISCREG_TLBI_ALLE3
@ MISCREG_TLBI_ALLE3
Definition: miscregs.hh:699
ArmISA::MISCREG_MVFR1
@ MISCREG_MVFR1
Definition: miscregs.hh:69
ArmISA::TLBIMVA
TLB Invalidate by VA.
Definition: tlbi_op.hh:190
ArmISA::HTMCheckpoint
Definition: htm.hh:54
ArmISA::CCREG_V
@ CCREG_V
Definition: ccregs.hh:47
ArmISA::MISCREG_MDCR_EL3
@ MISCREG_MDCR_EL3
Definition: miscregs.hh:588
ArmISA::MISCREG_TLBI_ASIDE1IS_Xt
@ MISCREG_TLBI_ASIDE1IS_Xt
Definition: miscregs.hh:672
ArmISA::MISCREG_FPSCR_QC
@ MISCREG_FPSCR_QC
Definition: miscregs.hh:77
ArmISA::MISCREG_DBGDSCRext
@ MISCREG_DBGDSCRext
Definition: miscregs.hh:99
ArmSystem::haveSVE
bool haveSVE() const
Returns true if SVE is implemented (ARMv8)
Definition: system.hh:231
ArmISA::MISCREG_TLBI_IPAS2LE1IS_Xt
@ MISCREG_TLBI_IPAS2LE1IS_Xt
Definition: miscregs.hh:683
CheckerCPU
CheckerCPU class.
Definition: cpu.hh:85
ArmISA::DTLBIALL
Data TLB Invalidate All.
Definition: tlbi_op.hh:105
ArmISA::MISCREG_AT_S1E0W_Xt
@ MISCREG_AT_S1E0W_Xt
Definition: miscregs.hh:654
ArmISA::MISCREG_FPSCR_EXC
@ MISCREG_FPSCR_EXC
Definition: miscregs.hh:76
ArmISA::ArmFault::isStage2
virtual bool isStage2() const
Definition: faults.hh:249
ArmISA::TLBIOp::broadcast
void broadcast(ThreadContext *tc)
Broadcast the TLB Invalidate operation to all TLBs in the Arm system.
Definition: tlbi_op.hh:69
tlb.hh
std::vector
STL vector class.
Definition: stl.hh:37
ArmISA::TLB::getAttr
uint64_t getAttr() const
Definition: tlb.hh:349
ArmISA::MISCREG_DBGWCR12_EL1
@ MISCREG_DBGWCR12_EL1
Definition: miscregs.hh:512
ArmISA::ISA::redirectRegVHE
int redirectRegVHE(ThreadContext *tc, int misc_reg)
Returns the enconcing equivalent when VHE is implemented and HCR_EL2.E2H is enabled and executing at ...
Definition: isa.hh:708
GenericTimer
Definition: generic_timer.hh:276
ArmISA::EL3
@ EL3
Definition: types.hh:625
ArmISA::MISCREG_DBGBCR8
@ MISCREG_DBGBCR8
Definition: miscregs.hh:126
ArmISA::MISCREG_ISR_EL1
@ MISCREG_ISR_EL1
Definition: miscregs.hh:731
FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:132
ArmISA::MISCREG_TLBIMVAA
@ MISCREG_TLBIMVAA
Definition: miscregs.hh:330
ArmISA::MISCREG_ID_ISAR3
@ MISCREG_ID_ISAR3
Definition: miscregs.hh:218
ArmISA::MISCREG_ISR
@ MISCREG_ISR
Definition: miscregs.hh:390
ArmISA::MISCREG_TCR_EL2
@ MISCREG_TCR_EL2
Definition: miscregs.hh:596
ArmISA::MISCREG_ID_MMFR1
@ MISCREG_ID_MMFR1
Definition: miscregs.hh:212
ArmISA::ISA
Definition: isa.hh:65
ArmISA::TLB::S1S2NsTran
@ S1S2NsTran
Definition: tlb.hh:124
ArmISA::MISCREG_CCSIDR
@ MISCREG_CCSIDR
Definition: miscregs.hh:221
ArmSystem::getGIC
BaseGic * getGIC() const
Get a pointer to the system's GIC.
Definition: system.hh:197
mbits
T mbits(T val, int first, int last)
Mask off the given bits in place like bits() but without shifting.
Definition: bitfield.hh:104
ArmSystem::getGenericTimer
GenericTimer * getGenericTimer() const
Get a pointer to the system's generic timer model.
Definition: system.hh:194
ArmISA::Interrupts
Definition: interrupts.hh:69
system.hh
ThreadContext::setHtmCheckpointPtr
virtual void setHtmCheckpointPtr(BaseHTMCheckpointPtr cpt)=0
ArmISA::TLBIASID
TLB Invalidate by ASID match.
Definition: tlbi_op.hh:118
ArmISA::MISCREG_ICH_LRC15
@ MISCREG_ICH_LRC15
Definition: miscregs.hh:1043
ArmISA::unflattenMiscReg
int unflattenMiscReg(int reg)
Definition: miscregs.cc:1363
ArmISA::MISCREG_ZCR_EL1
@ MISCREG_ZCR_EL1
Definition: miscregs.hh:1050
ArmISA::MISCREG_DBGWCR13_EL1
@ MISCREG_DBGWCR13_EL1
Definition: miscregs.hh:513
ArmISA::miscRegName
const char *const miscRegName[]
Definition: miscregs.hh:1159
ArmISA::MISCREG_AT_S1E1W_Xt
@ MISCREG_AT_S1E1W_Xt
Definition: miscregs.hh:652
faults.hh
ArmISA::MISCREG_HIFAR
@ MISCREG_HIFAR
Definition: miscregs.hh:284
ArmISA::ISA::sveVL
unsigned sveVL
SVE vector length in quadwords.
Definition: isa.hh:102
ArmISA::MISCREG_SEV_MAILBOX
@ MISCREG_SEV_MAILBOX
Definition: miscregs.hh:88
ArmISA
Definition: ccregs.hh:41
ArmISA::MISCREG_DBGBCR11
@ MISCREG_DBGBCR11
Definition: miscregs.hh:129
ArmISA::MISCREG_TLBI_VALE2IS_Xt
@ MISCREG_TLBI_VALE2IS_Xt
Definition: miscregs.hh:687
ArmISA::MISCREG_TCR_EL3
@ MISCREG_TCR_EL3
Definition: miscregs.hh:602
ArmISA::ISA::haveSecEL2
bool haveSecEL2
Definition: isa.hh:98
ArmISA::MISCREG_AT_S12E0W_Xt
@ MISCREG_AT_S12E0W_Xt
Definition: miscregs.hh:667
ArmISA::MISCREG_MPIDR
@ MISCREG_MPIDR
Definition: miscregs.hh:205
X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:87
ArmSystem::haveVirtualization
bool haveVirtualization() const
Returns true if this system implements the virtualization Extensions.
Definition: system.hh:170
ArmISA::MISCREG_TLBIMVAALIS
@ MISCREG_TLBIMVAALIS
Definition: miscregs.hh:320
ArmISA::MISCREG_DBGBCR12
@ MISCREG_DBGBCR12
Definition: miscregs.hh:130
ArmISA::MISCREG_ATS1CUR
@ MISCREG_ATS1CUR
Definition: miscregs.hh:300
ArmISA::ISA::Params
ArmISAParams Params
Definition: isa.hh:854
ArmISA::MISCREG_DBGWCR14
@ MISCREG_DBGWCR14
Definition: miscregs.hh:164
ArmISA::ISA::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg) const
Definition: isa.cc:484
ArmISA::MISCREG_TLBIIPAS2LIS
@ MISCREG_TLBIIPAS2LIS
Definition: miscregs.hh:334
ArmISA::MISCREG_VMPIDR
@ MISCREG_VMPIDR
Definition: miscregs.hh:228
ArmISA::ISA::zeroSveVecRegUpperPart
static void zeroSveVecRegUpperPart(VecRegContainer &vc, unsigned eCount)
Definition: isa.cc:2334
ArmISA::MISCREG_CNTFRQ
@ MISCREG_CNTFRQ
Definition: miscregs.hh:407
ArmISA::MISCREG_DBGBCR14_EL1
@ MISCREG_DBGBCR14_EL1
Definition: miscregs.hh:482
ArmISA::ISA::takeOverFrom
void takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc) override
Definition: isa.cc:477
ArmISA::MISCREG_ID_AA64MMFR0_EL1
@ MISCREG_ID_AA64MMFR0_EL1
Definition: miscregs.hh:561
ArmISA::MISCREG_DBGWCR5_EL1
@ MISCREG_DBGWCR5_EL1
Definition: miscregs.hh:505
ArmISA::ISA::assert32
void assert32()
Definition: isa.hh:457
ThreadContext::threadId
virtual int threadId() const =0
ArmISA::ISA::system
ArmSystem * system
Definition: isa.hh:69
ArmISA::MISCREG_TLBIALL
@ MISCREG_TLBIALL
Definition: miscregs.hh:327
ArmISA::ISA::addressTranslation
void addressTranslation(TLB::ArmTranslationType tran_type, BaseTLB::Mode mode, Request::Flags flags, RegVal val)
Definition: isa.cc:2394
ArmISA::MISCREG_ID_AA64AFR0_EL1
@ MISCREG_ID_AA64AFR0_EL1
Definition: miscregs.hh:557
iGbReg::TxdOp::ic
bool ic(TxDesc *d)
Definition: i8254xGBe_defs.hh:250
ArmISA::MISCREG_DBGBCR13
@ MISCREG_DBGBCR13
Definition: miscregs.hh:131
ArmISA::ISA::timer
std::unique_ptr< BaseISADevice > timer
Definition: isa.hh:82
ArmISA::MISCREG_NSACR
@ MISCREG_NSACR
Definition: miscregs.hh:239
VecRegContainer::as
VecRegT< VecElem, NumElems, true > as() const
View interposers.
Definition: vec_reg.hh:386
ArmISA::MISCREG_TLBIALLNSNHIS
@ MISCREG_TLBIALLNSNHIS
Definition: miscregs.hh:337
ArmISA::MISCREG_ID_AA64DFR1_EL1
@ MISCREG_ID_AA64DFR1_EL1
Definition: miscregs.hh:556
ArmISA::ISA::_vecRegRenameMode
const Enums::VecRegRenameMode _vecRegRenameMode
Definition: isa.hh:73
ArmISA::MISCREG_AT_S12E1R_Xt
@ MISCREG_AT_S12E1R_Xt
Definition: miscregs.hh:664
ArmISA::MISCREG_PRRR_NS
@ MISCREG_PRRR_NS
Definition: miscregs.hh:364
SimObject::startup
virtual void startup()
startup() is the final initialization call before simulation.
Definition: sim_object.cc:96
ArmISA::ISA::haveLargeAsid64
bool haveLargeAsid64
Definition: isa.hh:93
ArmISA::MISCREG_DBGBCR1_EL1
@ MISCREG_DBGBCR1_EL1
Definition: miscregs.hh:469
ArmISA::ISA::haveLSE
bool haveLSE
Definition: isa.hh:96
ArmISA::MISCREG_AMAIR0
@ MISCREG_AMAIR0
Definition: miscregs.hh:375
ArmISA::CCREG_C
@ CCREG_C
Definition: ccregs.hh:46
ArmISA::MISCREG_TLBIMVALH
@ MISCREG_TLBIMVALH
Definition: miscregs.hh:344
ArmISA::MISCREG_DBGBCR0_EL1
@ MISCREG_DBGBCR0_EL1
Definition: miscregs.hh:468
X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:997
ArmISA::MISCREG_DBGBCR15
@ MISCREG_DBGBCR15
Definition: miscregs.hh:133
ArmISA::SelfDebug::setDebugMask
void setDebugMask(bool mask)
Definition: self_debug.hh:417
ArmISA::MISCREG_DFAR_S
@ MISCREG_DFAR_S
Definition: miscregs.hh:279
ArmISA::TLB::S1CTran
@ S1CTran
Definition: tlb.hh:120
ArmISA::ISA::assert64
void assert64()
Definition: isa.hh:458
htm.hh
ArmISA::ISA::haveTME
bool haveTME
Definition: isa.hh:99
ArmISA::MISCREG_DBGWCR5
@ MISCREG_DBGWCR5
Definition: miscregs.hh:155
ArmISA::MISCREG_OSLSR_EL1
@ MISCREG_OSLSR_EL1
Definition: miscregs.hh:523
ArmISA::MISCREG_ID_MMFR3
@ MISCREG_ID_MMFR3
Definition: miscregs.hh:214
ArmISA::MISCREG_DC_ZVA_Xt
@ MISCREG_DC_ZVA_Xt
Definition: miscregs.hh:657
ArmISA::MISCREG_TLBI_VAE3IS_Xt
@ MISCREG_TLBI_VAE3IS_Xt
Definition: miscregs.hh:697
ArmISA::ELIs32
bool ELIs32(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:383
ArmISA::MISCREG_PAR
@ MISCREG_PAR
Definition: miscregs.hh:288
ArmISA::TLB::S12E0Tran
@ S12E0Tran
Definition: tlb.hh:133
ArmISA::MISCREG_CONTEXTIDR
@ MISCREG_CONTEXTIDR
Definition: miscregs.hh:393
ArmISA::BaseISADevice::setMiscReg
virtual void setMiscReg(int misc_reg, RegVal val)=0
Write to a system register belonging to this device.
ArmISA::MISCREG_ID_PFR0
@ MISCREG_ID_PFR0
Definition: miscregs.hh:207
ArmISA::MISCREG_MVBAR
@ MISCREG_MVBAR
Definition: miscregs.hh:388
ArmISA::MISCREG_ICC_AP0R0
@ MISCREG_ICC_AP0R0
Definition: miscregs.hh:951
ArmISA::MISCREG_CTR
@ MISCREG_CTR
Definition: miscregs.hh:202
ArmISA::SelfDebug::setbSDD
void setbSDD(RegVal val)
Definition: self_debug.hh:373
ArmISA::MISCREG_ID_AA64PFR0_EL1
@ MISCREG_ID_AA64PFR0_EL1
Definition: miscregs.hh:553
interrupts.hh
ArmISA::MISCREG_IFAR_S
@ MISCREG_IFAR_S
Definition: miscregs.hh:282
ArmISA::MISCREG_DTLBIMVA
@ MISCREG_DTLBIMVA
Definition: miscregs.hh:325
ArmSystem::haveSecurity
bool haveSecurity() const
Returns true if this system implements the Security Extensions.
Definition: system.hh:161
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
ArmISA::MISCREG_SCTLR_RST
@ MISCREG_SCTLR_RST
Definition: miscregs.hh:87
ArmISA::ISA::haveSVE
bool haveSVE
Definition: isa.hh:95
ArmISA::MODE_EL1H
@ MODE_EL1H
Definition: types.hh:631
ArmISA::ISA::dummyDevice
DummyISADevice dummyDevice
Dummy device for to handle non-existing ISA devices.
Definition: isa.hh:76
ArmSystem::haveLPAE
bool haveLPAE() const
Returns true if this system implements the Large Physical Address Extension.
Definition: system.hh:165
ArmISA::MISCREG_AMAIR1
@ MISCREG_AMAIR1
Definition: miscregs.hh:378
ArmISA::MISCREG_DBGWCR3_EL1
@ MISCREG_DBGWCR3_EL1
Definition: miscregs.hh:503
ArmISA::MISCREG_TLBIIPAS2
@ MISCREG_TLBIIPAS2
Definition: miscregs.hh:339
ArmSystem::haveLSE
bool haveLSE() const
Returns true if LSE is implemented (ARMv8.1)
Definition: system.hh:237
ArmISA::ArmFault
Definition: faults.hh:60
ArmISA::MISCREG_DBGWCR6
@ MISCREG_DBGWCR6
Definition: miscregs.hh:156
ArmISA::TLB::S1E2Tran
@ S1E2Tran
Definition: tlb.hh:131
ArmISA::MISCREG_MDSCR_EL1
@ MISCREG_MDSCR_EL1
Definition: miscregs.hh:449
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:234
ArmISA::MISCREG_HCR
@ MISCREG_HCR
Definition: miscregs.hh:242
ThreadContext::pcStateNoRecord
virtual void pcStateNoRecord(const TheISA::PCState &val)=0
ArmISA::ISA::clear32
void clear32(const ArmISAParams *p, const SCTLR &sctlr_rst)
Definition: isa.cc:223
ArmSystem::havePAN
bool havePAN() const
Returns true if Priviledge Access Never is implemented.
Definition: system.hh:240
ArmISA::MISCREG_ATS1CUW
@ MISCREG_ATS1CUW
Definition: miscregs.hh:301
ArmISA::MISCREG_TLBI_VAE1IS_Xt
@ MISCREG_TLBI_VAE1IS_Xt
Definition: miscregs.hh:671
ArmISA::ISA::haveCrypto
bool haveCrypto
Definition: isa.hh:92
BaseISA::tc
ThreadContext * tc
Definition: isa.hh:52
ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:621
ArmISA::MISCREG_PMOVSSET
@ MISCREG_PMOVSSET
Definition: miscregs.hh:360
ArmISA::MISCREG_TLBTR
@ MISCREG_TLBTR
Definition: miscregs.hh:204
ArmISA::SelfDebug::setMDSCRvals
void setMDSCRvals(RegVal val)
Definition: self_debug.hh:379
Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:240
ArmISA::MISCREG_DBGWCR12
@ MISCREG_DBGWCR12
Definition: miscregs.hh:162
MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:240
ArmISA::MISCREG_AT_S12E0R_Xt
@ MISCREG_AT_S12E0R_Xt
Definition: miscregs.hh:666
ArmISA::MISCREG_ID_DFR0_EL1
@ MISCREG_ID_DFR0_EL1
Definition: miscregs.hh:538
ArmISA::ISA::ISA
ISA(Params *p)
Definition: isa.cc:63
ArmISA::MISCREG_ID_AA64MMFR1_EL1
@ MISCREG_ID_AA64MMFR1_EL1
Definition: miscregs.hh:562
isa.hh
ArmISA::MISCREG_AT_S1E2W_Xt
@ MISCREG_AT_S1E2W_Xt
Definition: miscregs.hh:663
ArmISA::MISCREG_AT_S1E0R_Xt
@ MISCREG_AT_S1E0R_Xt
Definition: miscregs.hh:653
MipsISA::r
r
Definition: pra_constants.hh:95
cpu.hh
ArmISA::FpscrExcMask
static const uint32_t FpscrExcMask
Definition: miscregs.hh:2196
ArmISA::MISCREG_SP_EL0
@ MISCREG_SP_EL0
Definition: miscregs.hh:608
ArmISA::MISCREG_ID_ISAR1
@ MISCREG_ID_ISAR1
Definition: miscregs.hh:216
ArmISA::MISCREG_TCR_EL1
@ MISCREG_TCR_EL1
Definition: miscregs.hh:593
ArmISA::mode
Bitfield< 4, 0 > mode
Definition: miscregs_types.hh:70
ArmISA::MISCREG_ID_ISAR4
@ MISCREG_ID_ISAR4
Definition: miscregs.hh:219
ArmISA::el
Bitfield< 3, 2 > el
Definition: miscregs_types.hh:69
ArmISA::ISA::getGICv3CPUInterface
BaseISADevice & getGICv3CPUInterface()
Definition: isa.cc:2283
ArmISA::TLB::S1E0Tran
@ S1E0Tran
Definition: tlb.hh:129
ArmISA::MISCREG_RVBAR_EL1
@ MISCREG_RVBAR_EL1
Definition: miscregs.hh:730
ArmISA::MISCREG_L2CTLR
@ MISCREG_L2CTLR
Definition: miscregs.hh:361
ArmISA::MISCREG_TLBIALLHIS
@ MISCREG_TLBIALLHIS
Definition: miscregs.hh:335
ArmISA::MISCREG_TTBCR
@ MISCREG_TTBCR
Definition: miscregs.hh:254
ArmISA::MISCREG_DFSR
@ MISCREG_DFSR
Definition: miscregs.hh:262
ArmISA::MISCREG_ID_AA64DFR0_EL1
@ MISCREG_ID_AA64DFR0_EL1
Definition: miscregs.hh:555
ArmISA::MISCREG_DBGWCR2
@ MISCREG_DBGWCR2
Definition: miscregs.hh:152
ArmISA::getDTBPtr
TLB * getDTBPtr(T *tc)
Definition: tlb.hh:479
ArmISA::attr
attr
Definition: miscregs_types.hh:649
ArmISA::MISCREG_DBGBCR9_EL1
@ MISCREG_DBGBCR9_EL1
Definition: miscregs.hh:477
ArmISA::MISCREG_TLBI_VMALLS12E1IS
@ MISCREG_TLBI_VMALLS12E1IS
Definition: miscregs.hh:688
ArmSystem::sveVL
unsigned sveVL() const
Returns the SVE vector length at reset, in quadwords.
Definition: system.hh:234
ArmSystem::haveSecEL2
bool haveSecEL2() const
Returns true if Priviledge Access Never is implemented.
Definition: system.hh:243
tlbi_op.hh
System::Threads::size
int size() const
Definition: system.hh:204
ArmISA::MISCREG_SCTLR_S
@ MISCREG_SCTLR_S
Definition: miscregs.hh:231
ArmISA::MISCREG_DBGBCR2
@ MISCREG_DBGBCR2
Definition: miscregs.hh:120
ThreadContext::contextId
virtual ContextID contextId() const =0
ArmISA::MISCREG_TLBIMVAAL
@ MISCREG_TLBIMVAAL
Definition: miscregs.hh:332
ArmISA::MISCREG_TLBI_VAAE1_Xt
@ MISCREG_TLBI_VAAE1_Xt
Definition: miscregs.hh:679
ArmISA::ISA::clear64
void clear64(const ArmISAParams *p)
Definition: isa.cc:275
ArmISA::MISCREG_ACTLR
@ MISCREG_ACTLR
Definition: miscregs.hh:232
ArmISA::ISA::selfDebug
SelfDebug * selfDebug
Definition: isa.hh:112
ArmISA::MISCREG_TTBR0_EL2
@ MISCREG_TTBR0_EL2
Definition: miscregs.hh:595
ArmISA::INTREG_SP0
@ INTREG_SP0
Definition: intregs.hh:118
ArmISA::MISCREG_TLBI_VMALLE1IS
@ MISCREG_TLBI_VMALLE1IS
Definition: miscregs.hh:670
ArmISA::MISCREG_TLBIMVAH
@ MISCREG_TLBIMVAH
Definition: miscregs.hh:342
Gicv3
Definition: gic_v3.hh:53
ArmISA::MISCREG_CNTVOFF_EL2
@ MISCREG_CNTVOFF_EL2
Definition: miscregs.hh:780
ArmISA::MISCREG_ATS12NSOUW
@ MISCREG_ATS12NSOUW
Definition: miscregs.hh:305
ArmISA::MISCREG_DACR
@ MISCREG_DACR
Definition: miscregs.hh:259
ArmISA::MISCREG_SCTLR_NS
@ MISCREG_SCTLR_NS
Definition: miscregs.hh:230
ArmISA::MISCREG_TLBI_VAE2_Xt
@ MISCREG_TLBI_VAE2_Xt
Definition: miscregs.hh:692
ArmISA::MISCREG_DBGWCR6_EL1
@ MISCREG_DBGWCR6_EL1
Definition: miscregs.hh:506
ArmISA::MISCREG_ATS12NSOUR
@ MISCREG_ATS12NSOUR
Definition: miscregs.hh:304
ArmISA::MISCREG_DBGBCR11_EL1
@ MISCREG_DBGBCR11_EL1
Definition: miscregs.hh:479
ArmISA::TLB::invalidateMiscReg
void invalidateMiscReg()
Definition: tlb.hh:446
ArmISA::TLBIMVAA
TLB Invalidate by VA, All ASID.
Definition: tlbi_op.hh:175
ArmISA::MISCREG_DBGWCR9
@ MISCREG_DBGWCR9
Definition: miscregs.hh:159
ArmISA::MISCREG_TTBR0_EL3
@ MISCREG_TTBR0_EL3
Definition: miscregs.hh:601
ArmISA::MISCREG_DBGWCR10_EL1
@ MISCREG_DBGWCR10_EL1
Definition: miscregs.hh:510
faults.hh
ArmISA::MISCREG_ITLBIALL
@ MISCREG_ITLBIALL
Definition: miscregs.hh:321
generic_timer.hh
ArmISA::MISCREG_TLBIASIDIS
@ MISCREG_TLBIASIDIS
Definition: miscregs.hh:317
ArmISA::MISCREG_HCR2
@ MISCREG_HCR2
Definition: miscregs.hh:243
ArmISA::MISCREG_DBGWCR10
@ MISCREG_DBGWCR10
Definition: miscregs.hh:160
ArmISA::ISA::MiscRegLUTEntryInitializer::highest
chain highest(ArmSystem *const sys) const
Definition: isa.cc:2461
ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition: miscregs.hh:578
ArmISA::ISA::setMiscRegNoEffect
void setMiscRegNoEffect(int misc_reg, RegVal val)
Definition: isa.cc:810
X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
ArmISA::MISCREG_TLBI_ALLE3IS
@ MISCREG_TLBI_ALLE3IS
Definition: miscregs.hh:696
NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:245
ArmISA::MISCREG_TTBR1_EL1
@ MISCREG_TTBR1_EL1
Definition: miscregs.hh:591
ArmISA::MISCREG_DBGDIDR
@ MISCREG_DBGDIDR
Definition: miscregs.hh:91
ArmISA::sp
Bitfield< 0 > sp
Definition: miscregs_types.hh:71
ArmISA::MISCREG_SP_EL2
@ MISCREG_SP_EL2
Definition: miscregs.hh:626
ArmISA::MISCREG_IFSR
@ MISCREG_IFSR
Definition: miscregs.hh:265
ArmISA::MISCREG_DTLBIASID
@ MISCREG_DTLBIASID
Definition: miscregs.hh:326
ArmISA::MISCREG_FPEXC
@ MISCREG_FPEXC
Definition: miscregs.hh:71
ArmISA::EL1
@ EL1
Definition: types.hh:623
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
ArmISA::MISCREG_RVBAR_EL3
@ MISCREG_RVBAR_EL3
Definition: miscregs.hh:735
ArmISA::MISCREG_ATS12NSOPW
@ MISCREG_ATS12NSOPW
Definition: miscregs.hh:303
ArmISA::MISCREG_TLBIIPAS2L
@ MISCREG_TLBIIPAS2L
Definition: miscregs.hh:340
ArmISA::MISCREG_WARN_NOT_FAIL
@ MISCREG_WARN_NOT_FAIL
Definition: miscregs.hh:1095
ArmISA::MISCREG_HSCTLR
@ MISCREG_HSCTLR
Definition: miscregs.hh:240
ArmISA::readMPIDR
RegVal readMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
This helper function is either returing the value of MPIDR_EL1 (by calling getMPIDR),...
Definition: utility.cc:236
ArmISA::MISCREG_TLBIASID
@ MISCREG_TLBIASID
Definition: miscregs.hh:329
ArmISA::SelfDebug::updateOSLock
void updateOSLock(RegVal val)
Definition: self_debug.hh:399
ArmISA::MISCREG_DBGWCR3
@ MISCREG_DBGWCR3
Definition: miscregs.hh:153
ArmISA::MISCREG_TCMTR
@ MISCREG_TCMTR
Definition: miscregs.hh:203
ArmISA::ISA::afterStartup
bool afterStartup
Definition: isa.hh:110
ArmISA::ISA::MiscRegLUTEntryInitializer::hyp
chain hyp(bool v=true) const
Definition: isa.hh:278
ArmISA::ISA::updateRegMap
void updateRegMap(CPSR cpsr)
Definition: isa.hh:416
ArmISA::MISCREG_AT_S1E1R_Xt
@ MISCREG_AT_S1E1R_Xt
Definition: miscregs.hh:651
ArmISA::MISCREG_FPSCR
@ MISCREG_FPSCR
Definition: miscregs.hh:68
ArmISA::MISCREG_DBGBCR13_EL1
@ MISCREG_DBGBCR13_EL1
Definition: miscregs.hh:481
ArmISA::TLBIALL
TLB Invalidate All.
Definition: tlbi_op.hh:81
ArmISA::MISCREG_ZCR_EL3
@ MISCREG_ZCR_EL3
Definition: miscregs.hh:1047
ArmISA::MISCREG_NMRR
@ MISCREG_NMRR
Definition: miscregs.hh:369
ArmISA::MISCREG_DBGBCR7
@ MISCREG_DBGBCR7
Definition: miscregs.hh:125
ArmISA::MISCREG_TLBI_VALE3_Xt
@ MISCREG_TLBI_VALE3_Xt
Definition: miscregs.hh:701
ArmISA::MISCREG_SP_EL1
@ MISCREG_SP_EL1
Definition: miscregs.hh:619
ArmISA::ISA::getGenericTimer
BaseISADevice & getGenericTimer()
Definition: isa.cc:2262
ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
ArmISA::CpsrMaskQ
static const uint32_t CpsrMaskQ
Definition: miscregs.hh:2175
ArmISA::MISCREG_TTBR1
@ MISCREG_TTBR1
Definition: miscregs.hh:251
Request::funcRequestorId
@ funcRequestorId
This requestor id is used for functional requests that don't come from a particular device.
Definition: request.hh:248
ArmISA::MISCREG_PAN
@ MISCREG_PAN
Definition: miscregs.hh:1085
ArmISA::MISCREG_TLBI_VALE2_Xt
@ MISCREG_TLBI_VALE2_Xt
Definition: miscregs.hh:694
ArmISA::asid
asid
Definition: miscregs_types.hh:611
ArmISA::ISA::haveVirtualization
bool haveVirtualization
Definition: isa.hh:91
ThreadContext::readCCReg
virtual RegVal readCCReg(RegIndex reg_idx) const =0
BaseTLB::Write
@ Write
Definition: tlb.hh:57
ArmISA::ISA::MiscRegLUTEntryInitializer::chain
const typedef MiscRegLUTEntryInitializer & chain
Definition: isa.hh:142
ArmISA::MISCREG_PRRR
@ MISCREG_PRRR
Definition: miscregs.hh:363
ArmISA::DTLBIMVA
Data TLB Invalidate by VA.
Definition: tlbi_op.hh:224
ArmSystem
Definition: system.hh:59
ArmISA::MISCREG_DBGBCR7_EL1
@ MISCREG_DBGBCR7_EL1
Definition: miscregs.hh:475
ArmISA::MISCREG_TLBI_VAE1_Xt
@ MISCREG_TLBI_VAE1_Xt
Definition: miscregs.hh:677
ArmISA::MISCREG_TLBIALLNSNH
@ MISCREG_TLBIALLNSNH
Definition: miscregs.hh:343
ArmISA::ITLBIALL
Instruction TLB Invalidate All.
Definition: tlbi_op.hh:92
ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition: miscregs.hh:585
ArmISA::ISA::haveSecurity
bool haveSecurity
Definition: isa.hh:89
ArmISA::MISCREG_ID_DFR0
@ MISCREG_ID_DFR0
Definition: miscregs.hh:209
ArmISA::MISCREG_CPTR_EL2
@ MISCREG_CPTR_EL2
Definition: miscregs.hh:580
stat_control.hh
ArmISA::MISCREG_DBGWCR13
@ MISCREG_DBGWCR13
Definition: miscregs.hh:163
ArmISA::MISCREG_SPSEL
@ MISCREG_SPSEL
Definition: miscregs.hh:609
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:197
System::threads
Threads threads
Definition: system.hh:309
ArmISA::getITBPtr
TLB * getITBPtr(T *tc)
Definition: tlb.hh:470
ArmISA::MISCREG_MAIR1
@ MISCREG_MAIR1
Definition: miscregs.hh:372
ArmISA::MISCREG_SDCR
@ MISCREG_SDCR
Definition: miscregs.hh:236
ArmISA::MISCREG_DBGOSLSR
@ MISCREG_DBGOSLSR
Definition: miscregs.hh:184
ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: miscregs.hh:57
ArmISA::TLB::S1E1Tran
@ S1E1Tran
Definition: tlb.hh:130
ArmISA::MISCREG_TLBI_VALE1IS_Xt
@ MISCREG_TLBI_VALE1IS_Xt
Definition: miscregs.hh:674
ArmISA::MISCREG_DBGBCR4_EL1
@ MISCREG_DBGBCR4_EL1
Definition: miscregs.hh:472
ArmISA::MISCREG_FPCR
@ MISCREG_FPCR
Definition: miscregs.hh:613
ArmISA::ISA::physAddrRange
uint8_t physAddrRange
Definition: isa.hh:94
ArmISA::MISCREG_AT_S1E2R_Xt
@ MISCREG_AT_S1E2R_Xt
Definition: miscregs.hh:662
ArmISA::MISCREG_DBGBCR10
@ MISCREG_DBGBCR10
Definition: miscregs.hh:128
ThreadContext::setCCReg
virtual void setCCReg(RegIndex reg_idx, RegVal val)=0
base.hh
ArmISA::ArmFault::update
void update(ThreadContext *tc)
Definition: faults.cc:436
ArmISA::MISCREG_DBGWCR15
@ MISCREG_DBGWCR15
Definition: miscregs.hh:165
ArmISA::ISA::pmu
BaseISADevice * pmu
Definition: isa.hh:79
ArmISA::MISCREG_TLBI_ALLE2IS
@ MISCREG_TLBI_ALLE2IS
Definition: miscregs.hh:684
ArmISA::MISCREG_TLBI_ALLE1IS
@ MISCREG_TLBI_ALLE1IS
Definition: miscregs.hh:686
MipsISA::PCState
GenericISA::DelaySlotPCState< MachInst > PCState
Definition: types.hh:41
ArmISA::MISCREG_MDCR_EL2
@ MISCREG_MDCR_EL2
Definition: miscregs.hh:579
SimObject::_params
const SimObjectParams * _params
Cached copy of the object parameters.
Definition: sim_object.hh:110
ArmISA::MISCREG_ID_AFR0
@ MISCREG_ID_AFR0
Definition: miscregs.hh:210
ArmISA::MISCREG_TLBI_VAE3_Xt
@ MISCREG_TLBI_VAE3_Xt
Definition: miscregs.hh:700
ArmISA::ISA::initID64
void initID64(const ArmISAParams *p)
Definition: isa.cc:360
Gicv3::getCPUInterface
Gicv3CPUInterface * getCPUInterface(int cpu_id) const
Definition: gic_v3.hh:137
ArmISA::MISCREG_TLBIALLH
@ MISCREG_TLBIALLH
Definition: miscregs.hh:341
ArmISA::MISCREG_TLBIMVALIS
@ MISCREG_TLBIMVALIS
Definition: miscregs.hh:319
ArmSystem::highestEL
ArmISA::ExceptionLevel highestEL() const
Returns the highest implemented exception level.
Definition: system.hh:208
ArmISA::pan
Bitfield< 22 > pan
Definition: miscregs_types.hh:55
insertBits
T insertBits(T val, int first, int last, B bit_val)
Returns val with bits first to last set to the LSBs of bit_val.
Definition: bitfield.hh:147
ArmISA::MISCREG_DBGBCR5
@ MISCREG_DBGBCR5
Definition: miscregs.hh:123
ArmISA::ArmFault::getFsr
virtual FSR getFsr(ThreadContext *tc) const
Definition: faults.hh:250
ArmISA::NUM_MISCREGS
@ NUM_MISCREGS
Definition: miscregs.hh:1088
ArmISA::MISCREG_ID_ISAR2
@ MISCREG_ID_ISAR2
Definition: miscregs.hh:217
ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR
@ MISCREG_PMXEVTYPER_PMCCFILTR
Definition: miscregs.hh:86
ArmISA::MISCREG_ICH_LR15_EL2
@ MISCREG_ICH_LR15_EL2
Definition: miscregs.hh:906
ArmISA::MISCREG_TLBI_VAALE1_Xt
@ MISCREG_TLBI_VAALE1_Xt
Definition: miscregs.hh:681
ArmISA::len
Bitfield< 18, 16 > len
Definition: miscregs_types.hh:439
ThreadContext::getCheckerCpuPtr
virtual CheckerCPU * getCheckerCpuPtr()=0
ArmISA::MiscRegIndex
MiscRegIndex
Definition: miscregs.hh:56
ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
ArmISA::MISCREG_HSTR
@ MISCREG_HSTR
Definition: miscregs.hh:246
ArmISA::MISCREG_MIDR_EL1
@ MISCREG_MIDR_EL1
Definition: miscregs.hh:533
ArmISA::MISCREG_VPIDR
@ MISCREG_VPIDR
Definition: miscregs.hh:227
ArmISA::MISCREG_DBGWCR4
@ MISCREG_DBGWCR4
Definition: miscregs.hh:154
ArmISA::MISCREG_ID_ISAR0
@ MISCREG_ID_ISAR0
Definition: miscregs.hh:215
ArmISA::MISCREG_MPIDR_EL1
@ MISCREG_MPIDR_EL1
Definition: miscregs.hh:534
ArmISA::MISCREG_DTLBIALL
@ MISCREG_DTLBIALL
Definition: miscregs.hh:324
ArmISA::MISCREG_ITLBIASID
@ MISCREG_ITLBIASID
Definition: miscregs.hh:323
ArmISA::MISCREG_DBGWCR8_EL1
@ MISCREG_DBGWCR8_EL1
Definition: miscregs.hh:508
ArmISA::MISCREG_DBGBCR6_EL1
@ MISCREG_DBGBCR6_EL1
Definition: miscregs.hh:474
ArmISA::MISCREG_ID_PFR1
@ MISCREG_ID_PFR1
Definition: miscregs.hh:208
ArmISA::TLBIIPA
TLB Invalidate by Intermediate Physical Address.
Definition: tlbi_op.hh:242
pmu.hh
ArmISA::MISCREG_FPSID
@ MISCREG_FPSID
Definition: miscregs.hh:67
ThreadContext::getDecoderPtr
virtual TheISA::Decoder * getDecoderPtr()=0
ArmISA::MISCREG_RVBAR_EL2
@ MISCREG_RVBAR_EL2
Definition: miscregs.hh:733
ArmISA::MISCREG_TLBI_IPAS2E1_Xt
@ MISCREG_TLBI_IPAS2E1_Xt
Definition: miscregs.hh:689
ArmISA::MISCREG_MAIR0
@ MISCREG_MAIR0
Definition: miscregs.hh:366
ArmISA::MODE_MON
@ MODE_MON
Definition: types.hh:640
ArmISA::FpscrQcMask
static const uint32_t FpscrQcMask
Definition: miscregs.hh:2192
ArmISA::ISA::startup
void startup() override
startup() is the final initialization call before simulation.
Definition: isa.cc:439
ArmISA::MISCREG_DBGWCR11
@ MISCREG_DBGWCR11
Definition: miscregs.hh:161
ArmISA::ISA::readMiscReg
RegVal readMiscReg(int misc_reg)
Definition: isa.cc:508
ArmISA::MISCREG_HDFAR
@ MISCREG_HDFAR
Definition: miscregs.hh:283
ArmISA::MISCREG_DBGBCR3
@ MISCREG_DBGBCR3
Definition: miscregs.hh:121
ArmISA::SelfDebug::updateDBGBCR
void updateDBGBCR(int index, DBGBCR val)
Definition: self_debug.hh:405
ArmISA::ISA::MiscRegLUTEntryInitializer::mon
chain mon(bool v=true) const
Definition: isa.hh:316
ArmISA::MISCREG_DBGBCR6
@ MISCREG_DBGBCR6
Definition: miscregs.hh:124
ArmISA::ISA::addressTranslation64
void addressTranslation64(TLB::ArmTranslationType tran_type, BaseTLB::Mode mode, Request::Flags flags, RegVal val)
Definition: isa.cc:2343
ArmISA::MISCREG_TTBR1_EL2
@ MISCREG_TTBR1_EL2
Definition: miscregs.hh:812
ArmISA::MISCREG_SCTLR
@ MISCREG_SCTLR
Definition: miscregs.hh:229
ArmISA::ISA::getCurSveVecLenInBits
unsigned getCurSveVecLenInBits() const
Definition: isa.cc:2290
ArmISA::MISCREG_AT_S12E1W_Xt
@ MISCREG_AT_S12E1W_Xt
Definition: miscregs.hh:665
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
self_debug.hh
ArmISA::TLB::S1E3Tran
@ S1E3Tran
Definition: tlb.hh:132
ArmISA::MISCREG_TLBI_ALLE1
@ MISCREG_TLBI_ALLE1
Definition: miscregs.hh:693
ArmISA::DTLBIASID
Data TLB Invalidate by ASID match.
Definition: tlbi_op.hh:148
ArmISA::MISCREG_NZCV
@ MISCREG_NZCV
Definition: miscregs.hh:611
ArmISA::MISCREG_CPACR_EL1
@ MISCREG_CPACR_EL1
Definition: miscregs.hh:574
ArmISA::MISCREG_DBGBCR4
@ MISCREG_DBGBCR4
Definition: miscregs.hh:122
ArmISA::MISCREG_DBGBCR12_EL1
@ MISCREG_DBGBCR12_EL1
Definition: miscregs.hh:480
ArmISA::ISA::initID32
void initID32(const ArmISAParams *p)
Definition: isa.cc:324
System::cacheLineSize
unsigned int cacheLineSize() const
Get the cache line size of the system.
Definition: system.hh:307
ArmISA::MODE_USER
@ MODE_USER
Definition: types.hh:636
ArmISA::ITLBIASID
Instruction TLB Invalidate by ASID match.
Definition: tlbi_op.hh:132
ArmISA::ISA::MiscRegLUTEntryInitializer::priv
chain priv(bool v=true) const
Definition: isa.hh:245
ArmISA::MISCREG_PMEVTYPER5_EL0
@ MISCREG_PMEVTYPER5_EL0
Definition: miscregs.hh:793
ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
ArmISA::MISCREG_MIDR
@ MISCREG_MIDR
Definition: miscregs.hh:201
ArmISA::INTREG_SP1
@ INTREG_SP1
Definition: intregs.hh:119
ArmISA::MISCREG_SPSR_EL3
@ MISCREG_SPSR_EL3
Definition: miscregs.hh:624
ArmISA::MISCREG_SCTLR_EL3
@ MISCREG_SCTLR_EL3
Definition: miscregs.hh:583
ArmISA::MISCREG_DBGWCR7
@ MISCREG_DBGWCR7
Definition: miscregs.hh:157
ArmSystem::haveTME
bool haveTME() const
Returns true if this system implements the transactional memory extension (ARMv9)
Definition: system.hh:228
ArmISA::ISA::havePAN
bool havePAN
Definition: isa.hh:97
ArmISA::SelfDebug::setenableTDETGE
void setenableTDETGE(HCR hcr, HDCR mdcr)
Definition: self_debug.hh:393
ArmISA::MISCREG_DBGWCR1
@ MISCREG_DBGWCR1
Definition: miscregs.hh:151
ArmISA::MISCREG_TLBI_ALLE2
@ MISCREG_TLBI_ALLE2
Definition: miscregs.hh:691
ArmISA::MISCREG_JOSCR
@ MISCREG_JOSCR
Definition: miscregs.hh:197
ArmISA::BaseISADevice::setISA
virtual void setISA(ISA *isa)
Definition: isa_device.cc:51
ArmISA::MISCREG_TLBIIPAS2IS
@ MISCREG_TLBIIPAS2IS
Definition: miscregs.hh:333
ArmISA::MISCREG_TLBI_IPAS2LE1_Xt
@ MISCREG_TLBI_IPAS2LE1_Xt
Definition: miscregs.hh:690
ArmISA::NumMiscRegs
const int NumMiscRegs
Definition: registers.hh:85
ThreadContext::getCpuPtr
virtual BaseCPU * getCpuPtr()=0
ArmISA::MISCREG_SCR
@ MISCREG_SCR
Definition: miscregs.hh:237
ArmISA::MISCREG_HDCR
@ MISCREG_HDCR
Definition: miscregs.hh:244
ArmISA::MISCREG_DBGBCR8_EL1
@ MISCREG_DBGBCR8_EL1
Definition: miscregs.hh:476
ArmISA::MISCREG_TLBI_VALE1_Xt
@ MISCREG_TLBI_VALE1_Xt
Definition: miscregs.hh:680
ArmISA::MISCREG_DBGBCR10_EL1
@ MISCREG_DBGBCR10_EL1
Definition: miscregs.hh:478
ArmISA::MISCREG_CNTVOFF
@ MISCREG_CNTVOFF
Definition: miscregs.hh:427
ArmISA::TLB::S12E1Tran
@ S12E1Tran
Definition: tlb.hh:134
ArmISA::MODE_EL2H
@ MODE_EL2H
Definition: types.hh:633
BaseISA
Definition: isa.hh:47
ArmISA::MISCREG_CPTR_EL3
@ MISCREG_CPTR_EL3
Definition: miscregs.hh:587
ArmISA::MISCREG_SPSR_EL2
@ MISCREG_SPSR_EL2
Definition: miscregs.hh:617
ArmISA::miscRegInfo
bitset< NUM_MISCREG_INFOS > miscRegInfo[NUM_MISCREGS]
Definition: miscregs.cc:3381
ArmISA::ISA::params
const Params * params() const
Definition: isa.cc:124
BaseCPU::getInterruptController
BaseInterrupts * getInterruptController(ThreadID tid)
Definition: base.hh:219
ArmISA::MISCREG_SCTLR_EL2
@ MISCREG_SCTLR_EL2
Definition: miscregs.hh:576
ArmISA::MISCREG_ID_AA64PFR1_EL1
@ MISCREG_ID_AA64PFR1_EL1
Definition: miscregs.hh:554
ArmISA::MISCREG_TLBIMVALHIS
@ MISCREG_TLBIMVALHIS
Definition: miscregs.hh:338
gic_v3.hh
ArmISA::ISA::highestELIs64
bool highestELIs64
Definition: isa.hh:88
ArmISA::MISCREG_DBGWCR1_EL1
@ MISCREG_DBGWCR1_EL1
Definition: miscregs.hh:501
ArmISA::MISCREG_VTTBR
@ MISCREG_VTTBR
Definition: miscregs.hh:442
ArmISA::MISCREG_ATS1HW
@ MISCREG_ATS1HW
Definition: miscregs.hh:314
ArmISA::ITLBIMVA
Instruction TLB Invalidate by VA.
Definition: tlbi_op.hh:206
ArmISA::v
Bitfield< 28 > v
Definition: miscregs_types.hh:51
ArmISA::TLB::translateFunctional
bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr)
Do a functional lookup on the TLB (for debugging) and don't modify any internal state.
Definition: tlb.cc:117
ArmISA::MISCREG_DBGBCR0
@ MISCREG_DBGBCR0
Definition: miscregs.hh:118
ArmISA::MISCREG_CPSR_Q
@ MISCREG_CPSR_Q
Definition: miscregs.hh:75
ArmISA::MISCREG_DBGBCR1
@ MISCREG_DBGBCR1
Definition: miscregs.hh:119
ArmISA::MISCREG_CSSELR
@ MISCREG_CSSELR
Definition: miscregs.hh:224
ULL
#define ULL(N)
uint64_t constant
Definition: types.hh:50
ArmISA::MISCREG_TLBI_VAE2IS_Xt
@ MISCREG_TLBI_VAE2IS_Xt
Definition: miscregs.hh:685
RegVal
uint64_t RegVal
Definition: types.hh:168
ArmISA::MISCREG_PMCR
@ MISCREG_PMCR
Definition: miscregs.hh:345
ArmISA::MISCREG_ID_ISAR5
@ MISCREG_ID_ISAR5
Definition: miscregs.hh:220
VecRegContainer
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
Definition: vec_reg.hh:156
ArmISA::mask
Bitfield< 28, 24 > mask
Definition: miscregs_types.hh:711
ArmISA::MISCREG_SCTLR_EL1
@ MISCREG_SCTLR_EL1
Definition: miscregs.hh:571
ArmISA::isSecure
bool isSecure(ThreadContext *tc)
Definition: utility.cc:174
ArmISA::ISA::lookUpMiscReg
static std::vector< struct MiscRegLUTEntry > lookUpMiscReg
Metadata table accessible via the value of the register.
Definition: isa.hh:137
ArmISA::MISCREG_DBGWCR8
@ MISCREG_DBGWCR8
Definition: miscregs.hh:158
ThreadContext::getSystemPtr
virtual System * getSystemPtr()=0
ArmSystem::haveLargeAsid64
bool haveLargeAsid64() const
Returns true if ASID is 16 bits in AArch64 (ARMv8)
Definition: system.hh:223
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171
ArmISA::TLBIALLN
TLB Invalidate All, Non-Secure.
Definition: tlbi_op.hh:164
ArmISA::BaseISADevice::readMiscReg
virtual RegVal readMiscReg(int misc_reg)=0
Read a system register belonging to this device.
ArmISA::MISCREG_TLBI_ASIDE1_Xt
@ MISCREG_TLBI_ASIDE1_Xt
Definition: miscregs.hh:678
ArmISA::MISCREG_PMINTENSET_EL1
@ MISCREG_PMINTENSET_EL1
Definition: miscregs.hh:702
ArmISA::MISCREG_MVFR0
@ MISCREG_MVFR0
Definition: miscregs.hh:70
ArmISA::MISCREG_ATS1CPW
@ MISCREG_ATS1CPW
Definition: miscregs.hh:299
bits
T bits(T val, int first, int last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:75
ArmISA::MISCREG_SPSR_EL1
@ MISCREG_SPSR_EL1
Definition: miscregs.hh:604
ArmISA::INTREG_SP2
@ INTREG_SP2
Definition: intregs.hh:120
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