gem5  v21.1.0.2
GPUCoalescer.hh
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33 
34 #ifndef __MEM_RUBY_SYSTEM_GPU_COALESCER_HH__
35 #define __MEM_RUBY_SYSTEM_GPU_COALESCER_HH__
36 
37 #include <iostream>
38 #include <unordered_map>
39 
40 #include "base/statistics.hh"
42 #include "gpu-compute/misc.hh"
43 #include "mem/request.hh"
46 #include "mem/ruby/protocol/PrefetchBit.hh"
47 #include "mem/ruby/protocol/RubyAccessMode.hh"
48 #include "mem/ruby/protocol/RubyRequestType.hh"
49 #include "mem/ruby/protocol/SequencerRequestType.hh"
51 #include "mem/token_port.hh"
52 
53 namespace gem5
54 {
55 
56 struct RubyGPUCoalescerParams;
57 
58 namespace ruby
59 {
60 
61 class DataBlock;
62 class CacheMsg;
63 struct MachineID;
65 
66 // List of packets that belongs to a specific instruction.
68 
70 {
71  public:
74 
75  void insertPacket(PacketPtr pkt);
76  bool packetAvailable();
77  void printRequestTable(std::stringstream& ss);
78 
79  // Modify packets remaining map. Init sets value iff the seqNum has not
80  // yet been seen before. get/set act as a regular getter/setter.
81  void initPacketsRemaining(InstSeqNum seqNum, int count);
82  int getPacketsRemaining(InstSeqNum seqNum);
83  void setPacketsRemaining(InstSeqNum seqNum, int count);
84 
85  // Returns a pointer to the list of packets corresponding to an
86  // instruction in the instruction map or nullptr if there are no
87  // instructions at the offset.
89  void updateResources();
90  bool areRequestsDone(const InstSeqNum instSeqNum);
91 
92  // Check if a packet hasn't been removed from instMap in too long.
93  // Panics if a deadlock is detected and returns nothing otherwise.
94  void checkDeadlock(Tick threshold);
95 
96  private:
98 
99  // Maps an instructions unique sequence number to a queue of packets
100  // which need responses. This data structure assumes the sequence number
101  // is monotonically increasing (which is true for CU class) in order to
102  // issue packets in age order.
103  std::map<InstSeqNum, PerInstPackets> instMap;
104 
105  std::map<InstSeqNum, int> instPktsRemaining;
106 };
107 
109 {
110  public:
111  CoalescedRequest(uint64_t _seqNum)
112  : seqNum(_seqNum), issueTime(Cycles(0)),
113  rubyType(RubyRequestType_NULL)
114  {}
116 
117  void insertPacket(PacketPtr pkt) { pkts.push_back(pkt); }
118  void setSeqNum(uint64_t _seqNum) { seqNum = _seqNum; }
119  void setIssueTime(Cycles _issueTime) { issueTime = _issueTime; }
120  void setRubyType(RubyRequestType type) { rubyType = type; }
121 
122  uint64_t getSeqNum() const { return seqNum; }
123  PacketPtr getFirstPkt() const { return pkts[0]; }
124  Cycles getIssueTime() const { return issueTime; }
125  RubyRequestType getRubyType() const { return rubyType; }
127 
128  private:
129  uint64_t seqNum;
131  RubyRequestType rubyType;
133 };
134 
135 // PendingWriteInst tracks the number of outstanding Ruby requests
136 // per write instruction. Once all requests associated with one instruction
137 // are completely done in Ruby, we call back the requestor to mark
138 // that this instruction is complete.
140 {
141  public:
143  : numPendingStores(0),
144  originalPort(nullptr),
145  gpuDynInstPtr(nullptr)
146  {}
147 
149  {}
150 
151  void
153  bool usingRubyTester)
154  {
155  assert(port);
156  originalPort = port;
157 
158  if (!usingRubyTester) {
159  gpuDynInstPtr = inst;
160  }
161 
163  }
164 
165  // return true if no more ack is expected
166  bool
168  {
169  assert(numPendingStores > 0);
171  return (numPendingStores == 0) ? true : false;
172  }
173 
174  // ack the original requestor that this write instruction is complete
175  void
176  ackWriteCompletion(bool usingRubyTester)
177  {
178  assert(numPendingStores == 0);
179 
180  // make a response packet
181  PacketPtr pkt = new Packet(std::make_shared<Request>(),
183 
184  if (!usingRubyTester) {
185  assert(gpuDynInstPtr);
188  (gpuDynInstPtr, 0, nullptr);
189  pkt->senderState = ss;
190  }
191 
192  // send the ack response to the requestor
194  }
195 
196  int
198  return numPendingStores;
199  }
200 
201  private:
202  // the number of stores waiting for writeCompleteCallback
204  // The original port that sent one of packets associated with this
205  // write instruction. We may have more than one packet per instruction,
206  // which implies multiple ports per instruction. However, we need
207  // only 1 of the ports to call back the CU. Therefore, here we keep
208  // track the port that sent the first packet of this instruction.
210  // similar to the originalPort, this gpuDynInstPtr is set only for
211  // the first packet of this instruction.
213 };
214 
215 class GPUCoalescer : public RubyPort
216 {
217  public:
219  {
220  public:
221  GMTokenPort(const std::string& name, ClockedObject *owner,
222  PortID id = InvalidPortID)
224  { }
226 
227  protected:
228  Tick recvAtomic(PacketPtr) { return Tick(0); }
230  bool recvTimingReq(PacketPtr) { return false; }
232  {
233  AddrRangeList ranges;
234  return ranges;
235  }
236  };
237 
238  typedef RubyGPUCoalescerParams Params;
239  GPUCoalescer(const Params &);
240  ~GPUCoalescer();
241 
242  Port &getPort(const std::string &if_name,
243  PortID idx = InvalidPortID) override;
244 
245  // Public Methods
246  void wakeup(); // Used only for deadlock detection
247  void printRequestTable(std::stringstream& ss);
248 
249  void printProgress(std::ostream& out) const;
250  void resetStats() override;
251  void collateStats();
252 
253  // each store request needs two callbacks:
254  // (1) writeCallback is called when the store is received and processed
255  // by TCP. This writeCallback does not guarantee the store is actually
256  // completed at its destination cache or memory. writeCallback helps
257  // release hardware resources (e.g., its entry in coalescedTable)
258  // allocated for the store so that subsequent requests will not be
259  // blocked unnecessarily due to hardware resource constraints.
260  // (2) writeCompleteCallback is called when the store is fully completed
261  // at its destination cache or memory. writeCompleteCallback
262  // guarantees that the store is fully completed. This callback
263  // will decrement hardware counters in CU
264  void writeCallback(Addr address, DataBlock& data);
265 
266  void writeCallback(Addr address,
267  MachineType mach,
268  DataBlock& data);
269 
270  void writeCallback(Addr address,
271  MachineType mach,
272  DataBlock& data,
273  Cycles initialRequestTime,
274  Cycles forwardRequestTime,
275  Cycles firstResponseTime,
276  bool isRegion);
277 
278  void writeCallback(Addr address,
279  MachineType mach,
280  DataBlock& data,
281  Cycles initialRequestTime,
282  Cycles forwardRequestTime,
283  Cycles firstResponseTime);
284 
285  void writeCompleteCallback(Addr address,
286  uint64_t instSeqNum,
287  MachineType mach);
288 
289  void readCallback(Addr address, DataBlock& data);
290 
291  void readCallback(Addr address,
292  MachineType mach,
293  DataBlock& data);
294 
295  void readCallback(Addr address,
296  MachineType mach,
297  DataBlock& data,
298  Cycles initialRequestTime,
299  Cycles forwardRequestTime,
300  Cycles firstResponseTime);
301 
302  void readCallback(Addr address,
303  MachineType mach,
304  DataBlock& data,
305  Cycles initialRequestTime,
306  Cycles forwardRequestTime,
307  Cycles firstResponseTime,
308  bool isRegion);
309 
310  /* atomics need their own callback because the data
311  might be const coming from SLICC */
312  virtual void atomicCallback(Addr address,
313  MachineType mach,
314  const DataBlock& data);
315 
316  RequestStatus makeRequest(PacketPtr pkt) override;
317  int outstandingCount() const override { return m_outstanding_count; }
318 
319  bool
320  isDeadlockEventScheduled() const override
321  {
322  return deadlockCheckEvent.scheduled();
323  }
324 
325  void
327  {
329  }
330 
331  bool empty() const;
332 
333  void print(std::ostream& out) const;
334 
335  void evictionCallback(Addr address);
336  void completeIssue();
337 
338  void insertKernel(int wavefront_id, PacketPtr pkt);
339 
341 
343 
346  { return *m_typeLatencyHist[t]; }
347 
349  { return m_missLatencyHist; }
351  { return *m_missTypeLatencyHist[t]; }
352 
354  { return *m_missMachLatencyHist[t]; }
355 
357  getMissTypeMachLatencyHist(uint32_t r, uint32_t t) const
358  { return *m_missTypeMachLatencyHist[r][t]; }
359 
361  { return *m_IssueToInitialDelayHist[t]; }
362 
364  getInitialToForwardDelayHist(const MachineType t) const
365  { return *m_InitialToForwardDelayHist[t]; }
366 
368  getForwardRequestToFirstResponseHist(const MachineType t) const
370 
372  getFirstResponseToCompletionDelayHist(const MachineType t) const
374 
375  protected:
376  bool tryCacheAccess(Addr addr, RubyRequestType type,
377  Addr pc, RubyAccessMode access_mode,
378  int size, DataBlock*& data_ptr);
379 
380  // since the two following issue functions are protocol-specific,
381  // they must be implemented in a derived coalescer
382  virtual void issueRequest(CoalescedRequest* crequest) = 0;
383  virtual void issueMemSyncRequest(PacketPtr pkt) {}
384 
385  void kernelCallback(int wavefront_id);
386 
387  void hitCallback(CoalescedRequest* crequest,
388  MachineType mach,
389  DataBlock& data,
390  bool success,
391  Cycles initialRequestTime,
392  Cycles forwardRequestTime,
393  Cycles firstResponseTime,
394  bool isRegion);
395  void recordMissLatency(CoalescedRequest* crequest,
396  MachineType mach,
397  Cycles initialRequestTime,
398  Cycles forwardRequestTime,
399  Cycles firstResponseTime,
400  bool success, bool isRegion);
402 
403  virtual RubyRequestType getRequestType(PacketPtr pkt);
404 
406 
407  // Attempt to remove a packet from the uncoalescedTable and coalesce
408  // with a previous request from the same instruction. If there is no
409  // previous instruction and the max number of outstanding requests has
410  // not be reached, a new coalesced request is created and added to the
411  // "target" list of the coalescedTable.
412  bool coalescePacket(PacketPtr pkt);
413 
415 
416  protected:
419 
422 
423  // coalescingWindow is the maximum number of instructions that are
424  // allowed to be coalesced in a single cycle.
426 
427  // The uncoalescedTable contains several "columns" which hold memory
428  // request packets for an instruction. The maximum size is the number of
429  // columns * the wavefront size.
431 
432  // An MSHR-like struct for holding coalesced requests. The requests in
433  // this table may or may not be outstanding in the memory hierarchy. The
434  // maximum size is equal to the maximum outstanding requests for a CU
435  // (typically the number of blocks in TCP). If there are duplicates of
436  // an address, the are serviced in age order.
437  std::map<Addr, std::deque<CoalescedRequest*>> coalescedTable;
438  // Map of instruction sequence number to coalesced requests that get
439  // created in coalescePacket, used in completeIssue to send the fully
440  // coalesced request
441  std::unordered_map<uint64_t, std::deque<CoalescedRequest*>> coalescedReqs;
442 
443  // a map btw an instruction sequence number and PendingWriteInst
444  // this is used to do a final call back for each write when it is
445  // completely done in the memory system
446  std::unordered_map<uint64_t, PendingWriteInst> pendingWriteInsts;
447 
448  // Global outstanding request count, across all request tables
451  std::unordered_map<int, PacketPtr> kernelEndList;
453 
458 
460 
463 
464 // TODO - Need to update the following stats once the VIPER protocol
465 // is re-integrated.
466 // // m5 style stats for TCP hit/miss counts
467 // statistics::Scalar GPU_TCPLdHits;
468 // statistics::Scalar GPU_TCPLdTransfers;
469 // statistics::Scalar GPU_TCCLdHits;
470 // statistics::Scalar GPU_LdMiss;
471 //
472 // statistics::Scalar GPU_TCPStHits;
473 // statistics::Scalar GPU_TCPStTransfers;
474 // statistics::Scalar GPU_TCCStHits;
475 // statistics::Scalar GPU_StMiss;
476 //
477 // statistics::Scalar CP_TCPLdHits;
478 // statistics::Scalar CP_TCPLdTransfers;
479 // statistics::Scalar CP_TCCLdHits;
480 // statistics::Scalar CP_LdMiss;
481 //
482 // statistics::Scalar CP_TCPStHits;
483 // statistics::Scalar CP_TCPStTransfers;
484 // statistics::Scalar CP_TCCStHits;
485 // statistics::Scalar CP_StMiss;
486 
489 
493 
498 
504 
510 
511 // TODO - Need to update the following stats once the VIPER protocol
512 // is re-integrated.
513 // statistics::Distribution numHopDelays;
514 // statistics::Distribution tcpToTccDelay;
515 // statistics::Distribution tccToSdDelay;
516 // statistics::Distribution sdToSdDelay;
517 // statistics::Distribution sdToTccDelay;
518 // statistics::Distribution tccToTcpDelay;
519 //
520 // statistics::Average avgTcpToTcc;
521 // statistics::Average avgTccToSd;
522 // statistics::Average avgSdToSd;
523 // statistics::Average avgSdToTcc;
524 // statistics::Average avgTccToTcp;
525 
526  private:
527  // Token port is used to send/receive tokens to/from GPU's global memory
528  // pipeline across the port boundary. There is one per <wave size> data
529  // ports in the CU.
531 
532  // Private copy constructor and assignment operator
533  GPUCoalescer(const GPUCoalescer& obj);
534  GPUCoalescer& operator=(const GPUCoalescer& obj);
535 };
536 
537 inline std::ostream&
538 operator<<(std::ostream& out, const GPUCoalescer& obj)
539 {
540  obj.print(out);
541  out << std::flush;
542  return out;
543 }
544 
545 } // namespace ruby
546 } // namespace gem5
547 
548 #endif // __MEM_RUBY_SYSTEM_GPU_COALESCER_HH__
gem5::ruby::GPUCoalescer::getRequestType
virtual RubyRequestType getRequestType(PacketPtr pkt)
Definition: GPUCoalescer.cc:599
gem5::ruby::GPUCoalescer::printRequestTable
void printRequestTable(std::stringstream &ss)
Definition: GPUCoalescer.cc:312
gem5::ruby::GPUCoalescer::kernelEndList
std::unordered_map< int, PacketPtr > kernelEndList
Definition: GPUCoalescer.hh:451
gem5::ruby::GPUCoalescer::GMTokenPort::~GMTokenPort
~GMTokenPort()
Definition: GPUCoalescer.hh:225
gem5::ruby::GPUCoalescer::m_load_waiting_on_load_cycles
int m_load_waiting_on_load_cycles
Definition: GPUCoalescer.hh:457
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::ruby::CoalescedRequest::setIssueTime
void setIssueTime(Cycles _issueTime)
Definition: GPUCoalescer.hh:119
gem5::ruby::GPUCoalescer::pendingWriteInsts
std::unordered_map< uint64_t, PendingWriteInst > pendingWriteInsts
Definition: GPUCoalescer.hh:446
gem5::ruby::GPUCoalescer::getTypeLatencyHist
statistics::Histogram & getTypeLatencyHist(uint32_t t)
Definition: GPUCoalescer.hh:345
gem5::Port::name
const std::string name() const
Return port name (for DPRINTF).
Definition: port.hh:111
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::ruby::GPUCoalescer::GMTokenPort::recvAtomic
Tick recvAtomic(PacketPtr)
Receive an atomic request packet from the peer.
Definition: GPUCoalescer.hh:228
gem5::ruby::PendingWriteInst::ackWriteCompletion
void ackWriteCompletion(bool usingRubyTester)
Definition: GPUCoalescer.hh:176
gem5::ruby::GPUCoalescer::m_typeLatencyHist
std::vector< statistics::Histogram * > m_typeLatencyHist
Definition: GPUCoalescer.hh:492
gem5::ruby::GPUCoalescer::getOutstandReqHist
statistics::Histogram & getOutstandReqHist()
Definition: GPUCoalescer.hh:342
gem5::ruby::GPUCoalescer::descheduleDeadlockEvent
void descheduleDeadlockEvent() override
Definition: GPUCoalescer.hh:326
gem5::ruby::GPUCoalescer::coalescedTable
std::map< Addr, std::deque< CoalescedRequest * > > coalescedTable
Definition: GPUCoalescer.hh:437
gem5::ruby::UncoalescedTable::packetAvailable
bool packetAvailable()
Definition: GPUCoalescer.cc:79
gem5::ruby::PendingWriteInst::getNumPendingStores
int getNumPendingStores()
Definition: GPUCoalescer.hh:197
gem5::ruby::GPUCoalescer::operator=
GPUCoalescer & operator=(const GPUCoalescer &obj)
gem5::ruby::GPUCoalescer::m_missTypeLatencyHist
std::vector< statistics::Histogram * > m_missTypeLatencyHist
Definition: GPUCoalescer.hh:497
gem5::ruby::operator<<
std::ostream & operator<<(std::ostream &os, const BoolVec &myvector)
Definition: BoolVec.cc:49
gem5::ruby::GPUCoalescer::issueMemSyncRequest
virtual void issueMemSyncRequest(PacketPtr pkt)
Definition: GPUCoalescer.hh:383
gem5::ruby::GPUCoalescer::GMTokenPort::getAddrRanges
AddrRangeList getAddrRanges() const
Get a list of the non-overlapping address ranges the owner is responsible for.
Definition: GPUCoalescer.hh:231
gem5::ruby::UncoalescedTable::setPacketsRemaining
void setPacketsRemaining(InstSeqNum seqNum, int count)
Definition: GPUCoalescer.cc:99
gem5::ruby::RubyPort::MemResponsePort
Definition: RubyPort.hh:81
gem5::Port::id
const PortID id
A numeric identifier to distinguish ports in a vector, and set to InvalidPortID in case this port is ...
Definition: port.hh:79
gem5::ruby::GPUCoalescer::coalescePacket
bool coalescePacket(PacketPtr pkt)
Definition: GPUCoalescer.cc:712
gem5::ruby::GPUCoalescer::wakeup
void wakeup()
Definition: GPUCoalescer.cc:286
misc.hh
gem5::ruby::GPUCoalescer::newKernelEnds
std::vector< int > newKernelEnds
Definition: GPUCoalescer.hh:452
gem5::ruby::UncoalescedTable::instMap
std::map< InstSeqNum, PerInstPackets > instMap
Definition: GPUCoalescer.hh:103
gem5::ruby::GPUCoalescer::getDynInst
GPUDynInstPtr getDynInst(PacketPtr pkt) const
Definition: GPUCoalescer.cc:699
std::vector
STL vector class.
Definition: stl.hh:37
gem5::ruby::GPUCoalescer::GMTokenPort::recvTimingReq
bool recvTimingReq(PacketPtr)
Receive a timing request from the peer.
Definition: GPUCoalescer.hh:230
gem5::ruby::GPUCoalescer::writeCallback
void writeCallback(Addr address, DataBlock &data)
Definition: GPUCoalescer.cc:381
gem5::ruby::PendingWriteInst::receiveWriteCompleteAck
bool receiveWriteCompleteAck()
Definition: GPUCoalescer.hh:167
gem5::ruby::CoalescedRequest::setRubyType
void setRubyType(RubyRequestType type)
Definition: GPUCoalescer.hh:120
gem5::ruby::GPUCoalescer::m_load_waiting_on_store_cycles
int m_load_waiting_on_store_cycles
Definition: GPUCoalescer.hh:456
gem5::ruby::CoalescedRequest::CoalescedRequest
CoalescedRequest(uint64_t _seqNum)
Definition: GPUCoalescer.hh:111
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:253
gem5::ruby::GPUCoalescer::GMTokenPort::recvFunctional
void recvFunctional(PacketPtr)
Receive a functional request packet from the peer.
Definition: GPUCoalescer.hh:229
gem5::ruby::GPUCoalescer::outstandingCount
int outstandingCount() const override
Definition: GPUCoalescer.hh:317
request.hh
gem5::ruby::GPUCoalescer::m_IssueToInitialDelayHist
std::vector< statistics::Histogram * > m_IssueToInitialDelayHist
Histograms for recording the breakdown of miss latency.
Definition: GPUCoalescer.hh:506
gem5::ruby::GPUCoalescer::evictionCallback
void evictionCallback(Addr address)
Definition: GPUCoalescer.cc:877
gem5::ruby::GPUCoalescer::m_deadlock_check_scheduled
bool m_deadlock_check_scheduled
Definition: GPUCoalescer.hh:450
gem5::ruby::UncoalescedTable::instPktsRemaining
std::map< InstSeqNum, int > instPktsRemaining
Definition: GPUCoalescer.hh:105
gem5::ruby::CoalescedRequest::getFirstPkt
PacketPtr getFirstPkt() const
Definition: GPUCoalescer.hh:123
gem5::ruby::GPUCoalescer::printProgress
void printProgress(std::ostream &out) const
Definition: GPUCoalescer.cc:361
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::ruby::CoalescedRequest::getIssueTime
Cycles getIssueTime() const
Definition: GPUCoalescer.hh:124
gem5::ruby::GPUCoalescer::~GPUCoalescer
~GPUCoalescer()
Definition: GPUCoalescer.cc:270
gem5::ruby::GPUCoalescer::getGMTokenPort
GMTokenPort & getGMTokenPort()
Definition: GPUCoalescer.hh:340
gem5::ruby::GPUCoalescer::getMissTypeMachLatencyHist
statistics::Histogram & getMissTypeMachLatencyHist(uint32_t r, uint32_t t) const
Definition: GPUCoalescer.hh:357
gem5::statistics::Histogram
A simple histogram stat.
Definition: statistics.hh:2123
gem5::ruby::GPUCoalescer::m_latencyHist
statistics::Histogram m_latencyHist
Histogram for holding latency profile of all requests.
Definition: GPUCoalescer.hh:491
gem5::ruby::GPUCoalescer::issueRequest
virtual void issueRequest(CoalescedRequest *crequest)=0
gem5::ruby::UncoalescedTable::~UncoalescedTable
~UncoalescedTable()
Definition: GPUCoalescer.hh:73
gem5::ruby::UncoalescedTable::getInstPackets
PerInstPackets * getInstPackets(int offset)
Definition: GPUCoalescer.cc:105
gem5::ruby::GPUCoalescer::tryCacheAccess
bool tryCacheAccess(Addr addr, RubyRequestType type, Addr pc, RubyAccessMode access_mode, int size, DataBlock *&data_ptr)
gem5::ruby::GPUCoalescer::getMissMachLatencyHist
statistics::Histogram & getMissMachLatencyHist(uint32_t t) const
Definition: GPUCoalescer.hh:353
gem5::ruby::GPUCoalescer::GMTokenPort
Definition: GPUCoalescer.hh:218
gem5::ruby::GPUCoalescer::recordMissLatency
void recordMissLatency(CoalescedRequest *crequest, MachineType mach, Cycles initialRequestTime, Cycles forwardRequestTime, Cycles firstResponseTime, bool success, bool isRegion)
Definition: GPUCoalescer.cc:955
gem5::ruby::PendingWriteInst::addPendingReq
void addPendingReq(RubyPort::MemResponsePort *port, GPUDynInstPtr inst, bool usingRubyTester)
Definition: GPUCoalescer.hh:152
gem5::ruby::GPUCoalescer::Params
RubyGPUCoalescerParams Params
Definition: GPUCoalescer.hh:238
gem5::ruby::CoalescedRequest::pkts
std::vector< PacketPtr > pkts
Definition: GPUCoalescer.hh:132
gem5::X86ISA::count
count
Definition: misc.hh:709
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::ruby::GPUCoalescer::isDeadlockEventScheduled
bool isDeadlockEventScheduled() const override
Definition: GPUCoalescer.hh:320
gem5::ruby::GPUCoalescer::getForwardRequestToFirstResponseHist
statistics::Histogram & getForwardRequestToFirstResponseHist(const MachineType t) const
Definition: GPUCoalescer.hh:368
gem5::ruby::GPUCoalescer::getMissLatencyHist
statistics::Histogram & getMissLatencyHist()
Definition: GPUCoalescer.hh:348
gem5::probing::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:109
statistics.hh
gem5::ruby::UncoalescedTable::updateResources
void updateResources()
Definition: GPUCoalescer.cc:118
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::X86ISA::type
type
Definition: misc.hh:733
gem5::ruby::GPUCoalescer::gmTokenPort
GMTokenPort gmTokenPort
Definition: GPUCoalescer.hh:530
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Definition: GPUCoalescer.hh:126
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Definition: GPUCoalescer.hh:64
gem5::ruby::GPUCoalescer::getMissTypeLatencyHist
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Definition: GPUCoalescer.hh:350
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Cycles m_deadlock_threshold
Definition: GPUCoalescer.hh:418
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statistics::Histogram & getFirstResponseToCompletionDelayHist(const MachineType t) const
Definition: GPUCoalescer.hh:372
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Definition: GPUCoalescer.cc:806
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bool sendTimingResp(PacketPtr pkt)
Attempt to send a timing response to the request port by calling its corresponding receive function.
Definition: port.hh:370
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Definition: GPUCoalescer.hh:209
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Definition: types.hh:144
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Definition: GPUCoalescer.hh:507
ss
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Definition: trace.test.cc:45
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bool empty() const
Definition: GPUCoalescer.cc:593
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Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: GPUCoalescer.cc:275
gem5::ruby::GPUCoalescer::coalescedReqs
std::unordered_map< uint64_t, std::deque< CoalescedRequest * > > coalescedReqs
Definition: GPUCoalescer.hh:441
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Definition: GPUCoalescer.cc:167
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Definition: GPUCoalescer.cc:63
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Definition: GPUCoalescer.cc:922
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Definition: misc_types.hh:70
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bool assumingRfOCoherence
Definition: GPUCoalescer.hh:462
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Definition: GPUCoalescer.hh:117
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Definition: GPUCoalescer.hh:414
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Definition: GPUCoalescer.hh:118
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Definition: GPUCoalescer.hh:139
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bool m_runningGarnetStandalone
Definition: GPUCoalescer.hh:459
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Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
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void writeCompleteCallback(Addr address, uint64_t instSeqNum, MachineType mach)
Definition: GPUCoalescer.cc:437
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SenderState * senderState
This packet's sender state.
Definition: packet.hh:534
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std::vector< statistics::Histogram * > m_ForwardToFirstResponseDelayHist
Definition: GPUCoalescer.hh:508
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std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition: misc.hh:51
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The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Definition: clocked_object.hh:234
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Definition: eventq.hh:1028
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GPUCoalescer(const Params &)
Definition: GPUCoalescer.cc:189
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Definition: GPUCoalescer.hh:461
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Definition: GPUCoalescer.hh:69
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Definition: eventq.hh:1115
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@ WriteCompleteResp
Definition: packet.hh:91
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void resetStats() override
Callback to reset stats.
Definition: GPUCoalescer.cc:338
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Definition: GPUCoalescer.cc:534
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Definition: GPUCoalescer.cc:467
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void initPacketsRemaining(InstSeqNum seqNum, int count)
Definition: GPUCoalescer.cc:85
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Definition: port.hh:279
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void collateStats()
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Definition: GPUCoalescer.hh:129
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Definition: GPUCoalescer.hh:420
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Definition: GPUCoalescer.hh:221
gem5::ruby::CoalescedRequest::getSeqNum
uint64_t getSeqNum() const
Definition: GPUCoalescer.hh:122
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Ports are used to interface objects to each other.
Definition: port.hh:61
Consumer.hh
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statistics::Histogram & getLatencyHist()
Definition: GPUCoalescer.hh:344
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int numPendingStores
Definition: GPUCoalescer.hh:203
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std::vector< std::vector< statistics::Histogram * > > m_missTypeMachLatencyHist
Definition: GPUCoalescer.hh:503
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Definition: GPUCoalescer.hh:97
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Definition: GPUCoalescer.hh:108
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statistics::Histogram m_outstandReqHist
Histogram for number of outstanding requests per cycle.
Definition: GPUCoalescer.hh:488
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void printRequestTable(std::stringstream &ss)
Definition: GPUCoalescer.cc:156
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Definition: GPUCoalescer.hh:430
gem5::ruby::UncoalescedTable::areRequestsDone
bool areRequestsDone(const InstSeqNum instSeqNum)
Definition: GPUCoalescer.cc:143
token_port.hh
gem5::ruby::GPUCoalescer::makeRequest
RequestStatus makeRequest(PacketPtr pkt) override
Definition: GPUCoalescer.cc:627
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Bitfield< 4 > pc
Definition: pra_constants.hh:243
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void kernelCallback(int wavefront_id)
Definition: GPUCoalescer.cc:883
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std::vector< statistics::Histogram * > m_missMachLatencyHist
Histograms for profiling the latencies for requests that required external messages.
Definition: GPUCoalescer.hh:501
gem5::ruby::GPUCoalescer::m_missLatencyHist
statistics::Histogram m_missLatencyHist
Histogram for holding latency profile of all requests that miss in the controller connected to this s...
Definition: GPUCoalescer.hh:496
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GPUDynInstPtr gpuDynInstPtr
Definition: GPUCoalescer.hh:212
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Definition: CacheMemory.hh:69
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int m_store_waiting_on_store_cycles
Definition: GPUCoalescer.hh:455
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uint64_t InstSeqNum
Definition: inst_seq.hh:40
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virtual void atomicCallback(Addr address, MachineType mach, const DataBlock &data)
Definition: GPUCoalescer.cc:893
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Cycles issueTime
Definition: GPUCoalescer.hh:130
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void insertKernel(int wavefront_id, PacketPtr pkt)
Definition: GPUCoalescer.cc:367
gem5::MipsISA::r
r
Definition: pra_constants.hh:98
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statistics::Histogram & getIssueToInitialDelayHist(uint32_t t) const
Definition: GPUCoalescer.hh:360
gem5::ruby::UncoalescedTable::getPacketsRemaining
int getPacketsRemaining(InstSeqNum seqNum)
Definition: GPUCoalescer.cc:93
gem5::ruby::GPUCoalescer::m_max_outstanding_requests
int m_max_outstanding_requests
Definition: GPUCoalescer.hh:417
gem5::ruby::UncoalescedTable::insertPacket
void insertPacket(PacketPtr pkt)
Definition: GPUCoalescer.cc:69
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Definition: DataBlock.hh:60
std::list
STL list class.
Definition: stl.hh:51
gem5::ruby::CoalescedRequest::getRubyType
RubyRequestType getRubyType() const
Definition: GPUCoalescer.hh:125
gem5::ruby::PendingWriteInst::~PendingWriteInst
~PendingWriteInst()
Definition: GPUCoalescer.hh:148
gem5::ruby::CoalescedRequest::~CoalescedRequest
~CoalescedRequest()
Definition: GPUCoalescer.hh:115
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
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int m_store_waiting_on_load_cycles
Definition: GPUCoalescer.hh:454
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int m_outstanding_count
Definition: GPUCoalescer.hh:449
gem5::ruby::PendingWriteInst::PendingWriteInst
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Definition: GPUCoalescer.hh:142
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Definition: RubyPort.hh:64
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std::vector< statistics::Histogram * > m_FirstResponseToCompletionDelayHist
Definition: GPUCoalescer.hh:509
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Definition: GPUCoalescer.hh:425
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Definition: token_port.hh:93
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void print(std::ostream &out) const
Definition: GPUCoalescer.cc:691
gem5::ruby::GPUCoalescer::m_instCache_ptr
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Definition: GPUCoalescer.hh:421
gem5::ruby::GPUCoalescer::getInitialToForwardDelayHist
statistics::Histogram & getInitialToForwardDelayHist(const MachineType t) const
Definition: GPUCoalescer.hh:364
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Definition: GPUCoalescer.hh:215
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Definition: compute_unit.hh:518
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
gem5::ruby::CoalescedRequest::rubyType
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Definition: GPUCoalescer.hh:131
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Bitfield< 3 > addr
Definition: types.hh:84
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RubyTester::SenderState SenderState
Definition: Check.cc:40
Sequencer.hh

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