gem5  v22.0.0.2
GPUCoalescer.hh
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31 
32 #ifndef __MEM_RUBY_SYSTEM_GPU_COALESCER_HH__
33 #define __MEM_RUBY_SYSTEM_GPU_COALESCER_HH__
34 
35 #include <iostream>
36 #include <unordered_map>
37 
38 #include "base/statistics.hh"
40 #include "gpu-compute/misc.hh"
41 #include "mem/request.hh"
44 #include "mem/ruby/protocol/PrefetchBit.hh"
45 #include "mem/ruby/protocol/RubyAccessMode.hh"
46 #include "mem/ruby/protocol/RubyRequestType.hh"
47 #include "mem/ruby/protocol/SequencerRequestType.hh"
49 #include "mem/token_port.hh"
50 
51 namespace gem5
52 {
53 
54 struct RubyGPUCoalescerParams;
55 
56 namespace ruby
57 {
58 
59 class DataBlock;
60 class CacheMsg;
61 struct MachineID;
63 
64 // List of packets that belongs to a specific instruction.
66 
68 {
69  public:
72 
73  void insertPacket(PacketPtr pkt);
74  bool packetAvailable();
75  void printRequestTable(std::stringstream& ss);
76 
77  // Modify packets remaining map. Init sets value iff the seqNum has not
78  // yet been seen before. get/set act as a regular getter/setter.
79  void initPacketsRemaining(InstSeqNum seqNum, int count);
80  int getPacketsRemaining(InstSeqNum seqNum);
81  void setPacketsRemaining(InstSeqNum seqNum, int count);
82 
83  // Returns a pointer to the list of packets corresponding to an
84  // instruction in the instruction map or nullptr if there are no
85  // instructions at the offset.
87  void updateResources();
88  bool areRequestsDone(const InstSeqNum instSeqNum);
89 
90  // Check if a packet hasn't been removed from instMap in too long.
91  // Panics if a deadlock is detected and returns nothing otherwise.
92  void checkDeadlock(Tick threshold);
93 
94  private:
96 
97  // Maps an instructions unique sequence number to a queue of packets
98  // which need responses. This data structure assumes the sequence number
99  // is monotonically increasing (which is true for CU class) in order to
100  // issue packets in age order.
101  std::map<InstSeqNum, PerInstPackets> instMap;
102 
103  std::map<InstSeqNum, int> instPktsRemaining;
104 };
105 
107 {
108  public:
109  CoalescedRequest(uint64_t _seqNum)
110  : seqNum(_seqNum), issueTime(Cycles(0)),
111  rubyType(RubyRequestType_NULL)
112  {}
114 
115  void insertPacket(PacketPtr pkt) { pkts.push_back(pkt); }
116  void setSeqNum(uint64_t _seqNum) { seqNum = _seqNum; }
117  void setIssueTime(Cycles _issueTime) { issueTime = _issueTime; }
118  void setRubyType(RubyRequestType type) { rubyType = type; }
119 
120  uint64_t getSeqNum() const { return seqNum; }
121  PacketPtr getFirstPkt() const { return pkts[0]; }
122  Cycles getIssueTime() const { return issueTime; }
123  RubyRequestType getRubyType() const { return rubyType; }
125 
126  private:
127  uint64_t seqNum;
129  RubyRequestType rubyType;
131 };
132 
133 // PendingWriteInst tracks the number of outstanding Ruby requests
134 // per write instruction. Once all requests associated with one instruction
135 // are completely done in Ruby, we call back the requestor to mark
136 // that this instruction is complete.
138 {
139  public:
141  : numPendingStores(0),
142  originalPort(nullptr),
143  gpuDynInstPtr(nullptr)
144  {}
145 
147  {}
148 
149  void
151  bool usingRubyTester)
152  {
153  assert(port);
154  originalPort = port;
155 
156  if (!usingRubyTester) {
157  gpuDynInstPtr = inst;
158  }
159 
161  }
162 
163  // return true if no more ack is expected
164  bool
166  {
167  assert(numPendingStores > 0);
169  return (numPendingStores == 0) ? true : false;
170  }
171 
172  // ack the original requestor that this write instruction is complete
173  void
174  ackWriteCompletion(bool usingRubyTester)
175  {
176  assert(numPendingStores == 0);
177 
178  // make a response packet
179  PacketPtr pkt = new Packet(std::make_shared<Request>(),
181 
182  if (!usingRubyTester) {
183  assert(gpuDynInstPtr);
186  (gpuDynInstPtr, 0, nullptr);
187  pkt->senderState = ss;
188  }
189 
190  // send the ack response to the requestor
192  }
193 
194  int
196  return numPendingStores;
197  }
198 
199  private:
200  // the number of stores waiting for writeCompleteCallback
202  // The original port that sent one of packets associated with this
203  // write instruction. We may have more than one packet per instruction,
204  // which implies multiple ports per instruction. However, we need
205  // only 1 of the ports to call back the CU. Therefore, here we keep
206  // track the port that sent the first packet of this instruction.
208  // similar to the originalPort, this gpuDynInstPtr is set only for
209  // the first packet of this instruction.
211 };
212 
213 class GPUCoalescer : public RubyPort
214 {
215  public:
217  {
218  public:
219  GMTokenPort(const std::string& name, ClockedObject *owner,
220  PortID id = InvalidPortID)
222  { }
224 
225  protected:
226  Tick recvAtomic(PacketPtr) { return Tick(0); }
228  bool recvTimingReq(PacketPtr) { return false; }
230  {
231  AddrRangeList ranges;
232  return ranges;
233  }
234  };
235 
236  typedef RubyGPUCoalescerParams Params;
237  GPUCoalescer(const Params &);
238  ~GPUCoalescer();
239 
240  Port &getPort(const std::string &if_name,
241  PortID idx = InvalidPortID) override;
242 
243  // Public Methods
244  void wakeup(); // Used only for deadlock detection
245  void printRequestTable(std::stringstream& ss);
246 
247  void printProgress(std::ostream& out) const;
248  void resetStats() override;
249  void collateStats();
250 
251  // each store request needs two callbacks:
252  // (1) writeCallback is called when the store is received and processed
253  // by TCP. This writeCallback does not guarantee the store is actually
254  // completed at its destination cache or memory. writeCallback helps
255  // release hardware resources (e.g., its entry in coalescedTable)
256  // allocated for the store so that subsequent requests will not be
257  // blocked unnecessarily due to hardware resource constraints.
258  // (2) writeCompleteCallback is called when the store is fully completed
259  // at its destination cache or memory. writeCompleteCallback
260  // guarantees that the store is fully completed. This callback
261  // will decrement hardware counters in CU
262  void writeCallback(Addr address, DataBlock& data);
263 
264  void writeCallback(Addr address,
265  MachineType mach,
266  DataBlock& data);
267 
268  void writeCallback(Addr address,
269  MachineType mach,
270  DataBlock& data,
271  Cycles initialRequestTime,
272  Cycles forwardRequestTime,
273  Cycles firstResponseTime,
274  bool isRegion);
275 
276  void writeCallback(Addr address,
277  MachineType mach,
278  DataBlock& data,
279  Cycles initialRequestTime,
280  Cycles forwardRequestTime,
281  Cycles firstResponseTime);
282 
283  void writeCompleteCallback(Addr address,
284  uint64_t instSeqNum,
285  MachineType mach);
286 
287  void readCallback(Addr address, DataBlock& data);
288 
289  void readCallback(Addr address,
290  MachineType mach,
291  DataBlock& data);
292 
293  void readCallback(Addr address,
294  MachineType mach,
295  DataBlock& data,
296  Cycles initialRequestTime,
297  Cycles forwardRequestTime,
298  Cycles firstResponseTime);
299 
300  void readCallback(Addr address,
301  MachineType mach,
302  DataBlock& data,
303  Cycles initialRequestTime,
304  Cycles forwardRequestTime,
305  Cycles firstResponseTime,
306  bool isRegion);
307 
308  /* atomics need their own callback because the data
309  might be const coming from SLICC */
310  virtual void atomicCallback(Addr address,
311  MachineType mach,
312  const DataBlock& data);
313 
314  RequestStatus makeRequest(PacketPtr pkt) override;
315  int outstandingCount() const override { return m_outstanding_count; }
316 
317  bool
318  isDeadlockEventScheduled() const override
319  {
320  return deadlockCheckEvent.scheduled();
321  }
322 
323  void
325  {
327  }
328 
329  bool empty() const;
330 
331  void print(std::ostream& out) const;
332 
333  void evictionCallback(Addr address);
334  void completeIssue();
335 
336  void insertKernel(int wavefront_id, PacketPtr pkt);
337 
339 
341 
344  { return *m_typeLatencyHist[t]; }
345 
347  { return m_missLatencyHist; }
349  { return *m_missTypeLatencyHist[t]; }
350 
352  { return *m_missMachLatencyHist[t]; }
353 
355  getMissTypeMachLatencyHist(uint32_t r, uint32_t t) const
356  { return *m_missTypeMachLatencyHist[r][t]; }
357 
359  { return *m_IssueToInitialDelayHist[t]; }
360 
362  getInitialToForwardDelayHist(const MachineType t) const
363  { return *m_InitialToForwardDelayHist[t]; }
364 
366  getForwardRequestToFirstResponseHist(const MachineType t) const
368 
370  getFirstResponseToCompletionDelayHist(const MachineType t) const
372 
373  protected:
374  bool tryCacheAccess(Addr addr, RubyRequestType type,
375  Addr pc, RubyAccessMode access_mode,
376  int size, DataBlock*& data_ptr);
377 
378  // since the two following issue functions are protocol-specific,
379  // they must be implemented in a derived coalescer
380  virtual void issueRequest(CoalescedRequest* crequest) = 0;
381  virtual void issueMemSyncRequest(PacketPtr pkt) {}
382 
383  void kernelCallback(int wavefront_id);
384 
385  void hitCallback(CoalescedRequest* crequest,
386  MachineType mach,
387  DataBlock& data,
388  bool success,
389  Cycles initialRequestTime,
390  Cycles forwardRequestTime,
391  Cycles firstResponseTime,
392  bool isRegion);
393  void recordMissLatency(CoalescedRequest* crequest,
394  MachineType mach,
395  Cycles initialRequestTime,
396  Cycles forwardRequestTime,
397  Cycles firstResponseTime,
398  bool success, bool isRegion);
400 
401  virtual RubyRequestType getRequestType(PacketPtr pkt);
402 
404 
405  // Attempt to remove a packet from the uncoalescedTable and coalesce
406  // with a previous request from the same instruction. If there is no
407  // previous instruction and the max number of outstanding requests has
408  // not be reached, a new coalesced request is created and added to the
409  // "target" list of the coalescedTable.
410  bool coalescePacket(PacketPtr pkt);
411 
413 
414  protected:
417 
420 
421  // coalescingWindow is the maximum number of instructions that are
422  // allowed to be coalesced in a single cycle.
424 
425  // The uncoalescedTable contains several "columns" which hold memory
426  // request packets for an instruction. The maximum size is the number of
427  // columns * the wavefront size.
429 
430  // An MSHR-like struct for holding coalesced requests. The requests in
431  // this table may or may not be outstanding in the memory hierarchy. The
432  // maximum size is equal to the maximum outstanding requests for a CU
433  // (typically the number of blocks in TCP). If there are duplicates of
434  // an address, the are serviced in age order.
435  std::map<Addr, std::deque<CoalescedRequest*>> coalescedTable;
436  // Map of instruction sequence number to coalesced requests that get
437  // created in coalescePacket, used in completeIssue to send the fully
438  // coalesced request
439  std::unordered_map<uint64_t, std::deque<CoalescedRequest*>> coalescedReqs;
440 
441  // a map btw an instruction sequence number and PendingWriteInst
442  // this is used to do a final call back for each write when it is
443  // completely done in the memory system
444  std::unordered_map<uint64_t, PendingWriteInst> pendingWriteInsts;
445 
446  // Global outstanding request count, across all request tables
449  std::unordered_map<int, PacketPtr> kernelEndList;
451 
456 
458 
461 
462 // TODO - Need to update the following stats once the VIPER protocol
463 // is re-integrated.
464 // // m5 style stats for TCP hit/miss counts
465 // statistics::Scalar GPU_TCPLdHits;
466 // statistics::Scalar GPU_TCPLdTransfers;
467 // statistics::Scalar GPU_TCCLdHits;
468 // statistics::Scalar GPU_LdMiss;
469 //
470 // statistics::Scalar GPU_TCPStHits;
471 // statistics::Scalar GPU_TCPStTransfers;
472 // statistics::Scalar GPU_TCCStHits;
473 // statistics::Scalar GPU_StMiss;
474 //
475 // statistics::Scalar CP_TCPLdHits;
476 // statistics::Scalar CP_TCPLdTransfers;
477 // statistics::Scalar CP_TCCLdHits;
478 // statistics::Scalar CP_LdMiss;
479 //
480 // statistics::Scalar CP_TCPStHits;
481 // statistics::Scalar CP_TCPStTransfers;
482 // statistics::Scalar CP_TCCStHits;
483 // statistics::Scalar CP_StMiss;
484 
487 
491 
496 
502 
508 
509 // TODO - Need to update the following stats once the VIPER protocol
510 // is re-integrated.
511 // statistics::Distribution numHopDelays;
512 // statistics::Distribution tcpToTccDelay;
513 // statistics::Distribution tccToSdDelay;
514 // statistics::Distribution sdToSdDelay;
515 // statistics::Distribution sdToTccDelay;
516 // statistics::Distribution tccToTcpDelay;
517 //
518 // statistics::Average avgTcpToTcc;
519 // statistics::Average avgTccToSd;
520 // statistics::Average avgSdToSd;
521 // statistics::Average avgSdToTcc;
522 // statistics::Average avgTccToTcp;
523 
524  private:
525  // Token port is used to send/receive tokens to/from GPU's global memory
526  // pipeline across the port boundary. There is one per <wave size> data
527  // ports in the CU.
529 
530  // Private copy constructor and assignment operator
531  GPUCoalescer(const GPUCoalescer& obj);
532  GPUCoalescer& operator=(const GPUCoalescer& obj);
533 };
534 
535 inline std::ostream&
536 operator<<(std::ostream& out, const GPUCoalescer& obj)
537 {
538  obj.print(out);
539  out << std::flush;
540  return out;
541 }
542 
543 } // namespace ruby
544 } // namespace gem5
545 
546 #endif // __MEM_RUBY_SYSTEM_GPU_COALESCER_HH__
gem5::ruby::GPUCoalescer::getRequestType
virtual RubyRequestType getRequestType(PacketPtr pkt)
Definition: GPUCoalescer.cc:598
gem5::ruby::GPUCoalescer::printRequestTable
void printRequestTable(std::stringstream &ss)
Definition: GPUCoalescer.cc:310
gem5::ruby::GPUCoalescer::kernelEndList
std::unordered_map< int, PacketPtr > kernelEndList
Definition: GPUCoalescer.hh:449
gem5::ruby::GPUCoalescer::GMTokenPort::~GMTokenPort
~GMTokenPort()
Definition: GPUCoalescer.hh:223
gem5::ruby::GPUCoalescer::m_load_waiting_on_load_cycles
int m_load_waiting_on_load_cycles
Definition: GPUCoalescer.hh:455
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:245
gem5::ruby::CoalescedRequest::setIssueTime
void setIssueTime(Cycles _issueTime)
Definition: GPUCoalescer.hh:117
gem5::ruby::GPUCoalescer::pendingWriteInsts
std::unordered_map< uint64_t, PendingWriteInst > pendingWriteInsts
Definition: GPUCoalescer.hh:444
gem5::ruby::GPUCoalescer::getTypeLatencyHist
statistics::Histogram & getTypeLatencyHist(uint32_t t)
Definition: GPUCoalescer.hh:343
gem5::Port::name
const std::string name() const
Return port name (for DPRINTF).
Definition: port.hh:111
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::ruby::GPUCoalescer::GMTokenPort::recvAtomic
Tick recvAtomic(PacketPtr)
Receive an atomic request packet from the peer.
Definition: GPUCoalescer.hh:226
gem5::ruby::PendingWriteInst::ackWriteCompletion
void ackWriteCompletion(bool usingRubyTester)
Definition: GPUCoalescer.hh:174
gem5::ruby::GPUCoalescer::m_typeLatencyHist
std::vector< statistics::Histogram * > m_typeLatencyHist
Definition: GPUCoalescer.hh:490
gem5::ruby::GPUCoalescer::getOutstandReqHist
statistics::Histogram & getOutstandReqHist()
Definition: GPUCoalescer.hh:340
gem5::ruby::GPUCoalescer::descheduleDeadlockEvent
void descheduleDeadlockEvent() override
Definition: GPUCoalescer.hh:324
gem5::ruby::GPUCoalescer::coalescedTable
std::map< Addr, std::deque< CoalescedRequest * > > coalescedTable
Definition: GPUCoalescer.hh:435
gem5::ruby::UncoalescedTable::packetAvailable
bool packetAvailable()
Definition: GPUCoalescer.cc:77
gem5::ruby::PendingWriteInst::getNumPendingStores
int getNumPendingStores()
Definition: GPUCoalescer.hh:195
gem5::ruby::GPUCoalescer::operator=
GPUCoalescer & operator=(const GPUCoalescer &obj)
gem5::ruby::GPUCoalescer::m_missTypeLatencyHist
std::vector< statistics::Histogram * > m_missTypeLatencyHist
Definition: GPUCoalescer.hh:495
gem5::ruby::operator<<
std::ostream & operator<<(std::ostream &os, const BoolVec &myvector)
Definition: BoolVec.cc:49
gem5::ruby::GPUCoalescer::issueMemSyncRequest
virtual void issueMemSyncRequest(PacketPtr pkt)
Definition: GPUCoalescer.hh:381
gem5::ruby::GPUCoalescer::GMTokenPort::getAddrRanges
AddrRangeList getAddrRanges() const
Get a list of the non-overlapping address ranges the owner is responsible for.
Definition: GPUCoalescer.hh:229
gem5::ruby::UncoalescedTable::setPacketsRemaining
void setPacketsRemaining(InstSeqNum seqNum, int count)
Definition: GPUCoalescer.cc:97
gem5::ruby::RubyPort::MemResponsePort
Definition: RubyPort.hh:81
gem5::Port::id
const PortID id
A numeric identifier to distinguish ports in a vector, and set to InvalidPortID in case this port is ...
Definition: port.hh:79
gem5::ruby::GPUCoalescer::coalescePacket
bool coalescePacket(PacketPtr pkt)
Definition: GPUCoalescer.cc:711
gem5::ruby::GPUCoalescer::wakeup
void wakeup()
Definition: GPUCoalescer.cc:284
misc.hh
gem5::ruby::GPUCoalescer::newKernelEnds
std::vector< int > newKernelEnds
Definition: GPUCoalescer.hh:450
gem5::ruby::UncoalescedTable::instMap
std::map< InstSeqNum, PerInstPackets > instMap
Definition: GPUCoalescer.hh:101
gem5::ruby::GPUCoalescer::getDynInst
GPUDynInstPtr getDynInst(PacketPtr pkt) const
Definition: GPUCoalescer.cc:698
std::vector
STL vector class.
Definition: stl.hh:37
gem5::ruby::GPUCoalescer::GMTokenPort::recvTimingReq
bool recvTimingReq(PacketPtr)
Receive a timing request from the peer.
Definition: GPUCoalescer.hh:228
gem5::ruby::GPUCoalescer::writeCallback
void writeCallback(Addr address, DataBlock &data)
Definition: GPUCoalescer.cc:379
gem5::VegaISA::r
Bitfield< 5 > r
Definition: pagetable.hh:60
gem5::ruby::PendingWriteInst::receiveWriteCompleteAck
bool receiveWriteCompleteAck()
Definition: GPUCoalescer.hh:165
gem5::ruby::CoalescedRequest::setRubyType
void setRubyType(RubyRequestType type)
Definition: GPUCoalescer.hh:118
gem5::ruby::GPUCoalescer::m_load_waiting_on_store_cycles
int m_load_waiting_on_store_cycles
Definition: GPUCoalescer.hh:454
gem5::ruby::CoalescedRequest::CoalescedRequest
CoalescedRequest(uint64_t _seqNum)
Definition: GPUCoalescer.hh:109
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:246
gem5::ruby::GPUCoalescer::GMTokenPort::recvFunctional
void recvFunctional(PacketPtr)
Receive a functional request packet from the peer.
Definition: GPUCoalescer.hh:227
gem5::ruby::GPUCoalescer::outstandingCount
int outstandingCount() const override
Definition: GPUCoalescer.hh:315
request.hh
gem5::ruby::GPUCoalescer::m_IssueToInitialDelayHist
std::vector< statistics::Histogram * > m_IssueToInitialDelayHist
Histograms for recording the breakdown of miss latency.
Definition: GPUCoalescer.hh:504
gem5::ruby::GPUCoalescer::evictionCallback
void evictionCallback(Addr address)
Definition: GPUCoalescer.cc:876
gem5::ruby::GPUCoalescer::m_deadlock_check_scheduled
bool m_deadlock_check_scheduled
Definition: GPUCoalescer.hh:448
gem5::ruby::UncoalescedTable::instPktsRemaining
std::map< InstSeqNum, int > instPktsRemaining
Definition: GPUCoalescer.hh:103
gem5::ruby::CoalescedRequest::getFirstPkt
PacketPtr getFirstPkt() const
Definition: GPUCoalescer.hh:121
gem5::ruby::GPUCoalescer::printProgress
void printProgress(std::ostream &out) const
Definition: GPUCoalescer.cc:359
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::ruby::CoalescedRequest::getIssueTime
Cycles getIssueTime() const
Definition: GPUCoalescer.hh:122
gem5::ruby::GPUCoalescer::~GPUCoalescer
~GPUCoalescer()
Definition: GPUCoalescer.cc:268
gem5::ruby::GPUCoalescer::getGMTokenPort
GMTokenPort & getGMTokenPort()
Definition: GPUCoalescer.hh:338
gem5::ruby::GPUCoalescer::getMissTypeMachLatencyHist
statistics::Histogram & getMissTypeMachLatencyHist(uint32_t r, uint32_t t) const
Definition: GPUCoalescer.hh:355
gem5::statistics::Histogram
A simple histogram stat.
Definition: statistics.hh:2126
gem5::ruby::GPUCoalescer::m_latencyHist
statistics::Histogram m_latencyHist
Histogram for holding latency profile of all requests.
Definition: GPUCoalescer.hh:489
gem5::ruby::GPUCoalescer::issueRequest
virtual void issueRequest(CoalescedRequest *crequest)=0
gem5::ruby::UncoalescedTable::~UncoalescedTable
~UncoalescedTable()
Definition: GPUCoalescer.hh:71
gem5::ruby::UncoalescedTable::getInstPackets
PerInstPackets * getInstPackets(int offset)
Definition: GPUCoalescer.cc:103
gem5::ruby::GPUCoalescer::tryCacheAccess
bool tryCacheAccess(Addr addr, RubyRequestType type, Addr pc, RubyAccessMode access_mode, int size, DataBlock *&data_ptr)
gem5::ruby::GPUCoalescer::getMissMachLatencyHist
statistics::Histogram & getMissMachLatencyHist(uint32_t t) const
Definition: GPUCoalescer.hh:351
gem5::ruby::GPUCoalescer::GMTokenPort
Definition: GPUCoalescer.hh:216
gem5::ruby::GPUCoalescer::recordMissLatency
void recordMissLatency(CoalescedRequest *crequest, MachineType mach, Cycles initialRequestTime, Cycles forwardRequestTime, Cycles firstResponseTime, bool success, bool isRegion)
Definition: GPUCoalescer.cc:954
gem5::VegaISA::t
Bitfield< 51 > t
Definition: pagetable.hh:56
gem5::ruby::PendingWriteInst::addPendingReq
void addPendingReq(RubyPort::MemResponsePort *port, GPUDynInstPtr inst, bool usingRubyTester)
Definition: GPUCoalescer.hh:150
gem5::ruby::GPUCoalescer::Params
RubyGPUCoalescerParams Params
Definition: GPUCoalescer.hh:236
gem5::ruby::CoalescedRequest::pkts
std::vector< PacketPtr > pkts
Definition: GPUCoalescer.hh:130
gem5::X86ISA::count
count
Definition: misc.hh:703
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::ruby::GPUCoalescer::isDeadlockEventScheduled
bool isDeadlockEventScheduled() const override
Definition: GPUCoalescer.hh:318
gem5::ruby::GPUCoalescer::getForwardRequestToFirstResponseHist
statistics::Histogram & getForwardRequestToFirstResponseHist(const MachineType t) const
Definition: GPUCoalescer.hh:366
gem5::ruby::GPUCoalescer::getMissLatencyHist
statistics::Histogram & getMissLatencyHist()
Definition: GPUCoalescer.hh:346
gem5::probing::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:109
statistics.hh
gem5::ruby::UncoalescedTable::updateResources
void updateResources()
Definition: GPUCoalescer.cc:116
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::X86ISA::type
type
Definition: misc.hh:727
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Definition: GPUCoalescer.hh:528
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Definition: GPUCoalescer.hh:124
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Definition: GPUCoalescer.hh:62
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Definition: GPUCoalescer.hh:348
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Cycles m_deadlock_threshold
Definition: GPUCoalescer.hh:416
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Definition: GPUCoalescer.hh:370
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void completeIssue()
Definition: GPUCoalescer.cc:805
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bool sendTimingResp(PacketPtr pkt)
Attempt to send a timing response to the request port by calling its corresponding receive function.
Definition: port.hh:370
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Definition: GPUCoalescer.hh:207
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std::vector< statistics::Histogram * > m_InitialToForwardDelayHist
Definition: GPUCoalescer.hh:505
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Definition: trace.test.cc:45
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bool empty() const
Definition: GPUCoalescer.cc:592
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Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: GPUCoalescer.cc:273
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Definition: GPUCoalescer.hh:439
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Definition: GPUCoalescer.cc:165
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UncoalescedTable(GPUCoalescer *gc)
Definition: GPUCoalescer.cc:61
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Definition: GPUCoalescer.cc:921
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Definition: GPUCoalescer.hh:460
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Definition: GPUCoalescer.hh:115
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Definition: GPUCoalescer.hh:412
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Definition: GPUCoalescer.hh:116
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Definition: GPUCoalescer.hh:137
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Definition: GPUCoalescer.hh:457
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Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
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void writeCompleteCallback(Addr address, uint64_t instSeqNum, MachineType mach)
Definition: GPUCoalescer.cc:435
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SenderState * senderState
This packet's sender state.
Definition: packet.hh:542
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std::vector< statistics::Histogram * > m_ForwardToFirstResponseDelayHist
Definition: GPUCoalescer.hh:506
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Definition: misc.hh:49
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The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Definition: clocked_object.hh:234
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Definition: eventq.hh:1028
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Definition: GPUCoalescer.cc:187
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Definition: GPUCoalescer.hh:459
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Definition: GPUCoalescer.hh:67
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Definition: eventq.hh:1115
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@ WriteCompleteResp
Definition: packet.hh:91
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void resetStats() override
Callback to reset stats.
Definition: GPUCoalescer.cc:336
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Definition: GPUCoalescer.cc:532
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Definition: GPUCoalescer.cc:465
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Definition: GPUCoalescer.cc:83
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Definition: port.hh:279
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void collateStats()
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Definition: GPUCoalescer.hh:127
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Definition: GPUCoalescer.hh:418
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Definition: GPUCoalescer.hh:219
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uint64_t getSeqNum() const
Definition: GPUCoalescer.hh:120
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Ports are used to interface objects to each other.
Definition: port.hh:61
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statistics::Histogram & getLatencyHist()
Definition: GPUCoalescer.hh:342
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Definition: GPUCoalescer.hh:201
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std::vector< std::vector< statistics::Histogram * > > m_missTypeMachLatencyHist
Definition: GPUCoalescer.hh:501
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Definition: GPUCoalescer.hh:95
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Definition: GPUCoalescer.hh:106
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statistics::Histogram m_outstandReqHist
Histogram for number of outstanding requests per cycle.
Definition: GPUCoalescer.hh:486
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void printRequestTable(std::stringstream &ss)
Definition: GPUCoalescer.cc:154
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Definition: GPUCoalescer.hh:428
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bool areRequestsDone(const InstSeqNum instSeqNum)
Definition: GPUCoalescer.cc:141
token_port.hh
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RequestStatus makeRequest(PacketPtr pkt) override
Definition: GPUCoalescer.cc:626
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Bitfield< 4 > pc
Definition: pra_constants.hh:243
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void kernelCallback(int wavefront_id)
Definition: GPUCoalescer.cc:882
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std::vector< statistics::Histogram * > m_missMachLatencyHist
Histograms for profiling the latencies for requests that required external messages.
Definition: GPUCoalescer.hh:499
gem5::ruby::GPUCoalescer::m_missLatencyHist
statistics::Histogram m_missLatencyHist
Histogram for holding latency profile of all requests that miss in the controller connected to this s...
Definition: GPUCoalescer.hh:494
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Definition: GPUCoalescer.hh:210
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Definition: CacheMemory.hh:69
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int m_store_waiting_on_store_cycles
Definition: GPUCoalescer.hh:453
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Definition: inst_seq.hh:40
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virtual void atomicCallback(Addr address, MachineType mach, const DataBlock &data)
Definition: GPUCoalescer.cc:892
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Cycles issueTime
Definition: GPUCoalescer.hh:128
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void insertKernel(int wavefront_id, PacketPtr pkt)
Definition: GPUCoalescer.cc:365
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statistics::Histogram & getIssueToInitialDelayHist(uint32_t t) const
Definition: GPUCoalescer.hh:358
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int getPacketsRemaining(InstSeqNum seqNum)
Definition: GPUCoalescer.cc:91
gem5::ruby::GPUCoalescer::m_max_outstanding_requests
int m_max_outstanding_requests
Definition: GPUCoalescer.hh:415
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void insertPacket(PacketPtr pkt)
Definition: GPUCoalescer.cc:67
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Definition: DataBlock.hh:60
std::list
STL list class.
Definition: stl.hh:51
gem5::ruby::CoalescedRequest::getRubyType
RubyRequestType getRubyType() const
Definition: GPUCoalescer.hh:123
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~PendingWriteInst()
Definition: GPUCoalescer.hh:146
gem5::ruby::CoalescedRequest::~CoalescedRequest
~CoalescedRequest()
Definition: GPUCoalescer.hh:113
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
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int m_store_waiting_on_load_cycles
Definition: GPUCoalescer.hh:452
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int m_outstanding_count
Definition: GPUCoalescer.hh:447
gem5::ruby::PendingWriteInst::PendingWriteInst
PendingWriteInst()
Definition: GPUCoalescer.hh:140
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Definition: RubyPort.hh:64
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std::vector< statistics::Histogram * > m_FirstResponseToCompletionDelayHist
Definition: GPUCoalescer.hh:507
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int coalescingWindow
Definition: GPUCoalescer.hh:423
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Definition: token_port.hh:91
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void print(std::ostream &out) const
Definition: GPUCoalescer.cc:690
gem5::ruby::GPUCoalescer::m_instCache_ptr
CacheMemory * m_instCache_ptr
Definition: GPUCoalescer.hh:419
gem5::ruby::GPUCoalescer::getInitialToForwardDelayHist
statistics::Histogram & getInitialToForwardDelayHist(const MachineType t) const
Definition: GPUCoalescer.hh:362
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Definition: GPUCoalescer.hh:213
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Definition: compute_unit.hh:519
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
gem5::ruby::CoalescedRequest::rubyType
RubyRequestType rubyType
Definition: GPUCoalescer.hh:129
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Bitfield< 3 > addr
Definition: types.hh:84
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RubyTester::SenderState SenderState
Definition: Check.cc:40
Sequencer.hh

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