gem5  v21.1.0.2
CacheMemory.hh
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41 
42 #ifndef __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__
43 #define __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__
44 
45 #include <string>
46 #include <unordered_map>
47 #include <vector>
48 
49 #include "base/statistics.hh"
53 #include "mem/ruby/protocol/CacheRequestType.hh"
54 #include "mem/ruby/protocol/CacheResourceType.hh"
55 #include "mem/ruby/protocol/RubyRequest.hh"
60 #include "params/RubyCache.hh"
61 #include "sim/sim_object.hh"
62 
63 namespace gem5
64 {
65 
66 namespace ruby
67 {
68 
69 class CacheMemory : public SimObject
70 {
71  public:
72  typedef RubyCacheParams Params;
73  typedef std::shared_ptr<replacement_policy::ReplacementData> ReplData;
74  CacheMemory(const Params &p);
75  ~CacheMemory();
76 
77  void init();
78 
79  // Public Methods
80  // perform a cache access and see if we hit or not. Return true on a hit.
81  bool tryCacheAccess(Addr address, RubyRequestType type,
82  DataBlock*& data_ptr);
83 
84  // similar to above, but doesn't require full access check
85  bool testCacheAccess(Addr address, RubyRequestType type,
86  DataBlock*& data_ptr);
87 
88  // tests to see if an address is present in the cache
89  bool isTagPresent(Addr address) const;
90 
91  // Returns true if there is:
92  // a) a tag match on this address or there is
93  // b) an unused line in the same cache "way"
94  bool cacheAvail(Addr address) const;
95 
96  // Returns a NULL entry that acts as a placeholder for invalid lines
98  getNullEntry() const
99  {
100  return nullptr;
101  }
102 
103  // find an unused entry and sets the tag appropriate for the address
104  AbstractCacheEntry* allocate(Addr address, AbstractCacheEntry* new_entry);
105  void allocateVoid(Addr address, AbstractCacheEntry* new_entry)
106  {
107  allocate(address, new_entry);
108  }
109 
110  // Explicitly free up this address
111  void deallocate(Addr address);
112 
113  // Returns with the physical address of the conflicting cache line
114  Addr cacheProbe(Addr address) const;
115 
116  // looks an address up in the cache
117  AbstractCacheEntry* lookup(Addr address);
118  const AbstractCacheEntry* lookup(Addr address) const;
119 
120  Cycles getTagLatency() const { return tagArray.getLatency(); }
122 
123  bool isBlockInvalid(int64_t cache_set, int64_t loc);
124  bool isBlockNotBusy(int64_t cache_set, int64_t loc);
125 
126  // Hook for checkpointing the contents of the cache
127  void recordCacheContents(int cntrl, CacheRecorder* tr) const;
128 
129  // Set this address to most recently used
130  void setMRU(Addr address);
131  void setMRU(Addr addr, int occupancy);
132  void setMRU(AbstractCacheEntry* entry);
133  int getReplacementWeight(int64_t set, int64_t loc);
134 
135  // Functions for locking and unlocking cache lines corresponding to the
136  // provided address. These are required for supporting atomic memory
137  // accesses. These are to be used when only the address of the cache entry
138  // is available. In case the entry itself is available. use the functions
139  // provided by the AbstractCacheEntry class.
140  void setLocked (Addr addr, int context);
141  void clearLocked (Addr addr);
142  void clearLockedAll (int context);
143  bool isLocked (Addr addr, int context);
144 
145  // Print cache contents
146  void print(std::ostream& out) const;
147  void printData(std::ostream& out) const;
148 
149  bool checkResourceAvailable(CacheResourceType res, Addr addr);
150  void recordRequestType(CacheRequestType requestType, Addr addr);
151 
152  // hardware transactional memory
153  void htmAbortTransaction();
154  void htmCommitTransaction();
155 
156  public:
157  int getCacheSize() const { return m_cache_size; }
158  int getCacheAssoc() const { return m_cache_assoc; }
159  int getNumBlocks() const { return m_cache_num_sets * m_cache_assoc; }
160  Addr getAddressAtIdx(int idx) const;
161 
162  private:
163  // convert a Address to its location in the cache
164  int64_t addressToCacheSet(Addr address) const;
165 
166  // Given a cache tag: returns the index of the tag in a set.
167  // returns -1 if the tag is not found.
168  int findTagInSet(int64_t line, Addr tag) const;
169  int findTagInSetIgnorePermissions(int64_t cacheSet, Addr tag) const;
170 
171  // Private copy constructor and assignment operator
172  CacheMemory(const CacheMemory& obj);
173  CacheMemory& operator=(const CacheMemory& obj);
174 
175  private:
176  // Data Members (m_prefix)
178 
179  // The first index is the # of cache lines.
180  // The second index is the the amount associativity.
181  std::unordered_map<Addr, int> m_tag_index;
183 
186 
189 
197 
207 
213 
214  private:
216  {
218 
223 
226 
227  // hardware transactional memory
232 
236 
240 
243 
244  public:
245  // These function increment the number of demand hits/misses by one
246  // each time they are called
247  void profileDemandHit();
248  void profileDemandMiss();
249  void profilePrefetchHit();
250  void profilePrefetchMiss();
251 };
252 
253 std::ostream& operator<<(std::ostream& out, const CacheMemory& obj);
254 
255 } // namespace ruby
256 } // namespace gem5
257 
258 #endif // __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1927
gem5::ruby::CacheMemory::CacheMemoryStats::m_prefetch_hits
statistics::Scalar m_prefetch_hits
Definition: CacheMemory.hh:237
gem5::ruby::CacheMemory::profileDemandHit
void profileDemandHit()
Definition: CacheMemory.cc:751
gem5::ruby::CacheMemory::CacheMemoryStats::m_prefetch_accesses
statistics::Formula m_prefetch_accesses
Definition: CacheMemory.hh:239
gem5::ruby::CacheMemory::tagArray
BankedArray tagArray
Definition: CacheMemory.hh:188
gem5::ruby::CacheMemory::m_replacementPolicy_ptr
replacement_policy::Base * m_replacementPolicy_ptr
We use the replacement policies from the Classic memory system.
Definition: CacheMemory.hh:185
gem5::ruby::CacheMemory::profileDemandMiss
void profileDemandMiss()
Definition: CacheMemory.cc:757
gem5::ruby::CacheMemory::htmCommitTransaction
void htmCommitTransaction()
Definition: CacheMemory.cc:721
gem5::ruby::CacheMemory::CacheMemoryStats::m_prefetch_misses
statistics::Scalar m_prefetch_misses
Definition: CacheMemory.hh:238
gem5::ruby::CacheMemory::getAddressAtIdx
Addr getAddressAtIdx(int idx) const
Definition: CacheMemory.cc:166
gem5::ruby::CacheMemory::isBlockInvalid
bool isBlockInvalid(int64_t cache_set, int64_t loc)
Definition: CacheMemory.cc:673
gem5::ruby::CacheMemory::htmAbortTransaction
void htmAbortTransaction()
Definition: CacheMemory.cc:687
gem5::ruby::operator<<
std::ostream & operator<<(std::ostream &os, const BoolVec &myvector)
Definition: BoolVec.cc:49
gem5::ruby::CacheMemory::m_block_size
int m_block_size
Definition: CacheMemory.hh:196
gem5::ruby::BankedArray
Definition: BankedArray.hh:46
gem5::ruby::CacheMemory::Params
RubyCacheParams Params
Definition: CacheMemory.hh:72
gem5::ruby::AbstractCacheEntry
Definition: AbstractCacheEntry.hh:62
gem5::ruby::CacheMemory::print
void print(std::ostream &out) const
Definition: CacheMemory.cc:454
gem5::ruby::CacheMemory::getReplacementWeight
int getReplacementWeight(int64_t set, int64_t loc)
Definition: CacheMemory.cc:401
gem5::ruby::CacheMemory::cacheMemoryStats
gem5::ruby::CacheMemory::CacheMemoryStats cacheMemoryStats
gem5::ruby::CacheMemory::tryCacheAccess
bool tryCacheAccess(Addr address, RubyRequestType type, DataBlock *&data_ptr)
Definition: CacheMemory.cc:186
gem5::ruby::CacheMemory::CacheMemory
CacheMemory(const Params &p)
Definition: CacheMemory.cc:70
gem5::ruby::CacheMemory::CacheMemoryStats::numTagArrayWrites
statistics::Scalar numTagArrayWrites
Definition: CacheMemory.hh:222
gem5::ruby::CacheMemory::getCacheSize
int getCacheSize() const
Definition: CacheMemory.hh:157
gem5::statistics::Vector
A vector of scalar stats.
Definition: statistics.hh:2003
gem5::ruby::CacheMemory::addressToCacheSet
int64_t addressToCacheSet(Addr address) const
Definition: CacheMemory.cc:126
gem5::ruby::BankedArray::getLatency
Cycles getLatency() const
Definition: BankedArray.hh:80
gem5::ruby::CacheMemory::CacheMemoryStats::htmTransCommitReadSet
statistics::Histogram htmTransCommitReadSet
Definition: CacheMemory.hh:228
gem5::statistics::Formula
A formula for statistics that is calculated when printed.
Definition: statistics.hh:2536
std::vector
STL vector class.
Definition: stl.hh:37
gem5::ruby::CacheMemory::cacheProbe
Addr cacheProbe(Addr address) const
Definition: CacheMemory.cc:325
BankedArray.hh
gem5::ruby::CacheMemory::operator=
CacheMemory & operator=(const CacheMemory &obj)
gem5::ruby::CacheMemory::lookup
AbstractCacheEntry * lookup(Addr address)
Definition: CacheMemory.cc:342
AbstractCacheEntry.hh
gem5::ruby::CacheMemory::m_cache_num_set_bits
int m_cache_num_set_bits
Definition: CacheMemory.hh:192
gem5::ruby::CacheMemory::findTagInSet
int findTagInSet(int64_t line, Addr tag) const
Definition: CacheMemory.cc:136
gem5::ruby::CacheMemory::dataArray
BankedArray dataArray
Definition: CacheMemory.hh:187
gem5::ruby::CacheMemory::isTagPresent
bool isTagPresent(Addr address) const
Definition: CacheMemory.cc:231
gem5::ruby::CacheMemory::ReplData
std::shared_ptr< replacement_policy::ReplacementData > ReplData
Definition: CacheMemory.hh:73
gem5::ruby::CacheMemory::m_cache
std::vector< std::vector< AbstractCacheEntry * > > m_cache
Definition: CacheMemory.hh:182
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::ruby::CacheMemory::CacheMemoryStats::numTagArrayStalls
statistics::Scalar numTagArrayStalls
Definition: CacheMemory.hh:224
replaceable_entry.hh
gem5::statistics::Histogram
A simple histogram stat.
Definition: statistics.hh:2123
gem5::ruby::CacheMemory::m_tag_index
std::unordered_map< Addr, int > m_tag_index
Definition: CacheMemory.hh:181
gem5::ruby::CacheMemory::printData
void printData(std::ostream &out) const
Definition: CacheMemory.cc:473
gem5::ruby::CacheMemory::m_cache_assoc
int m_cache_assoc
Definition: CacheMemory.hh:193
gem5::ruby::CacheMemory::CacheMemoryStats::m_demand_misses
statistics::Scalar m_demand_misses
Definition: CacheMemory.hh:234
gem5::ruby::CacheMemory::CacheMemoryStats::numDataArrayWrites
statistics::Scalar numDataArrayWrites
Definition: CacheMemory.hh:220
sim_object.hh
gem5::ruby::CacheMemory::CacheMemoryStats::CacheMemoryStats
CacheMemoryStats(statistics::Group *parent)
Definition: CacheMemory.cc:524
gem5::ruby::CacheMemory::m_start_index_bit
int m_start_index_bit
Definition: CacheMemory.hh:194
gem5::ruby::CacheMemory::allocate
AbstractCacheEntry * allocate(Addr address, AbstractCacheEntry *new_entry)
Definition: CacheMemory.cc:269
gem5::ruby::CacheMemory::getCacheAssoc
int getCacheAssoc() const
Definition: CacheMemory.hh:158
DataBlock.hh
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
statistics.hh
gem5::X86ISA::type
type
Definition: misc.hh:733
gem5::ruby::CacheMemory::cacheAvail
bool cacheAvail(Addr address) const
Definition: CacheMemory.cc:247
gem5::ruby::CacheMemory::CacheMemoryStats::numDataArrayStalls
statistics::Scalar numDataArrayStalls
Definition: CacheMemory.hh:225
gem5::ruby::CacheMemory::CacheMemoryStats::numDataArrayReads
statistics::Scalar numDataArrayReads
Definition: CacheMemory.hh:219
gem5::ruby::CacheMemory::checkResourceAvailable
bool checkResourceAvailable(CacheResourceType res, Addr addr)
Definition: CacheMemory.cc:643
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::ruby::CacheMemory::getNumBlocks
int getNumBlocks() const
Definition: CacheMemory.hh:159
gem5::ruby::CacheMemory::~CacheMemory
~CacheMemory()
Definition: CacheMemory.cc:113
gem5::replacement_policy::Base
A common base class of cache replacement policy objects.
Definition: base.hh:55
base.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ruby::CacheMemory::m_cache_num_sets
int m_cache_num_sets
Definition: CacheMemory.hh:191
gem5::ruby::CacheMemory::findTagInSetIgnorePermissions
int findTagInSetIgnorePermissions(int64_t cacheSet, Addr tag) const
Definition: CacheMemory.cc:151
RubySlicc_ComponentMapping.hh
gem5::ruby::CacheMemory::m_resource_stalls
bool m_resource_stalls
Definition: CacheMemory.hh:195
gem5::ruby::CacheMemory::testCacheAccess
bool testCacheAccess(Addr address, RubyRequestType type, DataBlock *&data_ptr)
Definition: CacheMemory.cc:211
gem5::ruby::CacheMemory::recordCacheContents
void recordCacheContents(int cntrl, CacheRecorder *tr) const
Definition: CacheMemory.cc:415
gem5::ruby::CacheMemory::setMRU
void setMRU(Addr address)
Definition: CacheMemory.cc:364
gem5::ruby::CacheMemory::m_is_instruction_only_cache
bool m_is_instruction_only_cache
Definition: CacheMemory.hh:177
gem5::ruby::CacheMemory::isBlockNotBusy
bool isBlockNotBusy(int64_t cache_set, int64_t loc)
Definition: CacheMemory.cc:679
gem5::ruby::CacheMemory::setLocked
void setLocked(Addr addr, int context)
Definition: CacheMemory.cc:479
gem5::ruby::CacheMemory::isLocked
bool isLocked(Addr addr, int context)
Definition: CacheMemory.cc:514
gem5::ruby::CacheMemory::getNullEntry
AbstractCacheEntry * getNullEntry() const
Definition: CacheMemory.hh:98
gem5::ruby::CacheMemory::getDataLatency
Cycles getDataLatency() const
Definition: CacheMemory.hh:121
gem5::ruby::CacheMemory::init
void init()
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: CacheMemory.cc:90
gem5::ruby::CacheMemory::profilePrefetchHit
void profilePrefetchHit()
Definition: CacheMemory.cc:763
gem5::ruby::CacheMemory::CacheMemoryStats::m_demand_accesses
statistics::Formula m_demand_accesses
Definition: CacheMemory.hh:235
gem5::ruby::CacheMemory::m_use_occupancy
bool m_use_occupancy
Set to true when using WeightedLRU replacement policy, otherwise, set to false.
Definition: CacheMemory.hh:212
gem5::ruby::CacheMemory::clearLocked
void clearLocked(Addr addr)
Definition: CacheMemory.cc:488
gem5::ruby::CacheMemory
Definition: CacheMemory.hh:69
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::ruby::CacheMemory::CacheMemoryStats::htmTransAbortReadSet
statistics::Histogram htmTransAbortReadSet
Definition: CacheMemory.hh:230
gem5::ruby::CacheMemory::clearLockedAll
void clearLockedAll(int context)
Definition: CacheMemory.cc:497
gem5::ruby::CacheMemory::CacheMemoryStats::htmTransAbortWriteSet
statistics::Histogram htmTransAbortWriteSet
Definition: CacheMemory.hh:231
gem5::ruby::CacheMemory::CacheMemoryStats::htmTransCommitWriteSet
statistics::Histogram htmTransCommitWriteSet
Definition: CacheMemory.hh:229
gem5::ruby::DataBlock
Definition: DataBlock.hh:60
gem5::ruby::CacheMemory::CacheMemoryStats::numTagArrayReads
statistics::Scalar numTagArrayReads
Definition: CacheMemory.hh:221
CacheRecorder.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ruby::CacheMemory::CacheMemoryStats
Definition: CacheMemory.hh:215
gem5::ruby::CacheMemory::profilePrefetchMiss
void profilePrefetchMiss()
Definition: CacheMemory.cc:769
gem5::ruby::CacheMemory::getTagLatency
Cycles getTagLatency() const
Definition: CacheMemory.hh:120
gem5::ruby::CacheMemory::m_cache_size
int m_cache_size
Definition: CacheMemory.hh:190
gem5::ruby::CacheMemory::recordRequestType
void recordRequestType(CacheRequestType requestType, Addr addr)
Definition: CacheMemory.cc:611
gem5::ruby::CacheMemory::deallocate
void deallocate(Addr address)
Definition: CacheMemory.cc:310
gem5::ruby::CacheRecorder
Definition: CacheRecorder.hh:73
gem5::ruby::CacheMemory::replacement_data
std::vector< std::vector< ReplData > > replacement_data
We store all the ReplacementData in a 2-dimensional array.
Definition: CacheMemory.hh:206
gem5::ruby::CacheMemory::allocateVoid
void allocateVoid(Addr address, AbstractCacheEntry *new_entry)
Definition: CacheMemory.hh:105
gem5::ruby::CacheMemory::CacheMemoryStats::m_demand_hits
statistics::Scalar m_demand_hits
Definition: CacheMemory.hh:233
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::ruby::CacheMemory::CacheMemoryStats::m_accessModeType
statistics::Vector m_accessModeType
Definition: CacheMemory.hh:241

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