gem5  v21.1.0.2
SeriesRequestGenerator.cc
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2  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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29 
31 
32 #include "base/random.hh"
33 #include "base/trace.hh"
36 #include "debug/DirectedTest.hh"
37 
38 namespace gem5
39 {
40 
43  m_addr_increment_size(p.addr_increment_size),
44  m_percent_writes(p.percent_writes)
45 {
46  m_status = ruby::SeriesRequestGeneratorStatus_Thinking;
47  m_active_node = 0;
48  m_address = 0x0;
49 }
50 
52 {
53 }
54 
55 bool
57 {
58  DPRINTF(DirectedTest, "initiating request\n");
59  assert(m_status == ruby::SeriesRequestGeneratorStatus_Thinking);
60 
62 
63  Request::Flags flags;
64 
65  // For simplicity, requests are assumed to be 1 byte-sized
66  RequestPtr req = std::make_shared<Request>(m_address, 1, flags,
67  requestorId);
68 
69  Packet::Command cmd;
70  bool do_write = (random_mt.random(0, 100) < m_percent_writes);
71  if (do_write) {
72  cmd = MemCmd::WriteReq;
73  } else {
74  cmd = MemCmd::ReadReq;
75  }
76 
77  PacketPtr pkt = new Packet(req, cmd);
78  pkt->allocate();
79 
80  if (port->sendTimingReq(pkt)) {
81  DPRINTF(DirectedTest, "initiating request - successful\n");
82  m_status = ruby::SeriesRequestGeneratorStatus_Request_Pending;
83  return true;
84  } else {
85  // If the packet did not issue, must delete
86  // Note: No need to delete the data, the packet destructor
87  // will delete it
88  delete pkt;
89 
90  DPRINTF(DirectedTest, "failed to initiate request - sequencer not ready\n");
91  return false;
92  }
93 }
94 
95 void
97 {
98  assert(m_active_node == proc);
99  assert(m_address == address);
100  assert(m_status == ruby::SeriesRequestGeneratorStatus_Request_Pending);
101 
102  m_status = ruby::SeriesRequestGeneratorStatus_Thinking;
103  m_active_node++;
104  if (m_active_node == m_num_cpus) {
105  //
106  // Cycle of requests completed, increment cycle completions and restart
107  // at cpu zero
108  //
111  m_active_node = 0;
112  }
113 }
114 
115 } // namespace gem5
gem5::RequestPort::sendTimingReq
bool sendTimingReq(PacketPtr pkt)
Attempt to send a timing request to the responder port by calling its corresponding receive function.
Definition: port.hh:495
gem5::SeriesRequestGenerator::m_status
ruby::SeriesRequestGeneratorStatus m_status
Definition: SeriesRequestGenerator.hh:58
SeriesRequestGenerator.hh
gem5::SeriesRequestGenerator::initiate
bool initiate()
Definition: SeriesRequestGenerator.cc:56
gem5::RubyDirectedTester::incrementCycleCompletions
void incrementCycleCompletions()
Definition: RubyDirectedTester.hh:83
random.hh
gem5::DirectedGenerator
Definition: DirectedGenerator.hh:40
gem5::MemCmd::Command
Command
List of all commands associated with a packet.
Definition: packet.hh:83
gem5::SeriesRequestGenerator::m_percent_writes
uint32_t m_percent_writes
Definition: SeriesRequestGenerator.hh:62
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::Flags< FlagsType >
gem5::DirectedGenerator::m_directed_tester
RubyDirectedTester * m_directed_tester
Definition: DirectedGenerator.hh:56
gem5::SeriesRequestGenerator::m_active_node
uint32_t m_active_node
Definition: SeriesRequestGenerator.hh:60
RubyDirectedTester.hh
gem5::Random::random
std::enable_if_t< std::is_integral< T >::value, T > random()
Use the SFINAE idiom to choose an implementation based on whether the type is integral or floating po...
Definition: random.hh:90
gem5::SeriesRequestGenerator::m_addr_increment_size
uint32_t m_addr_increment_size
Definition: SeriesRequestGenerator.hh:61
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::probing::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:109
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::SeriesRequestGenerator::SeriesRequestGenerator
SeriesRequestGenerator(const Params &p)
Definition: SeriesRequestGenerator.cc:41
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::MemCmd::ReadReq
@ ReadReq
Definition: packet.hh:86
gem5::DirectedGenerator::m_num_cpus
int m_num_cpus
Definition: DirectedGenerator.hh:54
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::RubyDirectedTester::getCpuPort
RequestPort * getCpuPort(int idx)
Definition: RubyDirectedTester.cc:112
gem5::SeriesRequestGenerator::~SeriesRequestGenerator
~SeriesRequestGenerator()
Definition: SeriesRequestGenerator.cc:51
gem5::DirectedGenerator::Params
DirectedGeneratorParams Params
Definition: DirectedGenerator.hh:43
gem5::SeriesRequestGenerator::performCallback
void performCallback(uint32_t proc, Addr address)
Definition: SeriesRequestGenerator.cc:96
gem5::Packet::allocate
void allocate()
Allocate memory for the packet.
Definition: packet.hh:1326
gem5::DirectedGenerator::requestorId
RequestorID requestorId
Definition: DirectedGenerator.hh:55
DirectedGenerator.hh
gem5::MemCmd::WriteReq
@ WriteReq
Definition: packet.hh:89
trace.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::random_mt
Random random_mt
Definition: random.cc:99
gem5::SeriesRequestGenerator::m_address
Addr m_address
Definition: SeriesRequestGenerator.hh:59

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