gem5 v24.0.0.0
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RubyDirectedTester.hh
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1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * Copyright (c) 2009-2010 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#ifndef __CPU_DIRECTEDTEST_RUBYDIRECTEDTESTER_HH__
31#define __CPU_DIRECTEDTEST_RUBYDIRECTEDTESTER_HH__
32
33#include <iostream>
34#include <string>
35#include <vector>
36
37#include "mem/packet.hh"
38#include "mem/port.hh"
42#include "params/RubyDirectedTester.hh"
43#include "sim/clocked_object.hh"
44
45namespace gem5
46{
47
48class DirectedGenerator;
49
51{
52 public:
53 class CpuPort : public RequestPort
54 {
55 private:
57
58 public:
59 CpuPort(const std::string &_name, RubyDirectedTester *_tester,
60 PortID _id)
61 : RequestPort(_name, _id), tester(_tester)
62 {}
63
64 protected:
65 virtual bool recvTimingResp(PacketPtr pkt);
66 virtual void recvReqRetry()
67 { panic("%s does not expect a retry\n", name()); }
68 };
69
70 typedef RubyDirectedTesterParams Params;
73
74 Port &getPort(const std::string &if_name,
75 PortID idx=InvalidPortID) override;
76
77 RequestPort* getCpuPort(int idx);
78
79 void init() override;
80
81 void wakeup();
82
84
85 void printStats(std::ostream& out) const {}
86 void clearStats() {}
87 void printConfig(std::ostream& out) const {}
88
89 void print(std::ostream& out) const;
90
91 protected:
93
94 private:
96
98
99 // Private copy constructor and assignment operator
102
107};
108
109} // namespace gem5
110
111#endif // __CPU_DIRECTEDTEST_RUBYDIRECTEDTESTER_HH__
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
const std::string _name
Definition named.hh:41
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition packet.hh:295
Ports are used to interface objects to each other.
Definition port.hh:62
const std::string name() const
Return port name (for DPRINTF).
Definition port.hh:111
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition port.hh:136
CpuPort(const std::string &_name, RubyDirectedTester *_tester, PortID _id)
virtual bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
virtual void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
RubyDirectedTester & operator=(const RubyDirectedTester &obj)
void printConfig(std::ostream &out) const
RubyDirectedTester(const Params &p)
RequestPort * getCpuPort(int idx)
EventFunctionWrapper directedStartEvent
std::vector< RequestPort * > ports
DirectedGenerator * generator
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
RubyDirectedTesterParams Params
void hitCallback(ruby::NodeID proc, Addr addr)
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
void printStats(std::ostream &out) const
void print(std::ostream &out) const
RubyDirectedTester(const RubyDirectedTester &obj)
STL vector class.
Definition stl.hh:37
ClockedObject declaration and implementation.
#define panic(...)
This implements a cprintf based panic() function.
Definition logging.hh:188
Port Object Declaration.
Bitfield< 0 > p
Bitfield< 3 > addr
Definition types.hh:84
unsigned int NodeID
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
const PortID InvalidPortID
Definition types.hh:246
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition types.hh:245
Declaration of the Packet class.

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