gem5  v21.1.0.2
RubyDirectedTester.cc
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41 
43 
44 #include "base/trace.hh"
46 #include "debug/DirectedTest.hh"
47 #include "sim/sim_exit.hh"
48 
49 namespace gem5
50 {
51 
53  : ClockedObject(p),
54  directedStartEvent([this]{ wakeup(); }, "Directed tick",
55  false, Event::CPU_Tick_Pri),
56  m_requests_to_complete(p.requests_to_complete),
57  generator(p.generator)
58 {
59  m_requests_completed = 0;
60 
61  // create the ports
62  for (int i = 0; i < p.port_cpuPort_connection_count; ++i) {
63  ports.push_back(new CpuPort(csprintf("%s-port%d", name(), i),
64  this, i));
65  }
66 
67  // add the check start event to the event queue
68  schedule(directedStartEvent, 1);
69 }
70 
72 {
73  for (int i = 0; i < ports.size(); i++)
74  delete ports[i];
75 }
76 
77 void
79 {
80  assert(ports.size() > 0);
82 }
83 
84 Port &
85 RubyDirectedTester::getPort(const std::string &if_name, PortID idx)
86 {
87  if (if_name != "cpuPort") {
88  // pass it along to our super class
89  return ClockedObject::getPort(if_name, idx);
90  } else {
91  if (idx >= static_cast<int>(ports.size())) {
92  panic("RubyDirectedTester::getPort: unknown index %d\n", idx);
93  }
94 
95  return *ports[idx];
96  }
97 }
98 
99 bool
101 {
102  tester->hitCallback(id, pkt->getAddr());
103 
104  //
105  // Now that the tester has completed, delete the packet, then return
106  //
107  delete pkt;
108  return true;
109 }
110 
113 {
114  assert(idx >= 0 && idx < ports.size());
115 
116  return ports[idx];
117 }
118 
119 void
121 {
122  DPRINTF(DirectedTest,
123  "completed request for proc: %d addr: 0x%x\n",
124  proc,
125  addr);
126 
129 }
130 
131 void
133 {
135  if (!generator->initiate()) {
137  }
138  } else {
139  exitSimLoop("Ruby DirectedTester completed");
140  }
141 }
142 
143 } // namespace gem5
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::SimObject::getPort
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
Definition: sim_object.cc:126
gem5::RubyDirectedTester::wakeup
void wakeup()
Definition: RubyDirectedTester.cc:132
gem5::RubyDirectedTester::hitCallback
void hitCallback(ruby::NodeID proc, Addr addr)
Definition: RubyDirectedTester.cc:120
gem5::RubyDirectedTester::directedStartEvent
EventFunctionWrapper directedStartEvent
Definition: RubyDirectedTester.hh:92
gem5::DirectedGenerator::performCallback
virtual void performCallback(uint32_t proc, Addr address)=0
gem5::EventManager::schedule
void schedule(Event &event, Tick when)
Definition: eventq.hh:1019
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::RubyDirectedTester::m_requests_completed
uint64_t m_requests_completed
Definition: RubyDirectedTester.hh:103
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::RubyDirectedTester::~RubyDirectedTester
~RubyDirectedTester()
Definition: RubyDirectedTester.cc:71
sim_exit.hh
gem5::exitSimLoop
void exitSimLoop(const std::string &message, int exit_code, Tick when, Tick repeat, bool serialize)
Schedule an event to exit the simulation loop (returning to Python) at the end of the current cycle (...
Definition: sim_events.cc:88
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::RubyDirectedTester::ports
std::vector< RequestPort * > ports
Definition: RubyDirectedTester.hh:104
RubyDirectedTester.hh
gem5::RubyDirectedTester::RubyDirectedTester
RubyDirectedTester(const Params &p)
Definition: RubyDirectedTester.cc:52
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::DirectedGenerator::initiate
virtual bool initiate()=0
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::RubyDirectedTester::generator
DirectedGenerator * generator
Definition: RubyDirectedTester.hh:106
gem5::RubyDirectedTester::Params
RubyDirectedTesterParams Params
Definition: RubyDirectedTester.hh:70
gem5::RubyDirectedTester::m_requests_to_complete
uint64_t m_requests_to_complete
Definition: RubyDirectedTester.hh:105
gem5::DirectedGenerator::setDirectedTester
void setDirectedTester(RubyDirectedTester *directed_tester)
Definition: DirectedGenerator.cc:46
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
name
const std::string & name()
Definition: trace.cc:49
gem5::RubyDirectedTester::getCpuPort
RequestPort * getCpuPort(int idx)
Definition: RubyDirectedTester.cc:112
gem5::RubyDirectedTester::CpuPort::tester
RubyDirectedTester * tester
Definition: RubyDirectedTester.hh:56
gem5::ClockedObject
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Definition: clocked_object.hh:234
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
DirectedGenerator.hh
gem5::ruby::NodeID
unsigned int NodeID
Definition: TypeDefines.hh:40
gem5::RubyDirectedTester::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: RubyDirectedTester.cc:78
trace.hh
gem5::RubyDirectedTester::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: RubyDirectedTester.cc:85
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
gem5::EventBase::CPU_Tick_Pri
static const Priority CPU_Tick_Pri
CPU ticks must come after other associated CPU events (such as writebacks).
Definition: eventq.hh:204
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::RubyDirectedTester::CpuPort::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
Definition: RubyDirectedTester.cc:100

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