gem5 v24.0.0.0
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RubyDirectedTester.cc
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1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
15 * Copyright (c) 2009-2010 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
43
44#include "base/trace.hh"
46#include "debug/DirectedTest.hh"
47#include "sim/sim_exit.hh"
48
49namespace gem5
50{
51
54 directedStartEvent([this]{ wakeup(); }, "Directed tick",
55 false, Event::CPU_Tick_Pri),
56 m_requests_to_complete(p.requests_to_complete),
57 generator(p.generator)
58{
59 m_requests_completed = 0;
60
61 // create the ports
62 for (int i = 0; i < p.port_cpuPort_connection_count; ++i) {
63 ports.push_back(new CpuPort(csprintf("%s-port%d", name(), i),
64 this, i));
65 }
66
67 // add the check start event to the event queue
68 schedule(directedStartEvent, 1);
69}
70
72{
73 for (int i = 0; i < ports.size(); i++)
74 delete ports[i];
75}
76
77void
79{
80 assert(ports.size() > 0);
82}
83
84Port &
85RubyDirectedTester::getPort(const std::string &if_name, PortID idx)
86{
87 if (if_name != "cpuPort") {
88 // pass it along to our super class
89 return ClockedObject::getPort(if_name, idx);
90 } else {
91 if (idx >= static_cast<int>(ports.size())) {
92 panic("RubyDirectedTester::getPort: unknown index %d\n", idx);
93 }
94
95 return *ports[idx];
96 }
97}
98
99bool
101{
102 tester->hitCallback(id, pkt->getAddr());
103
104 //
105 // Now that the tester has completed, delete the packet, then return
106 //
107 delete pkt;
108 return true;
109}
110
113{
114 assert(idx >= 0 && idx < ports.size());
115
116 return ports[idx];
117}
118
119void
121{
122 DPRINTF(DirectedTest,
123 "completed request for proc: %d addr: 0x%x\n",
124 proc,
125 addr);
126
129}
130
131void
133{
135 if (!generator->initiate()) {
137 }
138 } else {
139 exitSimLoop("Ruby DirectedTester completed");
140 }
141}
142
143} // namespace gem5
#define DPRINTF(x,...)
Definition trace.hh:210
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
virtual bool initiate()=0
void setDirectedTester(RubyDirectedTester *directed_tester)
virtual void performCallback(uint32_t proc, Addr address)=0
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition packet.hh:295
Addr getAddr() const
Definition packet.hh:807
Ports are used to interface objects to each other.
Definition port.hh:62
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition port.hh:136
virtual bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
RubyDirectedTester(const Params &p)
RequestPort * getCpuPort(int idx)
EventFunctionWrapper directedStartEvent
std::vector< RequestPort * > ports
DirectedGenerator * generator
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
RubyDirectedTesterParams Params
void hitCallback(ruby::NodeID proc, Addr addr)
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
void schedule(Event &event, Tick when)
Definition eventq.hh:1012
static const Priority CPU_Tick_Pri
CPU ticks must come after other associated CPU events (such as writebacks).
Definition eventq.hh:207
#define panic(...)
This implements a cprintf based panic() function.
Definition logging.hh:188
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
Bitfield< 7 > i
Definition misc_types.hh:67
Bitfield< 0 > p
Bitfield< 3 > addr
Definition types.hh:84
unsigned int NodeID
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
Tick curTick()
The universal simulation clock.
Definition cur_tick.hh:46
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition types.hh:245
void exitSimLoop(const std::string &message, int exit_code, Tick when, Tick repeat, bool serialize)
Schedule an event to exit the simulation loop (returning to Python) at the end of the current cycle (...
Definition sim_events.cc:88
std::string csprintf(const char *format, const Args &...args)
Definition cprintf.hh:161
const std::string & name()
Definition trace.cc:48

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