gem5 v24.0.0.0
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WeightBased.cc
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1/*
2 * Copyright (c) 2021 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 */
40
42
43#include <algorithm>
44
45#include "base/random.hh"
47
48namespace gem5
49{
50
51namespace ruby
52{
53
58
59void
61 const std::vector<MessageBuffer*>& m_out_buffer,
62 const NetDest& routing_table_entry,
63 const PortDirection &direction,
64 int link_weight)
65{
66 gem5_assert(link_id == m_links.size());
67 m_links.emplace_back(new LinkInfo{link_id,
68 routing_table_entry,
69 m_out_buffer,
70 0, link_weight});
71 sortLinks();
72}
73
74void
76 int vnet,
77 bool deterministic,
78 std::vector<RouteInfo> &out_links)
79{
80 // Makes sure ordering was reset adaptive option was set
81 if (params().adaptive_routing) {
82 if (deterministic) {
83 // Don't adaptively route
84 // Makes sure ordering is reset
85 for (auto &link : m_links)
86 link->m_order = 0;
87 } else {
88 // Find how clogged each link is
89 for (auto &link : m_links) {
90 int out_queue_length = 0;
91 Tick current_time = m_parent_switch->clockEdge();
92 for (auto buffer : link->m_out_buffers) {
93 out_queue_length += buffer->getSize(current_time);
94 }
95 // improve load distribution by randomizing order of links
96 // with the same queue length
97 link->m_order =
98 (out_queue_length << 8) | random_mt.random(0, 0xff);
99 }
100 }
101 sortLinks();
102 }
103
104 findRoute(msg, out_links);
105}
106
107void
109 std::vector<RouteInfo> &out_links) const
110{
111 NetDest msg_dsts = msg.getDestination();
112 assert(out_links.size() == 0);
113 for (auto &link : m_links) {
114 const NetDest &dst = link->m_routing_entry;
115 if (msg_dsts.intersectionIsNotEmpty(dst)) {
116 // Need to remember which destinations need this message in
117 // another vector. This Set is the intersection of the
118 // routing_table entry and the current destination set.
119 out_links.emplace_back(msg_dsts.AND(dst), link->m_link_id);
120
121 // Next, we update the msg_destination not to include
122 // those nodes that were already handled by this link
123 msg_dsts.removeNetDest(dst);
124 }
125 }
126
127 gem5_assert(msg_dsts.count() == 0);
128}
129
130} // namespace ruby
131} // namespace gem5
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
SimObjectParams Params
virtual const NetDest & getDestination() const
Definition Message.hh:114
NetDest AND(const NetDest &andNetDest) const
Definition NetDest.cc:210
void removeNetDest(const NetDest &netDest)
Definition NetDest.cc:76
int count() const
Definition NetDest.cc:128
bool intersectionIsNotEmpty(const NetDest &other_netDest) const
Definition NetDest.cc:222
WeightBased(const Params &p)
void findRoute(const Message &msg, std::vector< RouteInfo > &out_links) const
std::vector< std::unique_ptr< LinkInfo > > m_links
void route(const Message &msg, int vnet, bool deterministic, std::vector< RouteInfo > &out_links) override
void addOutPort(LinkID link_id, const std::vector< MessageBuffer * > &m_out_buffer, const NetDest &routing_table_entry, const PortDirection &direction, int link_weight) override
STL vector class.
Definition stl.hh:37
Random random_mt
Definition random.cc:99
std::enable_if_t< std::is_integral_v< T >, T > random()
Use the SFINAE idiom to choose an implementation based on whether the type is integral or floating po...
Definition random.hh:90
#define gem5_assert(cond,...)
The assert macro will function like a normal assert, but will use panic instead of straight abort().
Definition logging.hh:317
const Params & params() const
Bitfield< 0 > p
unsigned int LinkID
std::string PortDirection
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
uint64_t Tick
Tick count type.
Definition types.hh:58

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