gem5 v24.0.0.0
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amdgpu_nbio.cc
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1/*
2 * Copyright (c) 2023 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
33
34#include "debug/AMDGPUDevice.hh"
36#include "mem/packet_access.hh"
37
38namespace gem5
39{
40
42{
43 // All read-before-write MMIOs go here
45}
46
47void
49{
50 gpuDevice = gpu_device;
51}
52
53void
55{
56 // For Vega10 we rely on the golden values in an MMIO trace. Return
57 // immediately as to not clobber those values.
58 if (gpuDevice->getGfxVersion() == GfxVersion::gfx900) {
60 return;
61 }
62 }
63
64 switch (offset) {
65 // PCIE_DATA, PCIE_DATA2, PCIE_INDEX, and PCIE_INDEX2 handle "indirect
66 // "register reads/writes from the driver. This provides a way to read
67 // any register by providing a 32-bit address to one of the two INDEX
68 // registers and then reading the corresponding DATA register. See:
69 // https://github.com/ROCm/ROCK-Kernel-Driver/blob/roc-6.0.x/drivers/
70 // gpu/drm/amd/amdgpu/amdgpu_device.c#L459
72 {
73 uint32_t value = gpuDevice->getRegVal(pcie_index_reg);
74 DPRINTF(AMDGPUDevice, "Read PCIe index %lx data %x\n",
75 pcie_index_reg, value);
76 pkt->setLE<uint32_t>(value);
77 }
78 break;
80 {
81 uint32_t value = gpuDevice->getRegVal(pcie_index2_reg);
82 DPRINTF(AMDGPUDevice, "Read PCIe index2 %lx data2 %x\n",
83 pcie_index2_reg, value);
84 pkt->setLE<uint32_t>(value);
85 }
86 break;
88 pkt->setLE<uint32_t>(pcie_index_reg);
89 break;
91 pkt->setLE<uint32_t>(pcie_index2_reg);
92 break;
93 case AMDGPU_MM_DATA:
94 pkt->setLE<uint32_t>(gpuDevice->getRegVal(mm_index_reg));
95 break;
101 pkt->setLE<uint32_t>(0x10001);
102 break;
108 pkt->setLE<uint32_t>(0x1);
109 break;
110 // PSP responds with bit 31 set when ready
112 pkt->setLE<uint32_t>(0x80000000);
113 break;
115 pkt->setLE<uint32_t>(0x1);
116 break;
117 default:
118 if (triggered_reads.count(offset)) {
119 DPRINTF(AMDGPUDevice, "Found triggered read for %#x\n", offset);
120 pkt->setLE<uint32_t>(triggered_reads[offset]);
121 } else if (regs.count(offset)) {
122 DPRINTF(AMDGPUDevice, "Returning value of unknown MMIO offset "
123 "%x: %x\n", offset, regs[offset]);
124 pkt->setLE<uint32_t>(regs[offset]);
125 } else {
126 DPRINTF(AMDGPUDevice, "NBIO Unknown MMIO %#x (%#x)\n", offset,
127 pkt->getAddr());
128 }
129 break;
130 }
131}
132
133void
135{
136 if (offset == AMDGPU_MM_INDEX) {
137 assert(pkt->getSize() == 4);
139 pkt->getLE<uint32_t>());
140 } else if (offset == AMDGPU_MM_INDEX_HI) {
141 assert(pkt->getSize() == 4);
143 pkt->getLE<uint32_t>());
144 } else if (offset == AMDGPU_MM_DATA) {
145 DPRINTF(AMDGPUDevice, "MM write to reg %#lx data %#lx\n",
146 mm_index_reg, pkt->getLE<uint32_t>());
147 gpuDevice->setRegVal(AMDGPU_MM_DATA, pkt->getLE<uint32_t>());
148 // PCIE_DATA, PCIE_DATA2, PCIE_INDEX, and PCIE_INDEX2 handle "indirect
149 // "register reads/writes from the driver. This provides a way to read
150 // any register by providing a 32-bit address to one of the two INDEX
151 // registers and then reading the corresponding DATA register. See:
152 // https://github.com/ROCm/ROCK-Kernel-Driver/blob/roc-6.0.x/drivers/
153 // gpu/drm/amd/amdgpu/amdgpu_device.c#L459
154 } else if (offset == AMDGPU_PCIE_INDEX) {
155 assert(pkt->getSize() == 4);
156 pcie_index_reg = pkt->getLE<uint32_t>();
157 } else if (offset == AMDGPU_PCIE_DATA) {
158 assert(pkt->getSize() == 4);
159 gpuDevice->setRegVal(pcie_index_reg, pkt->getLE<uint32_t>());
160 } else if (offset == AMDGPU_PCIE_INDEX2) {
161 assert(pkt->getSize() == 4);
162 pcie_index2_reg = pkt->getLE<uint32_t>();
163 } else if (offset == AMDGPU_PCIE_DATA2) {
164 assert(pkt->getSize() == 4);
165 gpuDevice->setRegVal(pcie_index2_reg, pkt->getLE<uint32_t>());
166 } else if (offset == AMDGPU_MP0_SMN_C2PMSG_35) {
167 // See psp_v3_1_bootloader_load_sos in amdgpu driver code.
168 if (pkt->getLE<uint32_t>() == 0x10000) {
170 }
171 } else if (offset == AMDGPU_MP0_SMN_C2PMSG_64) {
173 0x80000000 + pkt->getLE<uint32_t>();
174 } else if (offset == AMDGPU_MP0_SMN_C2PMSG_69) {
175 // PSP ring low addr
176 psp_ring = insertBits(psp_ring, 31, 0, pkt->getLE<uint32_t>());
179 } else if (offset == AMDGPU_MP0_SMN_C2PMSG_70) {
180 // PSP ring high addr
181 psp_ring = insertBits(psp_ring, 63, 32, pkt->getLE<uint32_t>());
184 } else if (offset == AMDGPU_MP0_SMN_C2PMSG_71) {
185 // PSP ring size
186 psp_ring_size = pkt->getLE<uint32_t>();
187 } else {
188 // Fallback to a map of register values. This was previously in the
189 // AMDGPUDevice, however that short-circuited some reads from other
190 // IP blocks. Since this is an end point IP block it is safer to use
191 // here.
192 regs[offset] = pkt->getLE<uint32_t>();
193 DPRINTF(AMDGPUDevice, "Writing value of unknown MMIO offset "
194 "%x: %x\n", offset, regs[offset]);
195 }
196}
197
198bool
200{
201 if (offset == psp_ring_dev_addr) {
203 pkt->setUintX(psp_ring_value, ByteOrder::little);
204
205 return true;
206 }
207
208 return false;
209}
210
211void
213{
215 DPRINTF(AMDGPUDevice, "Saw psp_ring_listen_addr with size %ld value "
216 "%ld\n", pkt->getSize(), pkt->getUintX(ByteOrder::little));
217
218 /*
219 * In ROCm versions 4.x this packet is a 4 byte value. In ROCm 5.x
220 * the packet is 8 bytes and mapped as a system address which needs
221 * to be subtracted out to get the framebuffer address.
222 */
223 if (pkt->getSize() == 4) {
224 psp_ring_dev_addr = pkt->getLE<uint32_t>();
225 } else if (pkt->getSize() == 8) {
226 psp_ring_dev_addr = pkt->getUintX(ByteOrder::little)
228 } else {
229 panic("Invalid write size to psp_ring_listen_addr\n");
230 }
231
232 DPRINTF(AMDGPUDevice, "Setting PSP ring device address to %#lx\n",
234 }
235}
236
237} // namespace gem5
#define AMDGPU_PCIE_INDEX
#define AMDGPU_PCIE_DATA2
#define AMDGPU_MM_INDEX_HI
#define AMDGPU_PCIE_INDEX2
#define VEGA10_INV_ENG17_ACK2
#define VEGA10_INV_ENG17_ACK1
#define MI100_INV_ENG17_SEM2
#define AMDGPU_MP0_SMN_C2PMSG_81
#define AMDGPU_MP0_SMN_C2PMSG_71
#define AMDGPU_MP0_SMN_C2PMSG_64
#define MI100_INV_ENG17_ACK2
#define MI200_INV_ENG17_SEM2
#define AMDGPU_MP0_SMN_C2PMSG_35
#define AMDGPU_MM_INDEX
MMIO offsets for NBIO.
#define VEGA10_INV_ENG17_SEM1
#define MI100_INV_ENG17_ACK3
#define MI100_INV_ENG17_SEM3
#define MI200_INV_ENG17_ACK2
#define AMDGPU_MP0_SMN_C2PMSG_69
#define AMDGPU_MM_DATA
#define VEGA10_INV_ENG17_SEM2
#define AMDGPU_MP1_SMN_C2PMSG_90
#define AMDGPU_MP0_SMN_C2PMSG_70
#define AMDGPU_PCIE_DATA
#define DPRINTF(x,...)
Definition trace.hh:210
Device model for an AMD GPU.
GfxVersion getGfxVersion() const
void setRegVal(uint64_t addr, uint32_t value)
uint32_t getRegVal(uint64_t addr)
Register value getter/setter.
void readMMIO(PacketPtr pkt, Addr offset)
uint32_t pcie_index2_reg
std::unordered_map< uint32_t, uint32_t > triggered_reads
void writeMMIO(PacketPtr pkt, Addr offset)
bool readFrame(PacketPtr pkt, Addr offset)
uint64_t mm_index_reg
AMDGPUDevice * gpuDevice
uint32_t pcie_index_reg
void writeFrame(PacketPtr pkt, Addr offset)
void setGPUDevice(AMDGPUDevice *gpu_device)
Addr getSysAddrRangeLow()
Definition amdgpu_vm.hh:250
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition packet.hh:295
Addr getAddr() const
Definition packet.hh:807
void setUintX(uint64_t w, ByteOrder endian)
Set the value in the word w after truncating it to the length of the packet and then byteswapping it ...
Definition packet.cc:361
void setLE(T v)
Set the value in the data pointer to v as little endian.
unsigned getSize() const
Definition packet.hh:817
uint64_t getUintX(ByteOrder endian) const
Get the data in the packet byte swapped from the specified endianness and zero-extended to 64 bits.
Definition packet.cc:352
T getLE() const
Get the data in the packet byte swapped from little endian to host endian.
constexpr T insertBits(T val, unsigned first, unsigned last, B bit_val)
Returns val with bits first to last set to the LSBs of bit_val.
Definition bitfield.hh:185
#define panic(...)
This implements a cprintf based panic() function.
Definition logging.hh:188
Bitfield< 23, 0 > offset
Definition types.hh:144
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147

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