gem5  v21.1.0.2
cpu.hh
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27 
28 #ifndef __ARCH_ARM_FASTMODEL_IRIS_CPU_HH__
29 #define __ARCH_ARM_FASTMODEL_IRIS_CPU_HH__
30 
31 #include "cpu/base.hh"
32 #include "iris/detail/IrisInterface.h"
33 #include "params/IrisBaseCPU.hh"
37 
38 namespace gem5
39 {
40 
41 namespace Iris
42 {
43 
44 class ThreadContext;
45 
46 // The base interface of the EVS used by gem5 BaseCPU below.
48 {
49  public:
50  virtual void sendFunc(PacketPtr pkt) = 0;
51  virtual void setClkPeriod(Tick clk_period) = 0;
52  virtual void setSysCounterFrq(uint64_t sys_counter_frq) = 0;
53  virtual void setCluster(SimObject *cluster) = 0;
54 };
55 
56 // This CPU class adds some mechanisms which help attach the gem5 and fast
57 // model CPUs to each other. It acts as a base class for the gem5 CPU, and
58 // holds a pointer to the EVS. It also has some methods for setting up some
59 // attributes in the fast model CPU to control its clock rate.
60 class BaseCPU : public gem5::BaseCPU
61 {
62  public:
63  BaseCPU(const BaseCPUParams &params, sc_core::sc_module *_evs);
64  virtual ~BaseCPU();
65 
66  Port &
67  getDataPort() override
68  {
69  panic("%s not implemented.", __FUNCTION__);
70  }
71 
72  Port &
73  getInstPort() override
74  {
75  panic("%s not implemented.", __FUNCTION__);
76  }
77 
78  void
79  wakeup(ThreadID tid) override
80  {
81  auto *tc = threadContexts.at(tid);
82  if (tc->status() == gem5::ThreadContext::Suspended)
83  tc->activate();
84  }
85 
86  Counter totalInsts() const override;
87  Counter totalOps() const override { return totalInsts(); }
88 
89  protected:
91  // Hold casted pointer to *evs.
93 
94  protected:
95  friend ThreadContext;
96 
97  void
98  clockPeriodUpdated() override
99  {
101  }
102 
103  void init() override;
104 
105  void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
106 };
107 
108 // This class specializes the one above and sets up ThreadContexts based on
109 // its template parameters. These ThreadContexts provide the standard gem5
110 // interface and translate those accesses to use the Iris API to access that
111 // state in the target context.
112 template <class TC>
113 class CPU : public Iris::BaseCPU
114 {
115  public:
116  CPU(const IrisBaseCPUParams &params,
117  iris::IrisConnectionInterface *iris_if) :
119  {
120  const std::string parent_path = evs->name();
121  System *sys = params.system;
122 
123  int thread_id = 0;
124  for (const std::string &sub_path: params.thread_paths) {
125  std::string path = parent_path + "." + sub_path;
126  auto id = thread_id++;
127  auto *tc = new TC(this, id, sys, params.mmu,
128  params.isa[id], iris_if, path);
129  threadContexts.push_back(tc);
130  }
131  }
132 };
133 
134 } // namespace Iris
135 } // namespace gem5
136 
137 #endif // __ARCH_ARM_FASTMODEL_IRIS_CPU_HH__
gem5::Iris::BaseCPU::getInstPort
Port & getInstPort() override
Purely virtual method that returns a reference to the instruction port.
Definition: cpu.hh:73
gem5::Iris::BaseCPU::BaseCPU
BaseCPU(const BaseCPUParams &params, sc_core::sc_module *_evs)
Definition: cpu.cc:40
gem5::Iris::BaseCpuEvs::setClkPeriod
virtual void setClkPeriod(Tick clk_period)=0
sc_core::sc_module
Definition: sc_module.hh:98
gem5::Serializable::path
static std::stack< std::string > path
Definition: serialize.hh:315
gem5::Iris::BaseCPU
Definition: cpu.hh:60
gem5::Iris::BaseCpuEvs
Definition: cpu.hh:47
gem5::Iris::BaseCPU::~BaseCPU
virtual ~BaseCPU()
Definition: cpu.cc:53
gem5::Iris::BaseCPU::ThreadContext
friend ThreadContext
Definition: cpu.hh:95
gem5::Iris::BaseCPU::evs_base_cpu
Iris::BaseCpuEvs * evs_base_cpu
Definition: cpu.hh:92
gem5::Iris::BaseCPU::evs
sc_core::sc_module * evs
Definition: cpu.hh:90
gem5::Iris::CPU::CPU
CPU(const IrisBaseCPUParams &params, iris::IrisConnectionInterface *iris_if)
Definition: cpu.hh:116
gem5::Iris::BaseCPU::serializeThread
void serializeThread(CheckpointOut &cp, ThreadID tid) const override
Serialize a single thread.
Definition: cpu.cc:78
gem5::Iris::BaseCpuEvs::setSysCounterFrq
virtual void setSysCounterFrq(uint64_t sys_counter_frq)=0
sc_event.hh
gem5::Iris::BaseCPU::wakeup
void wakeup(ThreadID tid) override
Definition: cpu.hh:79
gem5::System
Definition: system.hh:77
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::ThreadContext::Suspended
@ Suspended
Temporarily inactive.
Definition: thread_context.hh:112
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::Iris::BaseCpuEvs::sendFunc
virtual void sendFunc(PacketPtr pkt)=0
gem5::Iris::BaseCPU::totalOps
Counter totalOps() const override
Definition: cpu.hh:87
gem5::BaseCPU
Definition: base.hh:107
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
sc_module.hh
gem5::Iris::BaseCPU::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: cpu.cc:70
gem5::Iris::BaseCpuEvs::setCluster
virtual void setCluster(SimObject *cluster)=0
gem5::BaseCPU::threadContexts
std::vector< ThreadContext * > threadContexts
Definition: base.hh:262
base.hh
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
sc_core::sc_object::name
const char * name() const
Definition: sc_object.cc:44
gem5::statistics::Counter
double Counter
All counters are of 64-bit values.
Definition: types.hh:47
gem5::Iris::CPU
Definition: cpu.hh:113
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::Iris::BaseCPU::totalInsts
Counter totalInsts() const override
Definition: cpu.cc:61
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
sc_attr.hh
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::Clocked::clockPeriod
Tick clockPeriod() const
Definition: clocked_object.hh:217
gem5::Iris::BaseCPU::clockPeriodUpdated
void clockPeriodUpdated() override
A hook subclasses can implement so they can do any extra work that's needed when the clock rate is ch...
Definition: cpu.hh:98
gem5::Iris::BaseCPU::getDataPort
Port & getDataPort() override
Purely virtual method that returns a reference to the data port.
Definition: cpu.hh:67

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