gem5  v22.0.0.2
cpu.hh
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27 
28 #ifndef __ARCH_ARM_FASTMODEL_IRIS_CPU_HH__
29 #define __ARCH_ARM_FASTMODEL_IRIS_CPU_HH__
30 
31 #include "cpu/base.hh"
32 #include "iris/detail/IrisInterface.h"
33 #include "params/IrisBaseCPU.hh"
37 
38 namespace gem5
39 {
40 
41 namespace Iris
42 {
43 
44 class ThreadContext;
45 
46 // The base interface of the EVS used by gem5 BaseCPU below.
48 {
49  public:
50  virtual void sendFunc(PacketPtr pkt) = 0;
51  virtual void setClkPeriod(Tick clk_period) = 0;
52  virtual void setSysCounterFrq(uint64_t sys_counter_frq) = 0;
53  virtual void setCluster(SimObject *cluster) = 0;
54  virtual void setResetAddr(int core, Addr addr, bool secure) = 0;
55 };
56 
57 // This CPU class adds some mechanisms which help attach the gem5 and fast
58 // model CPUs to each other. It acts as a base class for the gem5 CPU, and
59 // holds a pointer to the EVS. It also has some methods for setting up some
60 // attributes in the fast model CPU to control its clock rate.
61 class BaseCPU : public gem5::BaseCPU
62 {
63  public:
64  BaseCPU(const BaseCPUParams &params, sc_core::sc_module *_evs);
65  virtual ~BaseCPU();
66 
67  Port &
68  getDataPort() override
69  {
70  panic("%s not implemented.", __FUNCTION__);
71  }
72 
73  Port &
74  getInstPort() override
75  {
76  panic("%s not implemented.", __FUNCTION__);
77  }
78 
79  void
80  wakeup(ThreadID tid) override
81  {
82  auto *tc = threadContexts.at(tid);
83  if (tc->status() == gem5::ThreadContext::Suspended)
84  tc->activate();
85  }
86 
87  Counter totalInsts() const override;
88  Counter totalOps() const override { return totalInsts(); }
89 
90  virtual void
91  setResetAddr(Addr addr, bool secure = false)
92  {
93  panic("%s not implemented.", __FUNCTION__);
94  }
95 
96  protected:
98  // Hold casted pointer to *evs.
100 
101  protected:
103 
104  void
106  {
107  evs_base_cpu->setClkPeriod(clockPeriod());
108  }
109 
110  void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
111 };
112 
113 // This class specializes the one above and sets up ThreadContexts based on
114 // its template parameters. These ThreadContexts provide the standard gem5
115 // interface and translate those accesses to use the Iris API to access that
116 // state in the target context.
117 template <class TC>
118 class CPU : public Iris::BaseCPU
119 {
120  public:
121  CPU(const IrisBaseCPUParams &params,
122  iris::IrisConnectionInterface *iris_if) :
123  BaseCPU(params, params.evs)
124  {
125  const std::string parent_path = evs->name();
126  System *sys = params.system;
127 
128  int thread_id = 0;
129  for (const std::string &sub_path: params.thread_paths) {
130  std::string path = parent_path + "." + sub_path;
131  auto id = thread_id++;
132  auto *tc = new TC(this, id, sys, params.mmu,
133  params.isa[id], iris_if, path);
134  threadContexts.push_back(tc);
135  }
136  }
137 };
138 
139 } // namespace Iris
140 } // namespace gem5
141 
142 #endif // __ARCH_ARM_FASTMODEL_IRIS_CPU_HH__
gem5::Iris::BaseCPU::~BaseCPU
virtual ~BaseCPU()
Definition: cpu.cc:53
gem5::Iris::BaseCPU::getInstPort
Port & getInstPort() override
Definition: cpu.hh:74
gem5::Iris::BaseCpuEvs::setClkPeriod
virtual void setClkPeriod(Tick clk_period)=0
gem5::Iris::BaseCPU::setResetAddr
virtual void setResetAddr(Addr addr, bool secure=false)
Definition: cpu.hh:91
gem5::Iris::BaseCpuEvs::setResetAddr
virtual void setResetAddr(int core, Addr addr, bool secure)=0
sc_core::sc_module
Definition: sc_module.hh:101
gem5::Iris::BaseCPU
Definition: cpu.hh:61
gem5::Iris::BaseCpuEvs
Definition: cpu.hh:47
gem5::Iris::BaseCPU::ThreadContext
friend ThreadContext
Definition: cpu.hh:102
gem5::Iris::BaseCPU::evs_base_cpu
Iris::BaseCpuEvs * evs_base_cpu
Definition: cpu.hh:99
gem5::Iris::BaseCPU::evs
sc_core::sc_module * evs
Definition: cpu.hh:97
gem5::Iris::CPU::CPU
CPU(const IrisBaseCPUParams &params, iris::IrisConnectionInterface *iris_if)
Definition: cpu.hh:121
gem5::Iris::BaseCpuEvs::setSysCounterFrq
virtual void setSysCounterFrq(uint64_t sys_counter_frq)=0
gem5::Iris::BaseCPU::BaseCPU
BaseCPU(const BaseCPUParams &params, sc_core::sc_module *_evs)
Definition: cpu.cc:40
sc_event.hh
gem5::Iris::BaseCPU::wakeup
void wakeup(ThreadID tid) override
Definition: cpu.hh:80
gem5::System
Definition: system.hh:75
gem5::ThreadContext::Suspended
@ Suspended
Temporarily inactive.
Definition: thread_context.hh:113
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::Iris::BaseCpuEvs::sendFunc
virtual void sendFunc(PacketPtr pkt)=0
gem5::Iris::BaseCPU::totalOps
Counter totalOps() const override
Definition: cpu.hh:88
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
sc_module.hh
gem5::Iris::BaseCpuEvs::setCluster
virtual void setCluster(SimObject *cluster)=0
base.hh
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
sc_core::sc_object::name
const char * name() const
Definition: sc_object.cc:44
gem5::statistics::Counter
double Counter
All counters are of 64-bit values.
Definition: types.hh:47
gem5::Iris::CPU
Definition: cpu.hh:118
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::Iris::BaseCPU::totalInsts
Counter totalInsts() const override
Definition: cpu.cc:61
gem5::Iris::BaseCPU::serializeThread
void serializeThread(CheckpointOut &cp, ThreadID tid) const override
Definition: cpu.cc:70
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:235
sc_attr.hh
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::Iris::BaseCPU::clockPeriodUpdated
void clockPeriodUpdated() override
Definition: cpu.hh:105
gem5::Iris::BaseCPU::getDataPort
Port & getDataPort() override
Definition: cpu.hh:68

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