gem5  v22.0.0.2
system.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2010, 2012-2013, 2015,2017-2021 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Copyright (c) 2002-2006 The Regents of The University of Michigan
15  * All rights reserved.
16  *
17  * Redistribution and use in source and binary forms, with or without
18  * modification, are permitted provided that the following conditions are
19  * met: redistributions of source code must retain the above copyright
20  * notice, this list of conditions and the following disclaimer;
21  * redistributions in binary form must reproduce the above copyright
22  * notice, this list of conditions and the following disclaimer in the
23  * documentation and/or other materials provided with the distribution;
24  * neither the name of the copyright holders nor the names of its
25  * contributors may be used to endorse or promote products derived from
26  * this software without specific prior written permission.
27  *
28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39  */
40 
41 #include "arch/arm/system.hh"
42 
43 #include <iostream>
44 
45 #include "arch/arm/fs_workload.hh"
46 #include "arch/arm/semihosting.hh"
48 #include "base/loader/symtab.hh"
49 #include "cpu/thread_context.hh"
51 #include "dev/arm/gic_v2.hh"
52 #include "mem/physical.hh"
53 #include "params/ArmRelease.hh"
54 
55 namespace gem5
56 {
57 
58 using namespace linux;
59 using namespace ArmISA;
60 
61 ArmRelease::ArmRelease(const ArmReleaseParams &p)
62  : SimObject(p)
63 {
64  for (auto ext : p.extensions) {
65  fatal_if(_extensions.find(ext) != _extensions.end(),
66  "Duplicated FEAT_\n");
67 
68  _extensions[ext] = true;
69  }
70 }
71 
73  : System(p),
74  _genericTimer(nullptr),
75  _gic(nullptr),
76  _pwrCtrl(nullptr),
77  _highestELIs64(p.highest_el_is_64),
78  _physAddrRange64(p.phys_addr_range_64),
79  _haveLargeAsid64(p.have_large_asid_64),
80  _sveVL(p.sve_vl),
81  semihosting(p.semihosting),
82  release(p.release),
83  multiProc(p.multi_proc)
84 {
85  if (p.auto_reset_addr) {
87  } else {
88  _resetAddr = p.reset_addr;
90  "Workload entry point %#x and reset address %#x are different",
92  }
93 
94  bool wl_is_64 = (workload->getArch() == loader::Arm64);
95  if (wl_is_64 != _highestELIs64) {
96  warn("Highest ARM exception-level set to AArch%d but the workload "
97  "is for AArch%d. Assuming you wanted these to match.",
98  _highestELIs64 ? 64 : 32, wl_is_64 ? 64 : 32);
99  _highestELIs64 = wl_is_64;
100  }
101 
102  if (_highestELIs64 && (
103  _physAddrRange64 < 32 ||
105  (_physAddrRange64 % 4 != 0 && _physAddrRange64 != 42) ||
106  (_physAddrRange64 == 52 && !release->has(ArmExtension::FEAT_LPA))))
107  {
108  fatal("Invalid physical address range (%d)\n", _physAddrRange64);
109  }
110 }
111 
112 bool
113 ArmSystem::has(ArmExtension ext, ThreadContext *tc)
114 {
115  return FullSystem? getArmSystem(tc)->has(ext) : false;
116 }
117 
118 bool
120 {
121  return FullSystem? getArmSystem(tc)->highestELIs64() : true;
122 }
123 
126 {
127  return FullSystem? getArmSystem(tc)->highestEL() : EL1;
128 }
129 
130 bool
132 {
133  switch (el) {
134  case EL0:
135  case EL1:
136  return true;
137  case EL2:
138  return has(ArmExtension::VIRTUALIZATION, tc);
139  case EL3:
140  return has(ArmExtension::SECURITY, tc);
141  default:
142  warn("Unimplemented Exception Level\n");
143  return false;
144  }
145 }
146 
147 Addr
149 {
150  return getArmSystem(tc)->resetAddr();
151 }
152 
153 uint8_t
155 {
156  return getArmSystem(tc)->physAddrRange();
157 }
158 
159 Addr
161 {
162  return getArmSystem(tc)->physAddrMask();
163 }
164 
165 bool
167 {
168  return getArmSystem(tc)->haveLargeAsid64();
169 }
170 
171 bool
173 {
174  return FullSystem && getArmSystem(tc)->haveSemihosting();
175 }
176 
177 bool
179 {
180  return getArmSystem(tc)->semihosting->call64(tc, gem5_ops);
181 }
182 
183 bool
185 {
186  return getArmSystem(tc)->semihosting->call32(tc, gem5_ops);
187 }
188 
189 bool
191 {
192  if (ArmISA::inAArch64(tc))
193  return callSemihosting64(tc, gem5_ops);
194  else
195  return callSemihosting32(tc, gem5_ops);
196 }
197 
198 void
200 {
201  if (FVPBasePwrCtrl *pwr_ctrl = getArmSystem(tc)->getPowerController())
202  pwr_ctrl->setStandByWfi(tc);
203 }
204 
205 void
207 {
208  if (FVPBasePwrCtrl *pwr_ctrl = getArmSystem(tc)->getPowerController())
209  pwr_ctrl->clearStandByWfi(tc);
210 }
211 
212 bool
214 {
215  if (FVPBasePwrCtrl *pwr_ctrl = getArmSystem(tc)->getPowerController())
216  return pwr_ctrl->setWakeRequest(tc);
217  else
218  return true;
219 }
220 
221 void
223 {
224  if (FVPBasePwrCtrl *pwr_ctrl = getArmSystem(tc)->getPowerController())
225  pwr_ctrl->clearWakeRequest(tc);
226 }
227 
228 } // namespace gem5
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:190
gem5::ArmSystem::physAddrRange
uint8_t physAddrRange() const
Returns the supported physical address range in bits.
Definition: system.hh:213
warn
#define warn(...)
Definition: logging.hh:246
gem5::Workload::getEntry
virtual Addr getEntry() const =0
gem5::ArmSystem::ArmSystem
ArmSystem(const Params &p)
Definition: system.cc:72
gem5::ArmSystem::highestELIs64
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:183
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition: misc_types.hh:73
gem5::ArmSystem::callSemihosting64
static bool callSemihosting64(ThreadContext *tc, bool gem5_ops=false)
Make a Semihosting call from aarch64.
Definition: system.cc:178
fs_workload.hh
gem5::ArmSystem::callClearWakeRequest
static void callClearWakeRequest(ThreadContext *tc)
Notify the power controller of WAKEREQUEST deassertion.
Definition: system.cc:222
gem5::ArmSystem::haveLargeAsid64
bool haveLargeAsid64() const
Returns true if ASID is 16 bits in AArch64 (ARMv8)
Definition: system.hh:202
gem5::ArmSystem::getPowerController
FVPBasePwrCtrl * getPowerController() const
Get a pointer to the system's power controller.
Definition: system.hh:179
gem5::ArmISA::MaxPhysAddrRange
const unsigned MaxPhysAddrRange
Definition: pagetable.hh:73
gem5::ArmISA::EL1
@ EL1
Definition: types.hh:274
gem5::System::workload
Workload * workload
OS kernel.
Definition: system.hh:330
gem5::ArmSystem::callSemihosting
static bool callSemihosting(ThreadContext *tc, bool gem5_ops=false)
Make a Semihosting call from either aarch64 or aarch32.
Definition: system.cc:190
gem5::ArmISA::inAArch64
bool inAArch64(ThreadContext *tc)
Definition: utility.cc:122
system.hh
gem5::Workload::getArch
virtual loader::Arch getArch() const =0
gem5::ArmSemihosting::call32
bool call32(ThreadContext *tc, bool gem5_ops)
Perform an Arm Semihosting call from aarch32 code.
Definition: semihosting.cc:196
gem5::loader::Arm64
@ Arm64
Definition: object_file.hh:70
gem5::ArmSystem::getArmSystem
static ArmSystem * getArmSystem(ThreadContext *tc)
Returns a valid ArmSystem pointer if using ARM ISA, it fails otherwise.
Definition: system.hh:233
gem5::ArmSystem::_resetAddr
Addr _resetAddr
Reset address (ARMv8)
Definition: system.hh:108
gem5::SimObject::Params
SimObjectParams Params
Definition: sim_object.hh:170
gem5::ArmRelease::has
bool has(ArmExtension ext) const
Definition: system.hh:75
gem5::ArmRelease::ArmRelease
ArmRelease(const Params &p)
Definition: system.cc:61
gem5::System
Definition: system.hh:75
gem5::ArmSystem::highestEL
ArmISA::ExceptionLevel highestEL() const
Returns the highest implemented exception level.
Definition: system.hh:187
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:275
gem5::ArmSystem::semihosting
ArmSemihosting *const semihosting
True if the Semihosting interface is enabled.
Definition: system.hh:133
gem5::ArmISA::EL3
@ EL3
Definition: types.hh:276
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::ArmISA::ext
Bitfield< 12 > ext
Definition: misc_types.hh:428
gem5::ArmSystem::_physAddrRange64
const uint8_t _physAddrRange64
Supported physical address range in bits if the highest implemented exception level is 64 bits (ARMv8...
Definition: system.hh:120
gem5::ArmSystem::callSetWakeRequest
static bool callSetWakeRequest(ThreadContext *tc)
Notify the power controller of WAKEREQUEST assertion.
Definition: system.cc:213
gem5::ArmSemihosting::call64
bool call64(ThreadContext *tc, bool gem5_ops)
Perform an Arm Semihosting call from aarch64 code.
Definition: semihosting.cc:170
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmSystem::callClearStandByWfi
static void callClearStandByWfi(ThreadContext *tc)
Make a call to notify the power controller of STANDBYWFI deassertion.
Definition: system.cc:206
gem5::ArmSystem::_highestELIs64
bool _highestELIs64
True if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:114
fvp_base_pwr_ctrl.hh
gem5::ArmSystem::physAddrMask
Addr physAddrMask() const
Returns the physical address mask.
Definition: system.hh:223
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
gem5::ArmSystem::has
bool has(ArmExtension ext) const
Definition: system.hh:154
gem5::ArmSystem::release
const ArmRelease * release
Arm Release object: contains a list of implemented features.
Definition: system.hh:139
warn_if
#define warn_if(cond,...)
Conditional warning macro that checks the supplied condition and only prints a warning if the conditi...
Definition: logging.hh:273
gem5::ArmSystem::callSetStandByWfi
static void callSetStandByWfi(ThreadContext *tc)
Make a call to notify the power controller of STANDBYWFI assertion.
Definition: system.cc:199
gem5::ArmISA::EL0
@ EL0
Definition: types.hh:273
gem5::FVPBasePwrCtrl
Definition: fvp_base_pwr_ctrl.hh:58
gem5::ArmRelease::_extensions
std::unordered_map< ArmExtension, bool > _extensions
List of implemented extensions.
Definition: system.hh:88
semihosting.hh
gem5::ArmSystem::haveSemihosting
bool haveSemihosting() const
Is Arm Semihosting support enabled?
Definition: system.hh:226
physical.hh
gem5::ArmSystem::resetAddr
Addr resetAddr() const
Returns the reset address if the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:198
symtab.hh
gem5::ArmSystem::haveEL
static bool haveEL(ThreadContext *tc, ArmISA::ExceptionLevel el)
Return true if the system implements a specific exception level.
Definition: system.cc:131
gic_v2.hh
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:226
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
object_file.hh
gem5::ArmSystem::callSemihosting32
static bool callSemihosting32(ThreadContext *tc, bool gem5_ops=false)
Make a Semihosting call from aarch32.
Definition: system.cc:184
thread_context.hh
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:271

Generated on Thu Jul 28 2022 13:32:25 for gem5 by doxygen 1.8.17