gem5  v21.1.0.2
system.cc
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40 
41 #include "arch/arm/system.hh"
42 
43 #include <iostream>
44 
45 #include "arch/arm/fs_workload.hh"
46 #include "arch/arm/semihosting.hh"
48 #include "base/loader/symtab.hh"
49 #include "cpu/thread_context.hh"
51 #include "dev/arm/gic_v2.hh"
52 #include "mem/physical.hh"
53 
54 namespace gem5
55 {
56 
57 using namespace linux;
58 using namespace ArmISA;
59 
61  : System(p),
62  _haveSecurity(p.have_security),
63  _haveLPAE(p.have_lpae),
64  _haveVirtualization(p.have_virtualization),
65  _haveCrypto(p.have_crypto),
66  _genericTimer(nullptr),
67  _gic(nullptr),
68  _pwrCtrl(nullptr),
69  _highestELIs64(p.highest_el_is_64),
70  _physAddrRange64(p.phys_addr_range_64),
71  _haveLargeAsid64(p.have_large_asid_64),
72  _haveTME(p.have_tme),
73  _haveSVE(p.have_sve),
74  _sveVL(p.sve_vl),
75  _haveLSE(p.have_lse),
76  _haveVHE(p.have_vhe),
77  _havePAN(p.have_pan),
78  _haveSecEL2(p.have_secel2),
79  semihosting(p.semihosting),
80  multiProc(p.multi_proc)
81 {
82  if (p.auto_reset_addr) {
84  } else {
85  _resetAddr = p.reset_addr;
87  "Workload entry point %#x and reset address %#x are different",
89  }
90 
91  bool wl_is_64 = (workload->getArch() == loader::Arm64);
92  if (wl_is_64 != _highestELIs64) {
93  warn("Highest ARM exception-level set to AArch%d but the workload "
94  "is for AArch%d. Assuming you wanted these to match.",
95  _highestELIs64 ? 64 : 32, wl_is_64 ? 64 : 32);
96  _highestELIs64 = wl_is_64;
97  }
98 
99  if (_highestELIs64 && (
100  _physAddrRange64 < 32 ||
102  (_physAddrRange64 % 4 != 0 && _physAddrRange64 != 42))) {
103  fatal("Invalid physical address range (%d)\n", _physAddrRange64);
104  }
105 }
106 
107 bool
109 {
110  return FullSystem? getArmSystem(tc)->haveSecurity() : false;
111 }
112 
113 bool
115 {
116  return FullSystem? getArmSystem(tc)->haveLPAE() : false;
117 }
118 
119 bool
121 {
122  return FullSystem? getArmSystem(tc)->haveVirtualization() : false;
123 }
124 
125 bool
127 {
128  return FullSystem? getArmSystem(tc)->highestELIs64() : true;
129 }
130 
133 {
134  return FullSystem? getArmSystem(tc)->highestEL() : EL1;
135 }
136 
137 bool
139 {
140  switch (el) {
141  case EL0:
142  case EL1:
143  return true;
144  case EL2:
145  return haveVirtualization(tc);
146  case EL3:
147  return haveSecurity(tc);
148  default:
149  warn("Unimplemented Exception Level\n");
150  return false;
151  }
152 }
153 
154 bool
156 {
157  return getArmSystem(tc)->haveTME();
158 }
159 
160 Addr
162 {
163  return getArmSystem(tc)->resetAddr();
164 }
165 
166 uint8_t
168 {
169  return getArmSystem(tc)->physAddrRange();
170 }
171 
172 Addr
174 {
175  return getArmSystem(tc)->physAddrMask();
176 }
177 
178 bool
180 {
181  return getArmSystem(tc)->haveLargeAsid64();
182 }
183 
184 bool
186 {
187  return FullSystem && getArmSystem(tc)->haveSemihosting();
188 }
189 
190 bool
192 {
193  return getArmSystem(tc)->semihosting->call64(tc, gem5_ops);
194 }
195 
196 bool
198 {
199  return getArmSystem(tc)->semihosting->call32(tc, gem5_ops);
200 }
201 
202 bool
204 {
205  if (ArmISA::inAArch64(tc))
206  return callSemihosting64(tc, gem5_ops);
207  else
208  return callSemihosting32(tc, gem5_ops);
209 }
210 
211 void
213 {
214  if (FVPBasePwrCtrl *pwr_ctrl = getArmSystem(tc)->getPowerController())
215  pwr_ctrl->setStandByWfi(tc);
216 }
217 
218 void
220 {
221  if (FVPBasePwrCtrl *pwr_ctrl = getArmSystem(tc)->getPowerController())
222  pwr_ctrl->clearStandByWfi(tc);
223 }
224 
225 bool
227 {
228  if (FVPBasePwrCtrl *pwr_ctrl = getArmSystem(tc)->getPowerController())
229  return pwr_ctrl->setWakeRequest(tc);
230  else
231  return true;
232 }
233 
234 void
236 {
237  if (FVPBasePwrCtrl *pwr_ctrl = getArmSystem(tc)->getPowerController())
238  pwr_ctrl->clearWakeRequest(tc);
239 }
240 
241 } // namespace gem5
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:189
gem5::ArmSystem::physAddrRange
uint8_t physAddrRange() const
Returns the supported physical address range in bits.
Definition: system.hh:255
warn
#define warn(...)
Definition: logging.hh:245
gem5::Workload::getEntry
virtual Addr getEntry() const =0
gem5::ArmSystem::ArmSystem
ArmSystem(const Params &p)
Definition: system.cc:60
gem5::ArmSystem::highestELIs64
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:205
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition: misc_types.hh:72
gem5::ArmSystem::haveLPAE
bool haveLPAE() const
Returns true if this system implements the Large Physical Address Extension.
Definition: system.hh:166
gem5::ArmSystem::callSemihosting64
static bool callSemihosting64(ThreadContext *tc, bool gem5_ops=false)
Make a Semihosting call from aarch64.
Definition: system.cc:191
fs_workload.hh
gem5::ArmSystem::callClearWakeRequest
static void callClearWakeRequest(ThreadContext *tc)
Notify the power controller of WAKEREQUEST deassertion.
Definition: system.cc:235
gem5::ArmSystem::haveLargeAsid64
bool haveLargeAsid64() const
Returns true if ASID is 16 bits in AArch64 (ARMv8)
Definition: system.hh:224
gem5::ArmSystem::getPowerController
FVPBasePwrCtrl * getPowerController() const
Get a pointer to the system's power controller.
Definition: system.hh:201
gem5::ArmISA::MaxPhysAddrRange
const unsigned MaxPhysAddrRange
Definition: pagetable.hh:58
gem5::ArmISA::EL1
@ EL1
Definition: types.hh:267
gem5::System::workload
Workload * workload
OS kernel.
Definition: system.hh:335
gem5::ArmSystem::callSemihosting
static bool callSemihosting(ThreadContext *tc, bool gem5_ops=false)
Make a Semihosting call from either aarch64 or aarch32.
Definition: system.cc:203
gem5::ArmISA::inAArch64
bool inAArch64(ThreadContext *tc)
Definition: utility.cc:120
system.hh
gem5::Workload::getArch
virtual loader::Arch getArch() const =0
gem5::ArmSemihosting::call32
bool call32(ThreadContext *tc, bool gem5_ops)
Perform an Arm Semihosting call from aarch32 code.
Definition: semihosting.cc:196
gem5::loader::Arm64
@ Arm64
Definition: object_file.hh:58
gem5::ArmSystem::getArmSystem
static ArmSystem * getArmSystem(ThreadContext *tc)
Returns a valid ArmSystem pointer if using ARM ISA, it fails otherwise.
Definition: system.hh:275
gem5::ArmSystem::_resetAddr
Addr _resetAddr
Reset address (ARMv8)
Definition: system.hh:99
gem5::SimObject::Params
SimObjectParams Params
Definition: sim_object.hh:170
gem5::System
Definition: system.hh:77
gem5::ArmSystem::highestEL
ArmISA::ExceptionLevel highestEL() const
Returns the highest implemented exception level.
Definition: system.hh:209
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:268
gem5::ArmSystem::semihosting
ArmSemihosting *const semihosting
True if the Semihosting interface is enabled.
Definition: system.hh:148
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::ArmISA::EL3
@ EL3
Definition: types.hh:269
gem5::ArmSystem::_physAddrRange64
const uint8_t _physAddrRange64
Supported physical address range in bits if the highest implemented exception level is 64 bits (ARMv8...
Definition: system.hh:111
gem5::ArmSystem::callSetWakeRequest
static bool callSetWakeRequest(ThreadContext *tc)
Notify the power controller of WAKEREQUEST assertion.
Definition: system.cc:226
gem5::ArmSemihosting::call64
bool call64(ThreadContext *tc, bool gem5_ops)
Perform an Arm Semihosting call from aarch64 code.
Definition: semihosting.cc:170
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmSystem::callClearStandByWfi
static void callClearStandByWfi(ThreadContext *tc)
Make a call to notify the power controller of STANDBYWFI deassertion.
Definition: system.cc:219
gem5::ArmSystem::_highestELIs64
bool _highestELIs64
True if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:105
fvp_base_pwr_ctrl.hh
gem5::ArmSystem::physAddrMask
Addr physAddrMask() const
Returns the physical address mask.
Definition: system.hh:265
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:223
warn_if
#define warn_if(cond,...)
Conditional warning macro that checks the supplied condition and only prints a warning if the conditi...
Definition: logging.hh:272
gem5::ArmSystem::callSetStandByWfi
static void callSetStandByWfi(ThreadContext *tc)
Make a call to notify the power controller of STANDBYWFI assertion.
Definition: system.cc:212
gem5::ArmISA::EL0
@ EL0
Definition: types.hh:266
gem5::FVPBasePwrCtrl
Definition: fvp_base_pwr_ctrl.hh:58
semihosting.hh
gem5::ArmSystem::haveSemihosting
bool haveSemihosting() const
Is Arm Semihosting support enabled?
Definition: system.hh:268
physical.hh
gem5::ArmSystem::haveSecurity
bool haveSecurity() const
Returns true if this system implements the Security Extensions.
Definition: system.hh:162
gem5::ArmSystem::resetAddr
Addr resetAddr() const
Returns the reset address if the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:220
symtab.hh
gem5::ArmSystem::haveEL
static bool haveEL(ThreadContext *tc, ArmISA::ExceptionLevel el)
Return true if the system implements a specific exception level.
Definition: system.cc:138
gic_v2.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmSystem::haveTME
bool haveTME() const
Returns true if this system implements the transactional memory extension (ARMv9)
Definition: system.hh:229
object_file.hh
gem5::ArmSystem::callSemihosting32
static bool callSemihosting32(ThreadContext *tc, bool gem5_ops=false)
Make a Semihosting call from aarch32.
Definition: system.cc:197
thread_context.hh
gem5::ArmSystem::haveVirtualization
bool haveVirtualization() const
Returns true if this system implements the virtualization Extensions.
Definition: system.hh:171
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:264

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