gem5  v22.1.0.0
system.cc
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40 
41 #include "arch/arm/system.hh"
42 
43 #include <iostream>
44 
45 #include "arch/arm/fs_workload.hh"
46 #include "arch/arm/semihosting.hh"
48 #include "base/loader/symtab.hh"
49 #include "cpu/thread_context.hh"
51 #include "dev/arm/gic_v2.hh"
52 #include "mem/physical.hh"
53 #include "params/ArmRelease.hh"
54 
55 namespace gem5
56 {
57 
58 using namespace linux;
59 using namespace ArmISA;
60 
61 ArmRelease::ArmRelease(const ArmReleaseParams &p)
62  : SimObject(p)
63 {
64  for (auto ext : p.extensions) {
65  fatal_if(_extensions.find(ext) != _extensions.end(),
66  "Duplicated FEAT_\n");
67 
68  _extensions[ext] = true;
69  }
70 }
71 
73  : System(p),
74  _genericTimer(nullptr),
75  _gic(nullptr),
76  _pwrCtrl(nullptr),
77  _highestELIs64(p.highest_el_is_64),
78  _physAddrRange64(p.phys_addr_range_64),
79  _haveLargeAsid64(p.have_large_asid_64),
80  _sveVL(p.sve_vl),
81  semihosting(p.semihosting),
82  release(p.release),
83  multiProc(p.multi_proc)
84 {
85  if (p.auto_reset_addr) {
87  } else {
88  _resetAddr = p.reset_addr;
90  "Workload entry point %#x and reset address %#x are different",
92  }
93 
94  bool wl_is_64 = (workload->getArch() == loader::Arm64);
95  if (wl_is_64 != _highestELIs64) {
96  warn("Highest ARM exception-level set to AArch%d but the workload "
97  "is for AArch%d. Assuming you wanted these to match.",
98  _highestELIs64 ? 64 : 32, wl_is_64 ? 64 : 32);
99  _highestELIs64 = wl_is_64;
100  }
101 
102  if (_highestELIs64 && (
103  _physAddrRange64 < 32 ||
105  (_physAddrRange64 % 4 != 0 && _physAddrRange64 != 42) ||
106  (_physAddrRange64 == 52 && !release->has(ArmExtension::FEAT_LPA))))
107  {
108  fatal("Invalid physical address range (%d)\n", _physAddrRange64);
109  }
110 }
111 
112 bool
113 ArmSystem::has(ArmExtension ext, ThreadContext *tc)
114 {
115  return FullSystem? getArmSystem(tc)->has(ext) : false;
116 }
117 
118 bool
120 {
121  return FullSystem? getArmSystem(tc)->highestELIs64() : true;
122 }
123 
126 {
127  return FullSystem? getArmSystem(tc)->highestEL() : EL1;
128 }
129 
130 bool
132 {
133  switch (el) {
134  case EL0:
135  case EL1:
136  return true;
137  case EL2:
138  return has(ArmExtension::VIRTUALIZATION, tc);
139  case EL3:
140  return has(ArmExtension::SECURITY, tc);
141  default:
142  warn("Unimplemented Exception Level\n");
143  return false;
144  }
145 }
146 
147 Addr
149 {
150  return getArmSystem(tc)->resetAddr();
151 }
152 
153 uint8_t
155 {
156  return getArmSystem(tc)->physAddrRange();
157 }
158 
159 Addr
161 {
162  return getArmSystem(tc)->physAddrMask();
163 }
164 
165 bool
167 {
168  return getArmSystem(tc)->haveLargeAsid64();
169 }
170 
171 bool
173 {
174  return FullSystem && getArmSystem(tc)->haveSemihosting();
175 }
176 
177 bool
179 {
180  return getArmSystem(tc)->semihosting->call64(tc, gem5_ops);
181 }
182 
183 bool
185 {
186  return getArmSystem(tc)->semihosting->call32(tc, gem5_ops);
187 }
188 
189 bool
191 {
192  if (ArmISA::inAArch64(tc))
193  return callSemihosting64(tc, gem5_ops);
194  else
195  return callSemihosting32(tc, gem5_ops);
196 }
197 
198 void
200 {
201  if (FVPBasePwrCtrl *pwr_ctrl = getArmSystem(tc)->getPowerController())
202  pwr_ctrl->setStandByWfi(tc);
203 }
204 
205 void
207 {
208  if (FVPBasePwrCtrl *pwr_ctrl = getArmSystem(tc)->getPowerController())
209  pwr_ctrl->clearStandByWfi(tc);
210 }
211 
212 bool
214 {
215  if (FVPBasePwrCtrl *pwr_ctrl = getArmSystem(tc)->getPowerController())
216  return pwr_ctrl->setWakeRequest(tc);
217  else
218  return true;
219 }
220 
221 void
223 {
224  if (FVPBasePwrCtrl *pwr_ctrl = getArmSystem(tc)->getPowerController())
225  pwr_ctrl->clearWakeRequest(tc);
226 }
227 
228 } // namespace gem5
bool has(ArmExtension ext) const
Definition: system.hh:76
ArmRelease(const Params &p)
Definition: system.cc:61
std::unordered_map< ArmExtension, bool > _extensions
List of implemented extensions.
Definition: system.hh:89
bool call32(ThreadContext *tc, bool gem5_ops)
Perform an Arm Semihosting call from aarch32 code.
Definition: semihosting.cc:196
bool call64(ThreadContext *tc, bool gem5_ops)
Perform an Arm Semihosting call from aarch64 code.
Definition: semihosting.cc:170
static ArmSystem * getArmSystem(ThreadContext *tc)
Returns a valid ArmSystem pointer if using ARM ISA, it fails otherwise.
Definition: system.hh:234
Addr physAddrMask() const
Returns the physical address mask.
Definition: system.hh:224
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:184
ArmISA::ExceptionLevel highestEL() const
Returns the highest implemented exception level.
Definition: system.hh:188
static bool callSemihosting32(ThreadContext *tc, bool gem5_ops=false)
Make a Semihosting call from aarch32.
Definition: system.cc:184
bool haveSemihosting() const
Is Arm Semihosting support enabled?
Definition: system.hh:227
const uint8_t _physAddrRange64
Supported physical address range in bits if the highest implemented exception level is 64 bits (ARMv8...
Definition: system.hh:121
static void callClearStandByWfi(ThreadContext *tc)
Make a call to notify the power controller of STANDBYWFI deassertion.
Definition: system.cc:206
static void callSetStandByWfi(ThreadContext *tc)
Make a call to notify the power controller of STANDBYWFI assertion.
Definition: system.cc:199
ArmSemihosting *const semihosting
True if the Semihosting interface is enabled.
Definition: system.hh:134
Addr _resetAddr
Reset address (ARMv8)
Definition: system.hh:109
static bool callSemihosting(ThreadContext *tc, bool gem5_ops=false)
Make a Semihosting call from either aarch64 or aarch32.
Definition: system.cc:190
uint8_t physAddrRange() const
Returns the supported physical address range in bits.
Definition: system.hh:214
static bool callSetWakeRequest(ThreadContext *tc)
Notify the power controller of WAKEREQUEST assertion.
Definition: system.cc:213
bool has(ArmExtension ext) const
Definition: system.hh:155
bool haveLargeAsid64() const
Returns true if ASID is 16 bits in AArch64 (ARMv8)
Definition: system.hh:203
Addr resetAddr() const
Returns the reset address if the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:199
static bool haveEL(ThreadContext *tc, ArmISA::ExceptionLevel el)
Return true if the system implements a specific exception level.
Definition: system.cc:131
FVPBasePwrCtrl * getPowerController() const
Get a pointer to the system's power controller.
Definition: system.hh:180
static void callClearWakeRequest(ThreadContext *tc)
Notify the power controller of WAKEREQUEST deassertion.
Definition: system.cc:222
ArmSystem(const Params &p)
Definition: system.cc:72
bool _highestELIs64
True if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:115
static bool callSemihosting64(ThreadContext *tc, bool gem5_ops=false)
Make a Semihosting call from aarch64.
Definition: system.cc:178
const ArmRelease * release
Arm Release object: contains a list of implemented features.
Definition: system.hh:140
Abstract superclass for simulation objects.
Definition: sim_object.hh:148
SimObjectParams Params
Definition: sim_object.hh:170
Workload * workload
OS kernel.
Definition: system.hh:329
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual loader::Arch getArch() const =0
virtual Addr getEntry() const =0
This class implements the base power controller for FVP-based platforms.
Implementation of a GICv2.
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:226
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:190
#define warn(...)
Definition: logging.hh:246
#define warn_if(cond,...)
Conditional warning macro that checks the supplied condition and only prints a warning if the conditi...
Definition: logging.hh:273
const unsigned MaxPhysAddrRange
Definition: pagetable.hh:73
Bitfield< 3, 2 > el
Definition: misc_types.hh:73
bool inAArch64(ThreadContext *tc)
Definition: utility.cc:117
Bitfield< 12 > ext
Definition: misc_types.hh:434
Bitfield< 54 > p
Definition: pagetable.hh:70
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220

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