gem5  v22.0.0.2
remote_gdb.cc
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39 
40 #include "arch/x86/remote_gdb.hh"
41 
42 #include <sys/signal.h>
43 #include <unistd.h>
44 
45 #include <string>
46 
47 #include "arch/x86/mmu.hh"
49 #include "arch/x86/process.hh"
50 #include "arch/x86/regs/int.hh"
51 #include "arch/x86/regs/misc.hh"
53 #include "base/logging.hh"
54 #include "base/remote_gdb.hh"
55 #include "base/socket.hh"
56 #include "base/trace.hh"
57 #include "cpu/base.hh"
58 #include "cpu/thread_context.hh"
59 #include "debug/GDBAcc.hh"
60 #include "mem/page_table.hh"
61 #include "sim/full_system.hh"
62 #include "sim/workload.hh"
63 
64 namespace gem5
65 {
66 
67 using namespace X86ISA;
68 
69 RemoteGDB::RemoteGDB(System *_system, int _port) :
70  BaseRemoteGDB(_system, _port), regCache32(this), regCache64(this)
71 {}
72 
73 bool
74 RemoteGDB::acc(Addr va, size_t len)
75 {
76  if (FullSystem) {
77  Walker *walker = dynamic_cast<MMU *>(
78  context()->getMMUPtr())->getDataWalker();
79  unsigned logBytes;
80  Fault fault = walker->startFunctional(context(), va, logBytes,
82  if (fault != NoFault)
83  return false;
84 
85  Addr endVa = va + len - 1;
86  if ((va & ~mask(logBytes)) == (endVa & ~mask(logBytes)))
87  return true;
88 
89  fault = walker->startFunctional(context(), endVa, logBytes,
91  return fault == NoFault;
92  } else {
93  return context()->getProcessPtr()->pTable->lookup(va) != nullptr;
94  }
95 }
96 
97 BaseGdbRegCache*
99 {
100  // First, try to figure out which type of register cache to return based
101  // on the architecture reported by the workload.
102  if (system()->workload) {
103  auto arch = system()->workload->getArch();
104  if (arch == loader::X86_64) {
105  return &regCache64;
106  } else if (arch == loader::I386) {
107  return &regCache32;
108  } else if (arch != loader::UnknownArch) {
109  panic("Unrecognized workload arch %s.",
110  loader::archToString(arch));
111  }
112  }
113 
114  // If that didn't work, decide based on the current mode of the context.
115  HandyM5Reg m5reg = context()->readMiscRegNoEffect(misc_reg::M5Reg);
116  if (m5reg.submode == SixtyFourBitMode)
117  return &regCache64;
118  else
119  return &regCache32;
120 }
121 
122 
123 
124 void
125 RemoteGDB::AMD64GdbRegCache::getRegs(ThreadContext *context)
126 {
127  DPRINTF(GDBAcc, "getRegs in remotegdb \n");
128  r.rax = context->getReg(int_reg::Rax);
129  r.rbx = context->getReg(int_reg::Rbx);
130  r.rcx = context->getReg(int_reg::Rcx);
131  r.rdx = context->getReg(int_reg::Rdx);
132  r.rsi = context->getReg(int_reg::Rsi);
133  r.rdi = context->getReg(int_reg::Rdi);
134  r.rbp = context->getReg(int_reg::Rbp);
135  r.rsp = context->getReg(int_reg::Rsp);
136  r.r8 = context->getReg(int_reg::R8);
137  r.r9 = context->getReg(int_reg::R9);
138  r.r10 = context->getReg(int_reg::R10);
139  r.r11 = context->getReg(int_reg::R11);
140  r.r12 = context->getReg(int_reg::R12);
141  r.r13 = context->getReg(int_reg::R13);
142  r.r14 = context->getReg(int_reg::R14);
143  r.r15 = context->getReg(int_reg::R15);
144  r.rip = context->pcState().instAddr();
152 }
153 
154 void
155 RemoteGDB::X86GdbRegCache::getRegs(ThreadContext *context)
156 {
157  DPRINTF(GDBAcc, "getRegs in remotegdb \n");
158  r.eax = context->getReg(int_reg::Rax);
159  r.ecx = context->getReg(int_reg::Rcx);
160  r.edx = context->getReg(int_reg::Rdx);
161  r.ebx = context->getReg(int_reg::Rbx);
162  r.esp = context->getReg(int_reg::Rsp);
163  r.ebp = context->getReg(int_reg::Rbp);
164  r.esi = context->getReg(int_reg::Rsi);
165  r.edi = context->getReg(int_reg::Rdi);
166  r.eip = context->pcState().instAddr();
174 }
175 
176 void
177 RemoteGDB::AMD64GdbRegCache::setRegs(ThreadContext *context) const
178 {
179  DPRINTF(GDBAcc, "setRegs in remotegdb \n");
180  context->setReg(int_reg::Rax, r.rax);
181  context->setReg(int_reg::Rbx, r.rbx);
182  context->setReg(int_reg::Rcx, r.rcx);
183  context->setReg(int_reg::Rdx, r.rdx);
184  context->setReg(int_reg::Rsi, r.rsi);
185  context->setReg(int_reg::Rdi, r.rdi);
186  context->setReg(int_reg::Rbp, r.rbp);
187  context->setReg(int_reg::Rsp, r.rsp);
188  context->setReg(int_reg::R8, r.r8);
189  context->setReg(int_reg::R9, r.r9);
190  context->setReg(int_reg::R10, r.r10);
191  context->setReg(int_reg::R11, r.r11);
192  context->setReg(int_reg::R12, r.r12);
193  context->setReg(int_reg::R13, r.r13);
194  context->setReg(int_reg::R14, r.r14);
195  context->setReg(int_reg::R15, r.r15);
196  context->pcState(r.rip);
199  warn("Remote gdb: Ignoring update to CS.\n");
201  warn("Remote gdb: Ignoring update to SS.\n");
203  warn("Remote gdb: Ignoring update to DS.\n");
205  warn("Remote gdb: Ignoring update to ES.\n");
207  warn("Remote gdb: Ignoring update to FS.\n");
209  warn("Remote gdb: Ignoring update to GS.\n");
210 }
211 
212 void
213 RemoteGDB::X86GdbRegCache::setRegs(ThreadContext *context) const
214 {
215  DPRINTF(GDBAcc, "setRegs in remotegdb \n");
216  context->setReg(int_reg::Rax, r.eax);
217  context->setReg(int_reg::Rcx, r.ecx);
218  context->setReg(int_reg::Rdx, r.edx);
219  context->setReg(int_reg::Rbx, r.ebx);
220  context->setReg(int_reg::Rsp, r.esp);
221  context->setReg(int_reg::Rbp, r.ebp);
222  context->setReg(int_reg::Rsi, r.esi);
223  context->setReg(int_reg::Rdi, r.edi);
224  context->pcState(r.eip);
227  warn("Remote gdb: Ignoring update to CS.\n");
229  warn("Remote gdb: Ignoring update to SS.\n");
231  warn("Remote gdb: Ignoring update to DS.\n");
233  warn("Remote gdb: Ignoring update to ES.\n");
235  warn("Remote gdb: Ignoring update to FS.\n");
237  warn("Remote gdb: Ignoring update to GS.\n");
238 }
239 
240 } // namespace gem5
gem5::PowerISA::int_reg::R14
constexpr RegId R14(IntRegClass, _R14Idx)
gem5::PCStateBase::instAddr
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Definition: pcstate.hh:107
gem5::BaseMMU::Read
@ Read
Definition: mmu.hh:56
socket.hh
gem5::SparcISA::RemoteGDB::gdbRegs
BaseGdbRegCache * gdbRegs()
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:253
warn
#define warn(...)
Definition: logging.hh:246
gem5::X86ISA::RemoteGDB::RemoteGDB
RemoteGDB(System *system, int _port)
mmu.hh
gem5::ThreadContext::getReg
virtual RegVal getReg(const RegId &reg) const
Definition: thread_context.cc:171
gem5::X86ISA::misc_reg::M5Reg
@ M5Reg
Definition: misc.hh:146
remote_gdb.hh
gem5::ThreadContext::getMMUPtr
virtual BaseMMU * getMMUPtr()=0
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::X86ISA::misc_reg::Ss
@ Ss
Definition: misc.hh:307
gem5::loader::X86_64
@ X86_64
Definition: object_file.hh:68
pagetable_walker.hh
gem5::System::workload
Workload * workload
OS kernel.
Definition: system.hh:330
gem5::EmulationPageTable::lookup
const Entry * lookup(Addr vaddr)
Lookup function.
Definition: page_table.cc:133
gem5::VegaISA::r
Bitfield< 5 > r
Definition: pagetable.hh:60
gem5::SparcISA::RemoteGDB::acc
bool acc(Addr addr, size_t len)
gem5::X86ISA::SixtyFourBitMode
@ SixtyFourBitMode
Definition: types.hh:204
gem5::Workload::getArch
virtual loader::Arch getArch() const =0
gem5::mask
constexpr uint64_t mask(unsigned nbits)
Generate a 64-bit mask of 'nbits' 1s, right justified.
Definition: bitfield.hh:63
gem5::PowerISA::int_reg::R10
constexpr RegId R10(IntRegClass, _R10Idx)
gem5::SparcISA::RemoteGDB::regCache64
SPARC64GdbRegCache regCache64
Definition: remote_gdb.hh:108
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
workload.hh
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
int.hh
gem5::Process::pTable
EmulationPageTable * pTable
Definition: process.hh:185
gem5::PowerISA::int_reg::R8
constexpr RegId R8(IntRegClass, _R8Idx)
gem5::SparcISA::RemoteGDB::regCache32
SPARCGdbRegCache regCache32
Definition: remote_gdb.hh:107
len
uint16_t len
Definition: helpers.cc:62
gem5::PowerISA::int_reg::R11
constexpr RegId R11(IntRegClass, _R11Idx)
remote_gdb.hh
gem5::PowerISA::int_reg::R9
constexpr RegId R9(IntRegClass, _R9Idx)
gem5::loader::archToString
const char * archToString(Arch arch)
Definition: object_file.cc:58
gem5::X86ISA::misc_reg::Ds
@ Ds
Definition: misc.hh:308
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::misc_reg::Cs
@ Cs
Definition: misc.hh:306
gem5::ArmISA::va
Bitfield< 8 > va
Definition: misc_types.hh:276
full_system.hh
gem5::ThreadContext::getProcessPtr
virtual Process * getProcessPtr()=0
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
gem5::loader::UnknownArch
@ UnknownArch
Definition: object_file.hh:64
gem5::X86ISA::misc_reg::Gs
@ Gs
Definition: misc.hh:310
process.hh
base.hh
gem5::PowerISA::int_reg::R15
constexpr RegId R15(IntRegClass, _R15Idx)
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
logging.hh
gem5::loader::I386
@ I386
Definition: object_file.hh:69
gem5::X86ISA::misc_reg::Rflags
@ Rflags
Definition: misc.hh:143
gem5::BaseRemoteGDB::context
ThreadContext * context()
Definition: remote_gdb.hh:395
gem5::BaseRemoteGDB::system
System * system()
Definition: remote_gdb.hh:396
trace.hh
gem5::X86ISA::misc_reg::Es
@ Es
Definition: misc.hh:305
page_table.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
misc.hh
object_file.hh
thread_context.hh
gem5::X86ISA::misc_reg::Fs
@ Fs
Definition: misc.hh:309
gem5::PowerISA::int_reg::R12
constexpr RegId R12(IntRegClass, _R12Idx)
gem5::PowerISA::int_reg::R13
constexpr RegId R13(IntRegClass, _R13Idx)
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::ThreadContext::setReg
virtual void setReg(const RegId &reg, RegVal val)
Definition: thread_context.cc:183

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