gem5  v21.1.0.2
remote_gdb.cc
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1 /*
2  * Copyright 2015 LabWare
3  * Copyright 2014 Google Inc.
4  * Copyright (c) 2010, 2013, 2016, 2018-2019 ARM Limited
5  * All rights reserved
6  *
7  * The license below extends only to copyright in the software and shall
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14  * modified or unmodified, in source code or in binary form.
15  *
16  * Copyright (c) 2002-2005 The Regents of The University of Michigan
17  * All rights reserved.
18  *
19  * Redistribution and use in source and binary forms, with or without
20  * modification, are permitted provided that the following conditions are
21  * met: redistributions of source code must retain the above copyright
22  * notice, this list of conditions and the following disclaimer;
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24  * notice, this list of conditions and the following disclaimer in the
25  * documentation and/or other materials provided with the distribution;
26  * neither the name of the copyright holders nor the names of its
27  * contributors may be used to endorse or promote products derived from
28  * this software without specific prior written permission.
29  *
30  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41  */
42 
43 /*
44  * Copyright (c) 1990, 1993 The Regents of the University of California
45  * All rights reserved
46  *
47  * This software was developed by the Computer Systems Engineering group
48  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
49  * contributed to Berkeley.
50  *
51  * All advertising materials mentioning features or use of this software
52  * must display the following acknowledgement:
53  * This product includes software developed by the University of
54  * California, Lawrence Berkeley Laboratories.
55  *
56  * Redistribution and use in source and binary forms, with or without
57  * modification, are permitted provided that the following conditions
58  * are met:
59  * 1. Redistributions of source code must retain the above copyright
60  * notice, this list of conditions and the following disclaimer.
61  * 2. Redistributions in binary form must reproduce the above copyright
62  * notice, this list of conditions and the following disclaimer in the
63  * documentation and/or other materials provided with the distribution.
64  * 3. All advertising materials mentioning features or use of this software
65  * must display the following acknowledgement:
66  * This product includes software developed by the University of
67  * California, Berkeley and its contributors.
68  * 4. Neither the name of the University nor the names of its contributors
69  * may be used to endorse or promote products derived from this software
70  * without specific prior written permission.
71  *
72  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
73  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
74  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
75  * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
76  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
77  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
78  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
79  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
80  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
81  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
82  * SUCH DAMAGE.
83  *
84  * @(#)kgdb_stub.c 8.4 (Berkeley) 1/12/94
85  */
86 
87 /*-
88  * Copyright (c) 2001 The NetBSD Foundation, Inc.
89  * All rights reserved.
90  *
91  * This code is derived from software contributed to The NetBSD Foundation
92  * by Jason R. Thorpe.
93  *
94  * Redistribution and use in source and binary forms, with or without
95  * modification, are permitted provided that the following conditions
96  * are met:
97  * 1. Redistributions of source code must retain the above copyright
98  * notice, this list of conditions and the following disclaimer.
99  * 2. Redistributions in binary form must reproduce the above copyright
100  * notice, this list of conditions and the following disclaimer in the
101  * documentation and/or other materials provided with the distribution.
102  * 3. All advertising materials mentioning features or use of this software
103  * must display the following acknowledgement:
104  * This product includes software developed by the NetBSD
105  * Foundation, Inc. and its contributors.
106  * 4. Neither the name of The NetBSD Foundation nor the names of its
107  * contributors may be used to endorse or promote products derived
108  * from this software without specific prior written permission.
109  *
110  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
111  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
112  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
113  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
114  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
115  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
116  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
117  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
118  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
119  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
120  * POSSIBILITY OF SUCH DAMAGE.
121  */
122 
123 /*
124  * $NetBSD: kgdb_stub.c,v 1.8 2001/07/07 22:58:00 wdk Exp $
125  *
126  * Taken from NetBSD
127  *
128  * "Stub" to allow remote cpu to debug over a serial line using gdb.
129  */
130 
131 #include "arch/arm/remote_gdb.hh"
132 
133 #include <sys/signal.h>
134 #include <unistd.h>
135 
136 #include <string>
137 
138 #include "arch/arm/decoder.hh"
139 #include "arch/arm/pagetable.hh"
140 #include "arch/arm/regs/vec.hh"
141 #include "arch/arm/system.hh"
142 #include "arch/arm/utility.hh"
143 #include "arch/generic/mmu.hh"
144 #include "base/chunk_generator.hh"
145 #include "base/intmath.hh"
146 #include "base/remote_gdb.hh"
147 #include "base/socket.hh"
148 #include "base/trace.hh"
149 #include "blobs/gdb_xml_aarch64_core.hh"
150 #include "blobs/gdb_xml_aarch64_fpu.hh"
151 #include "blobs/gdb_xml_aarch64_target.hh"
152 #include "blobs/gdb_xml_arm_core.hh"
153 #include "blobs/gdb_xml_arm_target.hh"
154 #include "blobs/gdb_xml_arm_vfpv3.hh"
155 #include "cpu/static_inst.hh"
156 #include "cpu/thread_context.hh"
157 #include "cpu/thread_state.hh"
158 #include "debug/GDBAcc.hh"
159 #include "debug/GDBMisc.hh"
160 #include "mem/page_table.hh"
161 #include "mem/physical.hh"
162 #include "mem/port.hh"
163 #include "sim/full_system.hh"
164 #include "sim/system.hh"
165 
166 namespace gem5
167 {
168 
169 using namespace ArmISA;
170 
171 static bool
173 {
174  // Set up a functional memory Request to pass to the TLB
175  // to get it to translate the vaddr to a paddr
176  auto req = std::make_shared<Request>(addr, 64, 0x40, -1, 0, 0);
177 
178  // Check the TLBs for a translation
179  // It's possible that there is a valid translation in the tlb
180  // that is no loger valid in the page table in memory
181  // so we need to check here first
182  //
183  // Calling translateFunctional invokes a table-walk if required
184  // so we should always succeed
185  auto *mmu = tc->getMMUPtr();
186  return mmu->translateFunctional(req, tc, BaseMMU::Read) == NoFault ||
187  mmu->translateFunctional(req, tc, BaseMMU::Execute) == NoFault;
188 }
189 
190 RemoteGDB::RemoteGDB(System *_system, int _port)
191  : BaseRemoteGDB(_system, _port), regCache32(this), regCache64(this)
192 {
193 }
194 
195 /*
196  * Determine if the mapping at va..(va+len) is valid.
197  */
198 bool
200 {
201  if (FullSystem) {
202  for (ChunkGenerator gen(va, len, PageBytes); !gen.done(); gen.next()) {
203  if (!tryTranslate(context(), gen.addr())) {
204  DPRINTF(GDBAcc, "acc: %#x mapping is invalid\n", va);
205  return false;
206  }
207  }
208 
209  DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va);
210  return true;
211  } else {
212  // Check to make sure the first byte is mapped into the processes
213  // address space.
214  return context()->getProcessPtr()->pTable->lookup(va) != nullptr;
215  }
216 }
217 
218 void
220 {
221  DPRINTF(GDBAcc, "getRegs in remotegdb \n");
222 
223  for (int i = 0; i < 31; ++i)
224  r.x[i] = context->readIntReg(INTREG_X0 + i);
225  r.spx = context->readIntReg(INTREG_SPX);
226  r.pc = context->pcState().pc();
228 
229  size_t base = 0;
230  for (int i = 0; i < NumVecV8ArchRegs; i++) {
231  auto v = (context->readVecReg(RegId(VecRegClass, i))).as<VecElem>();
232  for (size_t j = 0; j < NumVecElemPerNeonVecReg; j++) {
233  r.v[base] = v[j];
234  base++;
235  }
236  }
239 }
240 
241 void
243 {
244  DPRINTF(GDBAcc, "setRegs in remotegdb \n");
245 
246  for (int i = 0; i < 31; ++i)
247  context->setIntReg(INTREG_X0 + i, r.x[i]);
248  auto pc_state = context->pcState();
249  pc_state.set(r.pc);
250  context->pcState(pc_state);
252  // Update the stack pointer. This should be done after
253  // updating CPSR/PSTATE since that might affect how SPX gets
254  // mapped.
255  context->setIntReg(INTREG_SPX, r.spx);
256 
257  size_t base = 0;
258  for (int i = 0; i < NumVecV8ArchRegs; i++) {
259  auto v = (context->getWritableVecReg(
260  RegId(VecRegClass, i))).as<VecElem>();
261  for (size_t j = 0; j < NumVecElemPerNeonVecReg; j++) {
262  v[j] = r.v[base];
263  base++;
264  }
265  }
268 }
269 
270 void
272 {
273  DPRINTF(GDBAcc, "getRegs in remotegdb \n");
274 
275  r.gpr[0] = context->readIntReg(INTREG_R0);
276  r.gpr[1] = context->readIntReg(INTREG_R1);
277  r.gpr[2] = context->readIntReg(INTREG_R2);
278  r.gpr[3] = context->readIntReg(INTREG_R3);
279  r.gpr[4] = context->readIntReg(INTREG_R4);
280  r.gpr[5] = context->readIntReg(INTREG_R5);
281  r.gpr[6] = context->readIntReg(INTREG_R6);
282  r.gpr[7] = context->readIntReg(INTREG_R7);
283  r.gpr[8] = context->readIntReg(INTREG_R8);
284  r.gpr[9] = context->readIntReg(INTREG_R9);
285  r.gpr[10] = context->readIntReg(INTREG_R10);
286  r.gpr[11] = context->readIntReg(INTREG_R11);
287  r.gpr[12] = context->readIntReg(INTREG_R12);
288  r.gpr[13] = context->readIntReg(INTREG_SP);
289  r.gpr[14] = context->readIntReg(INTREG_LR);
290  r.gpr[15] = context->pcState().pc();
292 
293  // One day somebody will implement transfer of FPRs correctly.
294  for (int i = 0; i < 32; i++)
295  r.fpr[i] = 0;
296 
298 }
299 
300 void
302 {
303  DPRINTF(GDBAcc, "setRegs in remotegdb \n");
304 
305  context->setIntReg(INTREG_R0, r.gpr[0]);
306  context->setIntReg(INTREG_R1, r.gpr[1]);
307  context->setIntReg(INTREG_R2, r.gpr[2]);
308  context->setIntReg(INTREG_R3, r.gpr[3]);
309  context->setIntReg(INTREG_R4, r.gpr[4]);
310  context->setIntReg(INTREG_R5, r.gpr[5]);
311  context->setIntReg(INTREG_R6, r.gpr[6]);
312  context->setIntReg(INTREG_R7, r.gpr[7]);
313  context->setIntReg(INTREG_R8, r.gpr[8]);
314  context->setIntReg(INTREG_R9, r.gpr[9]);
315  context->setIntReg(INTREG_R10, r.gpr[10]);
316  context->setIntReg(INTREG_R11, r.gpr[11]);
317  context->setIntReg(INTREG_R12, r.gpr[12]);
318  context->setIntReg(INTREG_SP, r.gpr[13]);
319  context->setIntReg(INTREG_LR, r.gpr[14]);
320  auto pc_state = context->pcState();
321  pc_state.set(r.gpr[15]);
322  context->pcState(pc_state);
323 
324  // One day somebody will implement transfer of FPRs correctly.
325 
328 }
329 
330 bool
331 RemoteGDB::getXferFeaturesRead(const std::string &annex, std::string &output)
332 {
333 #define GDB_XML(x, s) \
334  { x, std::string(reinterpret_cast<const char *>(Blobs::s), \
335  Blobs::s ## _len) }
336  static const std::map<std::string, std::string> annexMap32{
337  GDB_XML("target.xml", gdb_xml_arm_target),
338  GDB_XML("arm-core.xml", gdb_xml_arm_core),
339  GDB_XML("arm-vfpv3.xml", gdb_xml_arm_vfpv3),
340  };
341  static const std::map<std::string, std::string> annexMap64{
342  GDB_XML("target.xml", gdb_xml_aarch64_target),
343  GDB_XML("aarch64-core.xml", gdb_xml_aarch64_core),
344  GDB_XML("aarch64-fpu.xml", gdb_xml_aarch64_fpu),
345  };
346 #undef GDB_XML
347  auto& annexMap = inAArch64(context()) ? annexMap64 : annexMap32;
348  auto it = annexMap.find(annex);
349  if (it == annexMap.end())
350  return false;
351  output = it->second;
352  return true;
353 }
354 
357 {
358  if (inAArch64(context()))
359  return &regCache64;
360  else
361  return &regCache32;
362 }
363 
364 } // namespace gem5
gem5::ThreadContext::setIntReg
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::GEM5_PACKED::cpsr
uint32_t cpsr
Definition: remote_gdb.hh:100
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::BaseMMU::Read
@ Read
Definition: mmu.hh:53
socket.hh
thread_state.hh
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::ArmISA::len
Bitfield< 18, 16 > len
Definition: misc_types.hh:444
gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::setRegs
void setRegs(ThreadContext *) const
Set the ThreadContext's registers from the values in the raw buffer.
Definition: remote_gdb.cc:301
gem5::ArmISA::NumVecElemPerNeonVecReg
constexpr unsigned NumVecElemPerNeonVecReg
Definition: vec.hh:56
system.hh
remote_gdb.hh
gem5::output
static void output(const char *filename)
Definition: debug.cc:66
remote_gdb.hh
gem5::ThreadContext::getMMUPtr
virtual BaseMMU * getMMUPtr()=0
gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::GEM5_PACKED::fpsr
uint32_t fpsr
Definition: remote_gdb.hh:102
pagetable.hh
gem5::ArmISA::RemoteGDB::RemoteGDB
RemoteGDB(System *_system, int _port)
Definition: remote_gdb.cc:190
gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::GEM5_PACKED::spx
uint64_t spx
Definition: remote_gdb.hh:98
gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::GEM5_PACKED::pc
uint64_t pc
Definition: remote_gdb.hh:99
vec.hh
gem5::EmulationPageTable::lookup
const Entry * lookup(Addr vaddr)
Lookup function.
Definition: page_table.cc:133
gem5::ArmISA::inAArch64
bool inAArch64(ThreadContext *tc)
Definition: utility.cc:120
gem5::X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
gem5::tryTranslate
static bool tryTranslate(ThreadContext *tc, Addr addr)
Definition: remote_gdb.cc:172
system.hh
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::BaseGdbRegCache
Concrete subclasses of this abstract class represent how the register values are transmitted on the w...
Definition: remote_gdb.hh:85
gem5::BaseMMU::Execute
@ Execute
Definition: mmu.hh:53
gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::setRegs
void setRegs(ThreadContext *) const
Set the ThreadContext's registers from the values in the raw buffer.
Definition: remote_gdb.cc:242
gem5::BaseMMU::translateFunctional
Fault translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode)
Definition: mmu.cc:79
gem5::ChunkGenerator
This class takes an arbitrary memory region (address/length pair) and generates a series of appropria...
Definition: chunk_generator.hh:59
gem5::ThreadContext::readVecReg
virtual const TheISA::VecRegContainer & readVecReg(const RegId &reg) const =0
gem5::ArmISA::j
Bitfield< 24 > j
Definition: misc_types.hh:57
gem5::ArmISA::RemoteGDB::gdbRegs
BaseGdbRegCache * gdbRegs()
Definition: remote_gdb.cc:356
gem5::System
Definition: system.hh:77
gem5::ChunkGenerator::done
bool done() const
Are we done? That is, did the last call to next() advance past the end of the region?
Definition: chunk_generator.hh:141
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Process::pTable
EmulationPageTable * pTable
Definition: process.hh:171
gem5::ArmISA::v
Bitfield< 28 > v
Definition: misc_types.hh:54
gem5::ArmISA::RemoteGDB::acc
bool acc(Addr addr, size_t len)
Definition: remote_gdb.cc:199
gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::getRegs
void getRegs(ThreadContext *)
Fill the raw buffer from the registers in the ThreadContext.
Definition: remote_gdb.cc:219
mmu.hh
port.hh
GDB_XML
#define GDB_XML(x, s)
gem5::ThreadContext::getWritableVecReg
virtual TheISA::VecRegContainer & getWritableVecReg(const RegId &reg)=0
static_inst.hh
gem5::ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::PowerISA::INTREG_LR
@ INTREG_LR
Definition: int.hh:64
gem5::ArmISA::RemoteGDB::regCache64
AArch64GdbRegCache regCache64
Definition: remote_gdb.hh:118
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
gem5::ArmISA::va
Bitfield< 8 > va
Definition: misc_types.hh:275
utility.hh
full_system.hh
gem5::ThreadContext::getProcessPtr
virtual Process * getProcessPtr()=0
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:223
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:60
gem5::ArmISA::RemoteGDB::regCache32
AArch32GdbRegCache regCache32
Definition: remote_gdb.hh:117
gem5::ArmISA::MISCREG_FPSCR
@ MISCREG_FPSCR
Definition: misc.hh:72
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
physical.hh
gem5::ArmISA::NumVecV8ArchRegs
const int NumVecV8ArchRegs
Definition: vec.hh:77
gem5::ArmISA::PageBytes
const Addr PageBytes
Definition: page_size.hh:53
gem5::ArmISA::RemoteGDB::getXferFeaturesRead
bool getXferFeaturesRead(const std::string &annex, std::string &output)
Get an XML target description.
Definition: remote_gdb.cc:331
chunk_generator.hh
gem5::BaseRemoteGDB::context
ThreadContext * context()
Definition: remote_gdb.hh:372
gem5::ArmISA::MISCREG_FPSR
@ MISCREG_FPSR
Definition: misc.hh:622
gem5::MipsISA::r
r
Definition: pra_constants.hh:98
trace.hh
gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::GEM5_PACKED::fpcr
uint32_t fpcr
Definition: remote_gdb.hh:103
gem5::ArmISA::MISCREG_FPCR
@ MISCREG_FPCR
Definition: misc.hh:621
gem5::BaseRemoteGDB
Definition: remote_gdb.hh:48
gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::GEM5_PACKED::x
uint64_t x[31]
Definition: remote_gdb.hh:97
intmath.hh
decoder.hh
page_table.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::r
struct gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::GEM5_PACKED r
thread_context.hh
gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::getRegs
void getRegs(ThreadContext *)
Fill the raw buffer from the registers in the ThreadContext.
Definition: remote_gdb.cc:271
gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::GEM5_PACKED::v
VecElem v[NumVecV8ArchRegs *NumVecElemPerNeonVecReg]
Definition: remote_gdb.hh:101
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0

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