gem5  v21.1.0.2
cfi_mem.cc
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40 
41 #include "mem/cfi_mem.hh"
42 
43 #include <cmath>
44 
45 #include "base/intmath.hh"
46 #include "base/random.hh"
47 #include "base/trace.hh"
48 #include "debug/CFI.hh"
49 #include "debug/Drain.hh"
50 
51 namespace gem5
52 {
53 
54 namespace memory
55 {
56 
57 bool
59 {
60  return locked[blockIdx(block_address)];
61 }
62 
63 void
65 {
66  locked[blockIdx(block_address)] = true;
67 }
68 
69 void
71 {
72  locked[blockIdx(block_address)] = false;
73 }
74 
75 void
77 {
78  SERIALIZE_CONTAINER(locked);
79 }
80 
81 void
83 {
84  UNSERIALIZE_CONTAINER(locked);
85 }
86 
87 uint32_t
89 {
90  return block_address / blockSize;
91 }
92 
93 void
94 CfiMemory::ProgramBuffer::setup(ssize_t buffer_size)
95 {
97  if (buffer_size > MAX_BUFFER_SIZE) {
98  buffer_size = MAX_BUFFER_SIZE;
99  }
100 
101  buffer.resize(buffer_size);
102  std::fill(buffer.begin(), buffer.end(), 0);
103  bytesWritten = 0;
104 }
105 
106 bool
108  void *data_ptr, ssize_t size)
109 {
110  if (bytesWritten >= buffer.size())
111  return true;
112 
113  if (bytesWritten == 0) {
114  blockPointer = flash_address;
115  }
116 
117  const Addr offset = flash_address - blockPointer;
118 
119  if (flash_address < blockPointer || offset >= MAX_BUFFER_SIZE)
120  return true;
121 
122  std::memcpy(buffer.data() + offset, data_ptr, size);
123  bytesWritten += size;
124 
125  return false;
126 }
127 
128 bool
130 {
131  if (parent.blocks.isLocked(blockPointer)) {
132  return false;
133  } else {
134  std::memcpy(parent.toHostAddr(parent.start() + blockPointer),
135  buffer.data(), bytesWritten);
136  return true;
137  }
138 }
139 
140 void
142 {
143  SERIALIZE_CONTAINER(buffer);
144  SERIALIZE_SCALAR(bytesWritten);
145  SERIALIZE_SCALAR(blockPointer);
146 }
147 
148 void
150 {
151  UNSERIALIZE_CONTAINER(buffer);
152  UNSERIALIZE_SCALAR(bytesWritten);
153  UNSERIALIZE_SCALAR(blockPointer);
154 }
155 
156 CfiMemory::CfiMemory(const CfiMemoryParams &p)
157  : AbstractMemory(p),
158  port(name() + ".port", *this), latency(p.latency),
160  retryReq(false), retryResp(false),
161  releaseEvent([this]{ release(); }, name()),
162  dequeueEvent([this]{ dequeue(); }, name()),
163  numberOfChips(2),
164  vendorID(p.vendor_id),
165  deviceID(p.device_id),
166  bankWidth(p.bank_width),
167  readState(CfiCommand::READ_ARRAY), writeState(CfiCommand::NO_CMD),
168  statusRegister(STATUS_READY),
169  blocks(*this, size() / p.blk_size, p.blk_size),
170  programBuffer(*this),
171  cfiQueryTable{
172  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
173  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
174  /* Query-unique ASCII string */
175  'Q', 'R', 'Y',
176  /* Primary Algorithm Command Set and Control = Intel/Sharp */
177  0x01, 0x00,
178  /* Address for Primary Algorithm extended Query */
179  0x31, 0x00,
180  /* Alternative Algorithm Command Set and Control Interface */
181  0x00, 0x00,
182  /* Address for Alternative Algorithm extended Query */
183  0x00, 0x00,
184  /* Vcc Minimum Program/Erase or Write voltage ([7:4].[3-0]V) */
185  0x45,
186  /* Vcc Maximum Program/Erase or Write voltage ([7:4].[3-0]V) */
187  0x55,
188  /* Vpp Minimum Program/Erase voltage (0 = No Vpp pin) */
189  0x00,
190  /* Vpp Minimum Program/Erase voltage (0 = No Vpp pin) */
191  0x00,
192  /* Typical timeout per single byte/word/D-word program: (2^N us) */
193  0x01,
194  /* Typical timeout for maximum-size multi-byte program: (2^N us) */
195  0x01,
196  /* Typical timeout per individual block erase: (2^N ms) */
197  0x01,
198  /* Typical timeout for full chip erase: (2^N ms) */
199  0x00,
200  /* Maximum timeout for byte/word/D-word program (2^N typical) */
201  0x00,
202  /* Maximum timeout for multi-byte program (2^N typical) */
203  0x00,
204  /* Maximum timeout per individual block erase (2^N typical) */
205  0x00,
206  /* Maximum timeout for chip erase (2^N typical) */
207  0x00,
208  /* Device Size in number of bytes (2^N) */
209  static_cast<uint8_t>(log2(size())),
210  /* Flash Device Interface Code description */
211  0x05, 0x00,
212  /* Maximum number of bytes in multi-byte program (2^N) */
213  static_cast<uint8_t>(bits(log2i(ProgramBuffer::MAX_BUFFER_SIZE), 7, 0)),
214  static_cast<uint8_t>(bits(log2i(ProgramBuffer::MAX_BUFFER_SIZE), 15, 8)),
215  /* Number of Erase Block Regions within device */
216  0x01,
217  /* Erase Block Region Information */
218  static_cast<uint8_t>(bits(blocks.number(), 7, 0)),
219  static_cast<uint8_t>(bits(blocks.number(), 15, 8)),
220  static_cast<uint8_t>(bits(blocks.size(), 7, 0)),
221  static_cast<uint8_t>(bits(blocks.size(), 15, 8)),
222  }
223 {}
224 
225 void
227 {
229 
230  // allow unconnected memories as this is used in several ruby
231  // systems at the moment
232  if (port.isConnected()) {
234  }
235 }
236 
237 Tick
239 {
240  panic_if(pkt->cacheResponding(), "Should not see packets where cache "
241  "is responding");
242 
243  cfiAccess(pkt);
244  return getLatency();
245 }
246 
247 Tick
249 {
250  Tick latency = recvAtomic(pkt);
251 
252  if (backdoor.ptr())
253  _backdoor = &backdoor;
254  return latency;
255 }
256 
257 void
259 {
260  pkt->pushLabel(name());
261 
262  functionalAccess(pkt);
263 
264  bool done = false;
265  auto p = packetQueue.begin();
266  // potentially update the packets in our packet queue as well
267  while (!done && p != packetQueue.end()) {
268  done = pkt->trySatisfyFunctional(p->pkt);
269  ++p;
270  }
271 
272  pkt->popLabel();
273 }
274 
275 bool
277 {
278  panic_if(pkt->cacheResponding(), "Should not see packets where cache "
279  "is responding");
280 
281  panic_if(!(pkt->isRead() || pkt->isWrite()),
282  "Should only see read and writes at memory controller, "
283  "saw %s to %#llx\n", pkt->cmdString(), pkt->getAddr());
284 
285  // we should not get a new request after committing to retry the
286  // current one, but unfortunately the CPU violates this rule, so
287  // simply ignore it for now
288  if (retryReq)
289  return false;
290 
291  // if we are busy with a read or write, remember that we have to
292  // retry
293  if (isBusy) {
294  retryReq = true;
295  return false;
296  }
297 
298  // technically the packet only reaches us after the header delay,
299  // and since this is a memory controller we also need to
300  // deserialise the payload before performing any write operation
301  Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
302  pkt->headerDelay = pkt->payloadDelay = 0;
303 
304  // update the release time according to the bandwidth limit, and
305  // do so with respect to the time it takes to finish this request
306  // rather than long term as it is the short term data rate that is
307  // limited for any real memory
308 
309  // calculate an appropriate tick to release to not exceed
310  // the bandwidth limit
311  Tick duration = pkt->getSize() * bandwidth;
312 
313  // only consider ourselves busy if there is any need to wait
314  // to avoid extra events being scheduled for (infinitely) fast
315  // memories
316  if (duration != 0) {
317  schedule(releaseEvent, curTick() + duration);
318  isBusy = true;
319  }
320 
321  // go ahead and deal with the packet and put the response in the
322  // queue if there is one
323  bool needs_response = pkt->needsResponse();
324  recvAtomic(pkt);
325  // turn packet around to go back to requester if response expected
326  if (needs_response) {
327  // recvAtomic() should already have turned packet into
328  // atomic response
329  assert(pkt->isResponse());
330 
331  Tick when_to_send = curTick() + receive_delay + getLatency();
332 
333  // typically this should be added at the end, so start the
334  // insertion sort with the last element, also make sure not to
335  // re-order in front of some existing packet with the same
336  // address, the latter is important as this memory effectively
337  // hands out exclusive copies (shared is not asserted)
338  auto i = packetQueue.end();
339  --i;
340  while (i != packetQueue.begin() && when_to_send < i->tick &&
341  !i->pkt->matchAddr(pkt)) {
342  --i;
343  }
344 
345  // emplace inserts the element before the position pointed to by
346  // the iterator, so advance it one step
347  packetQueue.emplace(++i, pkt, when_to_send);
348 
349  if (!retryResp && !dequeueEvent.scheduled())
350  schedule(dequeueEvent, packetQueue.back().tick);
351  } else {
352  pendingDelete.reset(pkt);
353  }
354 
355  return true;
356 }
357 
358 void
360 {
361  assert(isBusy);
362  isBusy = false;
363  if (retryReq) {
364  retryReq = false;
365  port.sendRetryReq();
366  }
367 }
368 
369 void
371 {
372  assert(!packetQueue.empty());
373  DeferredPacket deferred_pkt = packetQueue.front();
374 
375  retryResp = !port.sendTimingResp(deferred_pkt.pkt);
376 
377  if (!retryResp) {
378  packetQueue.pop_front();
379 
380  // if the queue is not empty, schedule the next dequeue event,
381  // otherwise signal that we are drained if we were asked to do so
382  if (!packetQueue.empty()) {
383  // if there were packets that got in-between then we
384  // already have an event scheduled, so use re-schedule
386  std::max(packetQueue.front().tick, curTick()), true);
387  } else if (drainState() == DrainState::Draining) {
388  DPRINTF(Drain, "Draining of CfiMemory complete\n");
389  signalDrainDone();
390  }
391  }
392 }
393 
394 Tick
396 {
397  return latency +
399 }
400 
401 void
403 {
404  assert(retryResp);
405 
406  dequeue();
407 }
408 
409 Port &
410 CfiMemory::getPort(const std::string &if_name, PortID idx)
411 {
412  if (if_name != "port") {
413  return AbstractMemory::getPort(if_name, idx);
414  } else {
415  return port;
416  }
417 }
418 
421 {
422  if (!packetQueue.empty()) {
423  DPRINTF(Drain, "CfiMemory Queue has requests, waiting to drain\n");
424  return DrainState::Draining;
425  } else {
426  return DrainState::Drained;
427  }
428 }
429 
430 void
432 {
435 
437 
440 }
441 
442 void
444 {
447 
449 
452 }
453 
454 CfiMemory::MemoryPort::MemoryPort(const std::string& _name,
455  CfiMemory& _memory)
456  : ResponsePort(_name, &_memory), mem(_memory)
457 { }
458 
461 {
462  AddrRangeList ranges;
463  ranges.push_back(mem.getAddrRange());
464  return ranges;
465 }
466 
467 Tick
469 {
470  return mem.recvAtomic(pkt);
471 }
472 
473 Tick
475  PacketPtr pkt, MemBackdoorPtr &_backdoor)
476 {
477  return mem.recvAtomicBackdoor(pkt, _backdoor);
478 }
479 
480 void
482 {
483  mem.recvFunctional(pkt);
484 }
485 
486 bool
488 {
489  return mem.recvTimingReq(pkt);
490 }
491 
492 void
494 {
495  mem.recvRespRetry();
496 }
497 
498 void
500 {
501  if (pkt->isWrite()) {
502  write(pkt);
503  } else {
504  read(pkt);
505  }
506 }
507 
508 void
510 {
511  DPRINTF(CFI, "write, address: %#x, val: %#x\n", pkt->getAddr(),
512  pkt->getUintX(ByteOrder::little));
513 
514  const Addr flash_address = pkt->getAddr() - start();
515 
516  const uint16_t value = pkt->getUintX(ByteOrder::little) & 0xffff;
517  const auto new_cmd = static_cast<CfiCommand>(value & 0xff);
518 
519  switch (writeState) {
520  case CfiCommand::NO_CMD:
521  handleCommand(new_cmd);
522  break;
523 
525  if (new_cmd == CfiCommand::BLOCK_ERASE_CONFIRM) {
526  // Erasing the block
527  // Check if block is locked
528  if (blocks.isLocked(flash_address)) {
530  } else {
531  blocks.erase(pkt);
532  }
533  } else {
535  }
538  break;
539 
541  if (new_cmd == CfiCommand::LOCK_BLOCK) {
542 
543  // Lock the addressed block
544  blocks.lock(flash_address);
546 
547  } else if (new_cmd == CfiCommand::UNLOCK_BLOCK) {
548 
549  // Unlock the addressed block
550  blocks.unlock(flash_address);
552 
553  } else {
555  }
556 
558  break;
559 
563 
564  if (blocks.isLocked(flash_address)) {
566  } else {
568  return;
569  }
570  break;
571 
573  // Buffer size in bytes
574  auto buffer_size = (value + 1) * sizeof(uint32_t);
575 
576  // Clearing the program buffer
577  programBuffer.setup(buffer_size);
578 
581  break;
582  }
583 
585  // Write to the buffer and check if a writeback is needed
586  // (if the buffer is full)
588  flash_address, pkt->getPtr<void>(), pkt->getSize());
589 
590  if (writeback) {
591  if (new_cmd == CfiCommand::BUFFERED_PROGRAM_CONFIRM) {
592  auto success = programBuffer.writeback();
593  if (!success)
595 
597  } else {
599  }
601  }
602  break;
603  }
604 
605  default:
606  panic("Invalid Write State\n");
607  return;
608  }
609 
610  pkt->makeResponse();
611 }
612 
613 void
615 {
616  const Addr flash_address = pkt->getAddr() - start();
617  uint64_t value = 0;
618 
619  switch (readState) {
621  value = statusRegister;
622  break;
624  value = readDeviceID(flash_address);
625  break;
627  value = cfiQuery(flash_address);
628  break;
631  return;
632  default:
633  panic("Invalid Read State\n");
634  return;
635  }
636 
637  if (numberOfChips == 2) {
638  value |= (value << 16);
639  }
640 
641  pkt->setUintX(value, ByteOrder::little);
642  pkt->makeResponse();
643 
644  DPRINTF(CFI, "read, address: %#x, val: %#x\n", pkt->getAddr(),
645  pkt->getUintX(ByteOrder::little));
646 
647 }
648 
649 uint64_t
650 CfiMemory::readDeviceID(Addr flash_address) const
651 {
652  switch ((flash_address & 0xff) / bankWidth) {
653  case 0x00: // vendor ID
654  return vendorID;
655  case 0x01: // device ID
656  return deviceID;
657  case 0x02: // lock bit
658  return blocks.isLocked(flash_address);
659  default:
660  // Unsupported entries
661  warn("Invalid Device Identifier code: %d\n", flash_address & 0xff);
662  return 0;
663  }
664 }
665 
666 void
668 {
669  switch (new_cmd) {
671  DPRINTF(CFI, "CFI Command: Read Array\n");
673  break;
675  DPRINTF(CFI, "CFI Command: Read Device Identifier\n");
677  break;
679  DPRINTF(CFI, "CFI Command: CFI Query\n");
681  break;
683  DPRINTF(CFI, "CFI Command: Read Status Register\n");
685  break;
687  DPRINTF(CFI, "CFI Command: Clear Status Register\n");
689  break;
691  DPRINTF(CFI, "CFI Command: Buffered Program Confirm\n");
692  break;
694  DPRINTF(CFI, "CFI Command: Erase Block Setup\n");
697  break;
699  DPRINTF(CFI, "CFI Command: Lock Block Setup\n");
701  break;
703  DPRINTF(CFI, "CFI Command: Word Program\n");
706  break;
708  DPRINTF(CFI, "CFI Command: Buffered Program Setup\n");
711  break;
712  default:
713  panic("Don't know what to do with %#x\n",
714  static_cast<uint16_t>(new_cmd));
715  }
716 
717 }
718 
719 uint64_t
720 CfiMemory::cfiQuery(Addr flash_address)
721 {
722  flash_address /= bankWidth;
723 
724  panic_if(flash_address >= sizeof(cfiQueryTable),
725  "Acessing invalid entry in CFI query table (addr=%#x)",
726  flash_address);
727 
728  return cfiQueryTable[flash_address];
729 }
730 
731 void
733 {
734  auto host_address = parent.toHostAddr(pkt->getAddr());
735  std::memset(host_address, 0xff, blockSize);
736 }
737 
738 } // namespace memory
739 } // namespace gem5
gem5::memory::CfiMemory::pendingDelete
std::unique_ptr< Packet > pendingDelete
Upstream caches need this packet until true is returned, so hold it for deletion until a subsequent c...
Definition: cfi_mem.hh:328
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::memory::CfiMemory::isBusy
bool isBusy
Track the state of the memory as either idle or busy, no need for an enum with only two states.
Definition: cfi_mem.hh:287
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::Packet::cmdString
const std::string & cmdString() const
Return the string name of the cmd field (for debugging and tracing).
Definition: packet.hh:577
gem5::memory::CfiMemory::drain
DrainState drain() override
Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are pa...
Definition: cfi_mem.cc:420
gem5::MipsISA::fill
fill
Definition: pra_constants.hh:57
gem5::SimObject::getPort
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
Definition: sim_object.cc:126
UNSERIALIZE_OBJ
#define UNSERIALIZE_OBJ(obj)
Definition: serialize.hh:655
gem5::memory::CfiMemory::CfiCommand::WORD_PROGRAM
@ WORD_PROGRAM
warn
#define warn(...)
Definition: logging.hh:245
gem5::memory::CfiMemory::programBuffer
ProgramBuffer programBuffer
Definition: cfi_mem.hh:344
gem5::memory::CfiMemory::writeState
CfiCommand writeState
Definition: cfi_mem.hh:338
gem5::memory::CfiMemory::readState
CfiCommand readState
Previous command (issued in the previous write cycle)
Definition: cfi_mem.hh:337
gem5::memory::CfiMemory::write
void write(PacketPtr pkt)
Write request to the CFI Memory.
Definition: cfi_mem.cc:509
gem5::memory::CfiMemory::DeferredPacket
A deferred packet stores a packet along with its scheduled transmission time.
Definition: cfi_mem.hh:226
gem5::Packet::getUintX
uint64_t getUintX(ByteOrder endian) const
Get the data in the packet byte swapped from the specified endianness and zero-extended to 64 bits.
Definition: packet.cc:334
gem5::memory::CfiMemory::read
void read(PacketPtr pkt)
Read request to the CFI Memory.
Definition: cfi_mem.cc:614
gem5::memory::CfiMemory::dequeue
void dequeue()
Dequeue a packet from our internal packet queue and move it to the port where it will be sent as soon...
Definition: cfi_mem.cc:370
gem5::ResponsePort::sendRetryReq
void sendRetryReq()
Send a retry to the request port that previously attempted a sendTimingReq to this response port and ...
Definition: port.hh:401
gem5::memory::CfiMemory::BlockData::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: cfi_mem.cc:82
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::memory::CfiMemory::recvAtomicBackdoor
Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &_backdoor)
Definition: cfi_mem.cc:248
gem5::Drainable::drainState
DrainState drainState() const
Return the current drain state of an object.
Definition: drain.hh:324
gem5::memory::CfiMemory::numberOfChips
const uint8_t numberOfChips
Definition: cfi_mem.hh:330
memory
Definition: mem.h:38
UNSERIALIZE_CONTAINER
#define UNSERIALIZE_CONTAINER(member)
Definition: serialize.hh:634
gem5::ArmISA::writeback
Bitfield< 21 > writeback
Definition: types.hh:126
gem5::memory::CfiMemory::MemoryPort::recvTimingReq
bool recvTimingReq(PacketPtr pkt) override
Receive a timing request from the peer.
Definition: cfi_mem.cc:487
gem5::memory::CfiMemory::ProgramBuffer::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: cfi_mem.cc:149
gem5::memory::CfiMemory::releaseEvent
EventFunctionWrapper releaseEvent
Definition: cfi_mem.hh:307
gem5::memory::CfiMemory::cfiQueryTable
uint8_t cfiQueryTable[49]
Definition: cfi_mem.hh:346
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::memory::CfiMemory::recvRespRetry
void recvRespRetry()
Definition: cfi_mem.cc:402
gem5::memory::CfiMemory::getLatency
Tick getLatency() const
Detemine the latency.
Definition: cfi_mem.cc:395
gem5::memory::CfiMemory::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: cfi_mem.cc:410
gem5::SimObject::init
virtual void init()
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: sim_object.cc:76
random.hh
gem5::memory::CfiMemory::CfiCommand::READ_ARRAY
@ READ_ARRAY
gem5::Packet::cacheResponding
bool cacheResponding() const
Definition: packet.hh:646
gem5::Packet::isWrite
bool isWrite() const
Definition: packet.hh:583
gem5::memory::CfiMemory::MemoryPort::recvAtomicBackdoor
Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &_backdoor) override
Receive an atomic request packet from the peer, and optionally provide a backdoor to the data being a...
Definition: cfi_mem.cc:474
gem5::memory::CfiMemory::MemoryPort::recvFunctional
void recvFunctional(PacketPtr pkt) override
Receive a functional request packet from the peer.
Definition: cfi_mem.cc:481
gem5::log2i
static constexpr int log2i(int value)
Calculate the log2 of a power of 2 integer.
Definition: intmath.hh:295
gem5::EventManager::schedule
void schedule(Event &event, Tick when)
Definition: eventq.hh:1019
gem5::memory::CfiMemory::port
MemoryPort port
Definition: cfi_mem.hh:256
gem5::memory::CfiMemory::CfiCommand::LOCK_BLOCK_SETUP
@ LOCK_BLOCK_SETUP
gem5::memory::CfiMemory::CfiCommand::UNLOCK_BLOCK
@ UNLOCK_BLOCK
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::Packet::headerDelay
uint32_t headerDelay
The extra delay from seeing the packet until the header is transmitted.
Definition: packet.hh:420
gem5::memory::CfiMemory::cfiQuery
uint64_t cfiQuery(Addr addr)
Return the selected entry in the CFI table.
Definition: cfi_mem.cc:720
gem5::memory::CfiMemory::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: cfi_mem.cc:226
gem5::memory::CfiMemory::CfiCommand::BUFFER_SIZE_READ
@ BUFFER_SIZE_READ
This is not a real command, but it is used by the internal model only to represent the 2nd write cycl...
gem5::memory::CfiMemory::bandwidth
const double bandwidth
Bandwidth in ticks per byte.
Definition: cfi_mem.hh:281
gem5::memory::CfiMemory::BlockData::blockIdx
uint32_t blockIdx(Addr block_address) const
Definition: cfi_mem.cc:88
SERIALIZE_ENUM
#define SERIALIZE_ENUM(scalar)
Definition: serialize.hh:591
gem5::Packet::payloadDelay
uint32_t payloadDelay
The extra pipelining delay from seeing the packet until the end of payload is transmitted by the comp...
Definition: packet.hh:438
gem5::memory::CfiMemory::STATUS_LOCK_ERROR
static const uint8_t STATUS_LOCK_ERROR
Definition: cfi_mem.hh:99
gem5::memory::CfiMemory::CfiCommand::NO_CMD
@ NO_CMD
gem5::DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:74
gem5::memory::CfiMemory::CfiCommand::CLEAR_STATUS_REG
@ CLEAR_STATUS_REG
gem5::Packet::isRead
bool isRead() const
Definition: packet.hh:582
gem5::memory::AbstractMemory::start
Addr start() const
Get the start address.
Definition: abstract_mem.hh:308
gem5::memory::CfiMemory::ProgramBuffer::setup
void setup(ssize_t buffer_size)
Start buffering.
Definition: cfi_mem.cc:94
gem5::Random::random
std::enable_if_t< std::is_integral< T >::value, T > random()
Use the SFINAE idiom to choose an implementation based on whether the type is integral or floating po...
Definition: random.hh:90
gem5::memory::AbstractMemory::functionalAccess
void functionalAccess(PacketPtr pkt)
Perform an untimed memory read or write without changing anything but the memory itself.
Definition: abstract_mem.cc:482
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::memory::CfiMemory::CfiCommand::LOCK_BLOCK
@ LOCK_BLOCK
gem5::memory::CfiMemory::CfiCommand::BUFFERED_PROGRAM_SETUP
@ BUFFERED_PROGRAM_SETUP
gem5::memory::CfiMemory::STATUS_ERASE_ERROR
static const uint8_t STATUS_ERASE_ERROR
Possible in the status register.
Definition: cfi_mem.hh:98
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
SERIALIZE_OBJ
#define SERIALIZE_OBJ(obj)
Definition: serialize.hh:648
gem5::memory::CfiMemory::MemoryPort::getAddrRanges
AddrRangeList getAddrRanges() const override
Get a list of the non-overlapping address ranges the owner is responsible for.
Definition: cfi_mem.cc:460
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::memory::AbstractMemory
An abstract memory represents a contiguous block of physical memory, with an associated address range...
Definition: abstract_mem.hh:110
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::memory::CfiMemory::latency_var
const Tick latency_var
Fudge factor added to the latency.
Definition: cfi_mem.hh:267
gem5::memory::CfiMemory::ProgramBuffer::writeback
bool writeback()
Definition: cfi_mem.cc:129
gem5::memory::CfiMemory::STATUS_READY
static const uint8_t STATUS_READY
Definition: cfi_mem.hh:100
gem5::memory::CfiMemory::MemoryPort::MemoryPort
MemoryPort(const std::string &_name, CfiMemory &_memory)
Definition: cfi_mem.cc:454
gem5::memory::CfiMemory
CfiMemory: This is modelling a flash memory adhering to the Common Flash Interface (CFI):
Definition: cfi_mem.hh:71
gem5::ResponsePort::sendTimingResp
bool sendTimingResp(PacketPtr pkt)
Attempt to send a timing response to the request port by calling its corresponding receive function.
Definition: port.hh:370
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::memory::CfiMemory::ProgramBuffer::write
bool write(Addr flash_address, void *data_ptr, ssize_t size)
Write data into the buffer.
Definition: cfi_mem.cc:107
gem5::memory::CfiMemory::packetQueue
std::list< DeferredPacket > packetQueue
Internal (unbounded) storage to mimic the delay caused by the actual memory access.
Definition: cfi_mem.hh:274
gem5::memory::CfiMemory::blocks
BlockData blocks
Definition: cfi_mem.hh:342
gem5::EventManager::reschedule
void reschedule(Event &event, Tick when, bool always=false)
Definition: eventq.hh:1037
gem5::memory::CfiMemory::CfiCommand::BUFFERED_PROGRAM_CONFIRM
@ BUFFERED_PROGRAM_CONFIRM
gem5::memory::CfiMemory::retryReq
bool retryReq
Remember if we have to retry an outstanding request that arrived while we were busy.
Definition: cfi_mem.hh:293
gem5::memory::CfiMemory::cfiAccess
void cfiAccess(PacketPtr pkt)
Make a read/write access to the CFI Memory.
Definition: cfi_mem.cc:499
gem5::Port::isConnected
bool isConnected() const
Is this port currently connected to a peer?
Definition: port.hh:133
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::memory::CfiMemory::CfiCommand::READ_DEVICE_ID
@ READ_DEVICE_ID
gem5::DrainState::Drained
@ Drained
Buffers drained, ready for serialization/handover.
gem5::memory::CfiMemory::CfiCommand::BLOCK_ERASE_CONFIRM
@ BLOCK_ERASE_CONFIRM
gem5::Packet::pushLabel
void pushLabel(const std::string &lbl)
Push label for PrintReq (safe to call unconditionally).
Definition: packet.hh:1420
gem5::memory::CfiMemory::BlockData::erase
void erase(PacketPtr pkt)
Erase a single block.
Definition: cfi_mem.cc:732
gem5::memory::CfiMemory::CfiMemory
CfiMemory(const CfiMemoryParams &p)
Definition: cfi_mem.cc:156
gem5::memory::CfiMemory::dequeueEvent
EventFunctionWrapper dequeueEvent
Definition: cfi_mem.hh:315
gem5::Packet::popLabel
void popLabel()
Pop label for PrintReq (safe to call unconditionally).
Definition: packet.hh:1430
gem5::Packet::needsResponse
bool needsResponse() const
Definition: packet.hh:597
gem5::memory::CfiMemory::CfiCommand::READ_CFI_QUERY
@ READ_CFI_QUERY
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::memory::CfiMemory::ProgramBuffer::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: cfi_mem.cc:141
name
const std::string & name()
Definition: trace.cc:49
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
gem5::MemBackdoor
Definition: backdoor.hh:41
gem5::ResponsePort::sendRangeChange
void sendRangeChange() const
Called by the owner to send a range change.
Definition: port.hh:296
gem5::memory::CfiMemory::recvTimingReq
bool recvTimingReq(PacketPtr pkt)
Definition: cfi_mem.cc:276
gem5::memory::CfiMemory::STATUS_PROGRAM_LOCK_BIT
static const uint8_t STATUS_PROGRAM_LOCK_BIT
Definition: cfi_mem.hh:101
gem5::Drainable::signalDrainDone
void signalDrainDone() const
Signal that an object is drained.
Definition: drain.hh:305
gem5::memory::AbstractMemory::size
uint64_t size() const
Get the memory size.
Definition: abstract_mem.hh:301
gem5::ResponsePort
A ResponsePort is a specialization of a port.
Definition: port.hh:268
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::memory::CfiMemory::readDeviceID
uint64_t readDeviceID(Addr flash_address) const
Helper function to read the device identifier after the read state machine is put in the CfiCommand::...
Definition: cfi_mem.cc:650
gem5::memory::CfiMemory::BlockData::locked
std::vector< bool > locked
Definition: cfi_mem.hh:161
gem5::memory::CfiMemory::BlockData::unlock
void unlock(Addr block_address)
Unlock the block pointed by the block_address parameter.
Definition: cfi_mem.cc:70
gem5::memory::CfiMemory::recvAtomic
Tick recvAtomic(PacketPtr pkt)
Definition: cfi_mem.cc:238
gem5::MemBackdoor::ptr
uint8_t * ptr() const
Definition: backdoor.hh:62
gem5::memory::CfiMemory::release
void release()
Release the memory after being busy and send a retry if a request was rejected in the meanwhile.
Definition: cfi_mem.cc:359
gem5::memory::CfiMemory::MemoryPort::recvRespRetry
void recvRespRetry() override
Called by the peer if sendTimingResp was called on this protocol (causing recvTimingResp to be called...
Definition: cfi_mem.cc:493
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::memory::CfiMemory::MemoryPort::recvAtomic
Tick recvAtomic(PacketPtr pkt) override
Receive an atomic request packet from the peer.
Definition: cfi_mem.cc:468
gem5::memory::AbstractMemory::backdoor
MemBackdoor backdoor
Definition: abstract_mem.hh:121
SERIALIZE_CONTAINER
#define SERIALIZE_CONTAINER(member)
Definition: serialize.hh:626
gem5::memory::CfiMemory::CfiCommand::ERASE_BLOCK_SETUP
@ ERASE_BLOCK_SETUP
gem5::Packet::makeResponse
void makeResponse()
Take a request packet and modify it in place to be suitable for returning as a response to that reque...
Definition: packet.hh:1031
gem5::memory::CfiMemory::CfiCommand::READ_STATUS_REG
@ READ_STATUS_REG
gem5::Clocked::tick
Tick tick
Definition: clocked_object.hh:68
gem5::memory::CfiMemory::deviceID
const uint16_t deviceID
Definition: cfi_mem.hh:333
gem5::memory::CfiMemory::vendorID
const uint16_t vendorID
Definition: cfi_mem.hh:332
gem5::Packet::trySatisfyFunctional
bool trySatisfyFunctional(PacketPtr other)
Check a functional request against a memory value stored in another packet (i.e.
Definition: packet.hh:1358
cfi_mem.hh
gem5::memory::CfiMemory::BlockData::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: cfi_mem.cc:76
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
mem
bool_vector8 mem[]
Definition: reset_stim.h:43
gem5::memory::CfiMemory::BlockData::isLocked
bool isLocked(Addr block_address) const
Return true if the block pointed by the block_address parameter is locked.
Definition: cfi_mem.cc:58
UNSERIALIZE_ENUM
#define UNSERIALIZE_ENUM(scalar)
Definition: serialize.hh:598
gem5::memory::CfiMemory::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: cfi_mem.cc:443
trace.hh
std::list< AddrRange >
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
intmath.hh
gem5::memory::CfiMemory::latency
const Tick latency
Latency from that a request is accepted until the response is ready to be sent.
Definition: cfi_mem.hh:262
gem5::memory::CfiMemory::DeferredPacket::pkt
const PacketPtr pkt
Definition: cfi_mem.hh:232
gem5::memory::AbstractMemory::access
void access(PacketPtr pkt)
Perform an untimed memory access and update all the state (e.g.
Definition: abstract_mem.cc:380
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::Packet::setUintX
void setUintX(uint64_t w, ByteOrder endian)
Set the value in the word w after truncating it to the length of the packet and then byteswapping it ...
Definition: packet.cc:351
gem5::random_mt
Random random_mt
Definition: random.cc:99
gem5::memory::CfiMemory::CfiCommand
CfiCommand
Definition: cfi_mem.hh:74
gem5::memory::CfiMemory::statusRegister
uint8_t statusRegister
Definition: cfi_mem.hh:340
gem5::memory::CfiMemory::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: cfi_mem.cc:431
gem5::memory::CfiMemory::recvFunctional
void recvFunctional(PacketPtr pkt)
Definition: cfi_mem.cc:258
gem5::Packet::isResponse
bool isResponse() const
Definition: packet.hh:587
gem5::Packet::getSize
unsigned getSize() const
Definition: packet.hh:791
gem5::DrainState::Draining
@ Draining
Draining buffers pending serialization/handover.
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
gem5::memory::CfiMemory::bankWidth
const uint16_t bankWidth
Definition: cfi_mem.hh:334
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::memory::CfiMemory::BlockData::lock
void lock(Addr block_address)
Lock the block pointed by the block_address parameter.
Definition: cfi_mem.cc:64
gem5::Packet::getPtr
T * getPtr()
get a pointer to the data ptr.
Definition: packet.hh:1184
gem5::memory::CfiMemory::handleCommand
void handleCommand(CfiCommand command)
Service a new command issued to the flash device.
Definition: cfi_mem.cc:667
gem5::memory::CfiMemory::retryResp
bool retryResp
Remember if we failed to send a response and are awaiting a retry.
Definition: cfi_mem.hh:299

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