gem5  v21.1.0.2
abstract_mem.cc
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40 
41 #include "mem/abstract_mem.hh"
42 
43 #include <vector>
44 
45 #include "arch/locked_mem.hh"
48 #include "cpu/thread_context.hh"
49 #include "debug/LLSC.hh"
50 #include "debug/MemoryAccess.hh"
51 #include "mem/packet_access.hh"
52 #include "sim/system.hh"
53 
54 namespace gem5
55 {
56 
57 namespace memory
58 {
59 
61  ClockedObject(p), range(p.range), pmemAddr(NULL),
62  backdoor(params().range, nullptr,
63  (MemBackdoor::Flags)(MemBackdoor::Readable |
64  MemBackdoor::Writeable)),
65  confTableReported(p.conf_table_reported), inAddrMap(p.in_addr_map),
66  kvmMap(p.kvm_map), _system(NULL),
67  stats(*this)
68 {
69  panic_if(!range.valid() || !range.size(),
70  "Memory range %s must be valid with non-zero size.",
71  range.to_string());
72 }
73 
74 void
76 {
78 
79  const auto &file = params().image_file;
80  if (file == "")
81  return;
82 
83  auto *object = loader::createObjectFile(file, true);
84  fatal_if(!object, "%s: Could not load %s.", name(), file);
85 
86  loader::debugSymbolTable.insert(*object->symtab().globals());
87  loader::MemoryImage image = object->buildImage();
88 
89  AddrRange image_range(image.minAddr(), image.maxAddr());
90  if (!range.contains(image_range.start())) {
91  warn("%s: Moving image from %s to memory address range %s.",
92  name(), image_range.to_string(), range.to_string());
93  image = image.offset(range.start());
94  image_range = AddrRange(image.minAddr(), image.maxAddr());
95  }
96  panic_if(!image_range.isSubset(range), "%s: memory image %s doesn't fit.",
97  name(), file);
98 
99  PortProxy proxy([this](PacketPtr pkt) { functionalAccess(pkt); },
100  system()->cacheLineSize());
101 
102  panic_if(!image.write(proxy), "%s: Unable to write image.");
103 }
104 
105 void
107 {
108  // If there was an existing backdoor, let everybody know it's going away.
109  if (backdoor.ptr())
111 
112  // The back door can't handle interleaved memory.
113  backdoor.ptr(range.interleaved() ? nullptr : pmem_addr);
114 
115  pmemAddr = pmem_addr;
116 }
117 
119  : statistics::Group(&_mem), mem(_mem),
120  ADD_STAT(bytesRead, statistics::units::Byte::get(),
121  "Number of bytes read from this memory"),
122  ADD_STAT(bytesInstRead, statistics::units::Byte::get(),
123  "Number of instructions bytes read from this memory"),
124  ADD_STAT(bytesWritten, statistics::units::Byte::get(),
125  "Number of bytes written to this memory"),
126  ADD_STAT(numReads, statistics::units::Count::get(),
127  "Number of read requests responded to by this memory"),
128  ADD_STAT(numWrites, statistics::units::Count::get(),
129  "Number of write requests responded to by this memory"),
130  ADD_STAT(numOther, statistics::units::Count::get(),
131  "Number of other requests responded to by this memory"),
132  ADD_STAT(bwRead, statistics::units::Rate<
133  statistics::units::Byte, statistics::units::Second>::get(),
134  "Total read bandwidth from this memory"),
135  ADD_STAT(bwInstRead,
136  statistics::units::Rate<
137  statistics::units::Byte, statistics::units::Second>::get(),
138  "Instruction read bandwidth from this memory"),
139  ADD_STAT(bwWrite, statistics::units::Rate<
140  statistics::units::Byte, statistics::units::Second>::get(),
141  "Write bandwidth from this memory"),
142  ADD_STAT(bwTotal, statistics::units::Rate<
143  statistics::units::Byte, statistics::units::Second>::get(),
144  "Total bandwidth to/from this memory")
145 {
146 }
147 
148 void
150 {
151  using namespace statistics;
152 
154 
155  System *sys = mem.system();
156  assert(sys);
157  const auto max_requestors = sys->maxRequestors();
158 
159  bytesRead
160  .init(max_requestors)
161  .flags(total | nozero | nonan)
162  ;
163  for (int i = 0; i < max_requestors; i++) {
164  bytesRead.subname(i, sys->getRequestorName(i));
165  }
166 
167  bytesInstRead
168  .init(max_requestors)
169  .flags(total | nozero | nonan)
170  ;
171  for (int i = 0; i < max_requestors; i++) {
172  bytesInstRead.subname(i, sys->getRequestorName(i));
173  }
174 
175  bytesWritten
176  .init(max_requestors)
177  .flags(total | nozero | nonan)
178  ;
179  for (int i = 0; i < max_requestors; i++) {
180  bytesWritten.subname(i, sys->getRequestorName(i));
181  }
182 
183  numReads
184  .init(max_requestors)
185  .flags(total | nozero | nonan)
186  ;
187  for (int i = 0; i < max_requestors; i++) {
188  numReads.subname(i, sys->getRequestorName(i));
189  }
190 
191  numWrites
192  .init(max_requestors)
193  .flags(total | nozero | nonan)
194  ;
195  for (int i = 0; i < max_requestors; i++) {
196  numWrites.subname(i, sys->getRequestorName(i));
197  }
198 
199  numOther
200  .init(max_requestors)
201  .flags(total | nozero | nonan)
202  ;
203  for (int i = 0; i < max_requestors; i++) {
204  numOther.subname(i, sys->getRequestorName(i));
205  }
206 
207  bwRead
208  .precision(0)
209  .prereq(bytesRead)
210  .flags(total | nozero | nonan)
211  ;
212  for (int i = 0; i < max_requestors; i++) {
213  bwRead.subname(i, sys->getRequestorName(i));
214  }
215 
216  bwInstRead
217  .precision(0)
218  .prereq(bytesInstRead)
219  .flags(total | nozero | nonan)
220  ;
221  for (int i = 0; i < max_requestors; i++) {
222  bwInstRead.subname(i, sys->getRequestorName(i));
223  }
224 
225  bwWrite
226  .precision(0)
227  .prereq(bytesWritten)
228  .flags(total | nozero | nonan)
229  ;
230  for (int i = 0; i < max_requestors; i++) {
231  bwWrite.subname(i, sys->getRequestorName(i));
232  }
233 
234  bwTotal
235  .precision(0)
236  .prereq(bwTotal)
237  .flags(total | nozero | nonan)
238  ;
239  for (int i = 0; i < max_requestors; i++) {
240  bwTotal.subname(i, sys->getRequestorName(i));
241  }
242 
243  bwRead = bytesRead / simSeconds;
244  bwInstRead = bytesInstRead / simSeconds;
245  bwWrite = bytesWritten / simSeconds;
246  bwTotal = (bytesRead + bytesWritten) / simSeconds;
247 }
248 
249 AddrRange
251 {
252  return range;
253 }
254 
255 // Add load-locked to tracking list. Should only be called if the
256 // operation is a load and the LLSC flag is set.
257 void
259 {
260  const RequestPtr &req = pkt->req;
261  Addr paddr = LockedAddr::mask(req->getPaddr());
262 
263  // first we check if we already have a locked addr for this
264  // xc. Since each xc only gets one, we just update the
265  // existing record with the new address.
267 
268  for (i = lockedAddrList.begin(); i != lockedAddrList.end(); ++i) {
269  if (i->matchesContext(req)) {
270  DPRINTF(LLSC, "Modifying lock record: context %d addr %#x\n",
271  req->contextId(), paddr);
272  i->addr = paddr;
273  return;
274  }
275  }
276 
277  // no record for this xc: need to allocate a new one
278  DPRINTF(LLSC, "Adding lock record: context %d addr %#x\n",
279  req->contextId(), paddr);
280  lockedAddrList.push_front(LockedAddr(req));
282 }
283 
284 
285 // Called on *writes* only... both regular stores and
286 // store-conditional operations. Check for conventional stores which
287 // conflict with locked addresses, and for success/failure of store
288 // conditionals.
289 bool
291 {
292  const RequestPtr &req = pkt->req;
293  Addr paddr = LockedAddr::mask(req->getPaddr());
294  bool isLLSC = pkt->isLLSC();
295 
296  // Initialize return value. Non-conditional stores always
297  // succeed. Assume conditional stores will fail until proven
298  // otherwise.
299  bool allowStore = !isLLSC;
300 
301  // Iterate over list. Note that there could be multiple matching records,
302  // as more than one context could have done a load locked to this location.
303  // Only remove records when we succeed in finding a record for (xc, addr);
304  // then, remove all records with this address. Failed store-conditionals do
305  // not blow unrelated reservations.
307 
308  if (isLLSC) {
309  while (i != lockedAddrList.end()) {
310  if (i->addr == paddr && i->matchesContext(req)) {
311  // it's a store conditional, and as far as the memory system can
312  // tell, the requesting context's lock is still valid.
313  DPRINTF(LLSC, "StCond success: context %d addr %#x\n",
314  req->contextId(), paddr);
315  allowStore = true;
316  break;
317  }
318  // If we didn't find a match, keep searching! Someone else may well
319  // have a reservation on this line here but we may find ours in just
320  // a little while.
321  i++;
322  }
323  req->setExtraData(allowStore ? 1 : 0);
324  }
325  // LLSCs that succeeded AND non-LLSC stores both fall into here:
326  if (allowStore) {
327  // We write address paddr. However, there may be several entries with a
328  // reservation on this address (for other contextIds) and they must all
329  // be removed.
330  i = lockedAddrList.begin();
331  while (i != lockedAddrList.end()) {
332  if (i->addr == paddr) {
333  DPRINTF(LLSC, "Erasing lock record: context %d addr %#x\n",
334  i->contextId, paddr);
335  ContextID owner_cid = i->contextId;
336  assert(owner_cid != InvalidContextID);
337  ContextID requestor_cid = req->hasContextId() ?
338  req->contextId() :
340  if (owner_cid != requestor_cid) {
341  ThreadContext* ctx = system()->threads[owner_cid];
343  }
344  i = lockedAddrList.erase(i);
345  } else {
346  i++;
347  }
348  }
349  }
350 
351  return allowStore;
352 }
353 
354 #if TRACING_ON
355 static inline void
356 tracePacket(System *sys, const char *label, PacketPtr pkt)
357 {
358  int size = pkt->getSize();
359  if (size == 1 || size == 2 || size == 4 || size == 8) {
360  ByteOrder byte_order = sys->getGuestByteOrder();
361  DPRINTF(MemoryAccess, "%s from %s of size %i on address %#x data "
362  "%#x %c\n", label, sys->getRequestorName(pkt->req->
363  requestorId()), size, pkt->getAddr(),
364  pkt->getUintX(byte_order),
365  pkt->req->isUncacheable() ? 'U' : 'C');
366  return;
367  }
368  DPRINTF(MemoryAccess, "%s from %s of size %i on address %#x %c\n",
369  label, sys->getRequestorName(pkt->req->requestorId()),
370  size, pkt->getAddr(), pkt->req->isUncacheable() ? 'U' : 'C');
371  DDUMP(MemoryAccess, pkt->getConstPtr<uint8_t>(), pkt->getSize());
372 }
373 
374 # define TRACE_PACKET(A) tracePacket(system(), A, pkt)
375 #else
376 # define TRACE_PACKET(A)
377 #endif
378 
379 void
381 {
382  if (pkt->cacheResponding()) {
383  DPRINTF(MemoryAccess, "Cache responding to %#llx: not responding\n",
384  pkt->getAddr());
385  return;
386  }
387 
388  if (pkt->cmd == MemCmd::CleanEvict || pkt->cmd == MemCmd::WritebackClean) {
389  DPRINTF(MemoryAccess, "CleanEvict on 0x%x: not responding\n",
390  pkt->getAddr());
391  return;
392  }
393 
394  assert(pkt->getAddrRange().isSubset(range));
395 
396  uint8_t *host_addr = toHostAddr(pkt->getAddr());
397 
398  if (pkt->cmd == MemCmd::SwapReq) {
399  if (pkt->isAtomicOp()) {
400  if (pmemAddr) {
401  pkt->setData(host_addr);
402  (*(pkt->getAtomicOp()))(host_addr);
403  }
404  } else {
405  std::vector<uint8_t> overwrite_val(pkt->getSize());
406  uint64_t condition_val64;
407  uint32_t condition_val32;
408 
409  panic_if(!pmemAddr, "Swap only works if there is real memory " \
410  "(i.e. null=False)");
411 
412  bool overwrite_mem = true;
413  // keep a copy of our possible write value, and copy what is at the
414  // memory address into the packet
415  pkt->writeData(&overwrite_val[0]);
416  pkt->setData(host_addr);
417 
418  if (pkt->req->isCondSwap()) {
419  if (pkt->getSize() == sizeof(uint64_t)) {
420  condition_val64 = pkt->req->getExtraData();
421  overwrite_mem = !std::memcmp(&condition_val64, host_addr,
422  sizeof(uint64_t));
423  } else if (pkt->getSize() == sizeof(uint32_t)) {
424  condition_val32 = (uint32_t)pkt->req->getExtraData();
425  overwrite_mem = !std::memcmp(&condition_val32, host_addr,
426  sizeof(uint32_t));
427  } else
428  panic("Invalid size for conditional read/write\n");
429  }
430 
431  if (overwrite_mem)
432  std::memcpy(host_addr, &overwrite_val[0], pkt->getSize());
433 
434  assert(!pkt->req->isInstFetch());
435  TRACE_PACKET("Read/Write");
436  stats.numOther[pkt->req->requestorId()]++;
437  }
438  } else if (pkt->isRead()) {
439  assert(!pkt->isWrite());
440  if (pkt->isLLSC()) {
441  assert(!pkt->fromCache());
442  // if the packet is not coming from a cache then we have
443  // to do the LL/SC tracking here
444  trackLoadLocked(pkt);
445  }
446  if (pmemAddr) {
447  pkt->setData(host_addr);
448  }
449  TRACE_PACKET(pkt->req->isInstFetch() ? "IFetch" : "Read");
450  stats.numReads[pkt->req->requestorId()]++;
451  stats.bytesRead[pkt->req->requestorId()] += pkt->getSize();
452  if (pkt->req->isInstFetch())
453  stats.bytesInstRead[pkt->req->requestorId()] += pkt->getSize();
454  } else if (pkt->isInvalidate() || pkt->isClean()) {
455  assert(!pkt->isWrite());
456  // in a fastmem system invalidating and/or cleaning packets
457  // can be seen due to cache maintenance requests
458 
459  // no need to do anything
460  } else if (pkt->isWrite()) {
461  if (writeOK(pkt)) {
462  if (pmemAddr) {
463  pkt->writeData(host_addr);
464  DPRINTF(MemoryAccess, "%s write due to %s\n",
465  __func__, pkt->print());
466  }
467  assert(!pkt->req->isInstFetch());
468  TRACE_PACKET("Write");
469  stats.numWrites[pkt->req->requestorId()]++;
470  stats.bytesWritten[pkt->req->requestorId()] += pkt->getSize();
471  }
472  } else {
473  panic("Unexpected packet %s", pkt->print());
474  }
475 
476  if (pkt->needsResponse()) {
477  pkt->makeResponse();
478  }
479 }
480 
481 void
483 {
484  assert(pkt->getAddrRange().isSubset(range));
485 
486  uint8_t *host_addr = toHostAddr(pkt->getAddr());
487 
488  if (pkt->isRead()) {
489  if (pmemAddr) {
490  pkt->setData(host_addr);
491  }
492  TRACE_PACKET("Read");
493  pkt->makeResponse();
494  } else if (pkt->isWrite()) {
495  if (pmemAddr) {
496  pkt->writeData(host_addr);
497  }
498  TRACE_PACKET("Write");
499  pkt->makeResponse();
500  } else if (pkt->isPrint()) {
501  Packet::PrintReqState *prs =
502  dynamic_cast<Packet::PrintReqState*>(pkt->senderState);
503  assert(prs);
504  // Need to call printLabels() explicitly since we're not going
505  // through printObj().
506  prs->printLabels();
507  // Right now we just print the single byte at the specified address.
508  ccprintf(prs->os, "%s%#x\n", prs->curPrefix(), *host_addr);
509  } else {
510  panic("AbstractMemory: unimplemented functional command %s",
511  pkt->cmdString());
512  }
513 }
514 
515 } // namespace memory
516 } // namespace gem5
gem5::Packet::cmdString
const std::string & cmdString() const
Return the string name of the cmd field (for debugging and tracing).
Definition: packet.hh:577
gem5::loader::MemoryImage::maxAddr
Addr maxAddr() const
Definition: memory_image.hh:136
gem5::Packet::isAtomicOp
bool isAtomicOp() const
Definition: packet.hh:820
gem5::AddrRange::to_string
std::string to_string() const
Get a string representation of the range.
Definition: addr_range.hh:333
gem5::memory::AbstractMemory::MemStats::bytesWritten
statistics::Vector bytesWritten
Number of bytes written to this memory.
Definition: abstract_mem.hh:186
gem5::memory::AbstractMemory::MemStats::MemStats
MemStats(AbstractMemory &mem)
Definition: abstract_mem.cc:118
gem5::SimObject::initState
virtual void initState()
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: sim_object.cc:94
gem5::AddrRange::start
Addr start() const
Get the start address of the range.
Definition: addr_range.hh:317
warn
#define warn(...)
Definition: logging.hh:245
gem5::Packet::getUintX
uint64_t getUintX(ByteOrder endian) const
Get the data in the packet byte swapped from the specified endianness and zero-extended to 64 bits.
Definition: packet.cc:334
system.hh
gem5::MemCmd::CleanEvict
@ CleanEvict
Definition: packet.hh:95
gem5::memory::AbstractMemory::MemStats::numOther
statistics::Vector numOther
Number of other requests.
Definition: abstract_mem.hh:192
gem5::MemCmd::SwapReq
@ SwapReq
Definition: packet.hh:115
memory
Definition: mem.h:38
abstract_mem.hh
gem5::memory::AbstractMemory::MemStats::numWrites
statistics::Vector numWrites
Number of write requests.
Definition: abstract_mem.hh:190
gem5::Packet::setData
void setData(const uint8_t *p)
Copy data into the packet from the provided pointer.
Definition: packet.hh:1252
TRACE_PACKET
#define TRACE_PACKET(A)
Definition: abstract_mem.cc:376
gem5::memory::AbstractMemory::getAddrRange
AddrRange getAddrRange() const
Get the address range.
Definition: abstract_mem.cc:250
gem5::memory::AbstractMemory::lockedAddrList
std::list< LockedAddr > lockedAddrList
Definition: abstract_mem.hh:132
gem5::Packet::req
RequestPtr req
A pointer to the original request.
Definition: packet.hh:366
gem5::AddrRange::contains
bool contains(const Addr &a) const
Determine if the range contains an address.
Definition: addr_range.hh:438
gem5::InvalidContextID
const ContextID InvalidContextID
Definition: types.hh:247
gem5::statistics::nozero
const FlagsType nozero
Don't print if this is zero.
Definition: info.hh:68
gem5::Packet::cacheResponding
bool cacheResponding() const
Definition: packet.hh:646
gem5::Packet::isWrite
bool isWrite() const
Definition: packet.hh:583
gem5::MemBackdoor::invalidate
void invalidate()
Definition: backdoor.hh:113
std::vector< uint8_t >
gem5::statistics::nonan
const FlagsType nonan
Don't print if this is NAN.
Definition: info.hh:70
gem5::System::getGuestByteOrder
ByteOrder getGuestByteOrder() const
Get the guest byte order.
Definition: system.hh:401
gem5::AddrRange::isSubset
bool isSubset(const AddrRange &r) const
Determine if this range is a subset of another range, i.e.
Definition: addr_range.hh:413
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::Packet::PrintReqState::printLabels
void printLabels()
Print all of the pending unprinted labels on the stack.
Definition: packet.cc:458
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::memory::AbstractMemory::MemStats::numReads
statistics::Vector numReads
Number of read requests.
Definition: abstract_mem.hh:188
gem5::System::cacheLineSize
unsigned int cacheLineSize() const
Get the cache line size of the system.
Definition: system.hh:314
gem5::memory::AbstractMemory::stats
gem5::memory::AbstractMemory::MemStats stats
gem5::Packet::getAtomicOp
AtomicOpFunctor * getAtomicOp() const
Accessor function to atomic op.
Definition: packet.hh:819
gem5::Flags
Wrapper that groups a few flag bits under the same undelying container.
Definition: flags.hh:44
gem5::Packet::PrintReqState::os
std::ostream & os
Definition: packet.hh:488
gem5::System::maxRequestors
RequestorID maxRequestors()
Get the number of requestors registered in the system.
Definition: system.hh:518
gem5::Packet::isRead
bool isRead() const
Definition: packet.hh:582
gem5::System
Definition: system.hh:77
gem5::memory::AbstractMemory::MemStats::bytesInstRead
statistics::Vector bytesInstRead
Number of instruction bytes read from this memory.
Definition: abstract_mem.hh:184
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::memory::AbstractMemory::functionalAccess
void functionalAccess(PacketPtr pkt)
Perform an untimed memory read or write without changing anything but the memory itself.
Definition: abstract_mem.cc:482
gem5::memory::AbstractMemory::setBackingStore
void setBackingStore(uint8_t *pmem_addr)
Set the host memory backing store to be used by this memory controller.
Definition: abstract_mem.cc:106
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::memory::AbstractMemory::writeOK
bool writeOK(PacketPtr pkt)
Definition: abstract_mem.hh:152
gem5::Packet::print
void print(std::ostream &o, int verbosity=0, const std::string &prefix="") const
Definition: packet.cc:373
gem5::loader::MemoryImage::offset
MemoryImage & offset(Addr by)
Definition: memory_image.hh:126
gem5::AddrRange::interleaved
bool interleaved() const
Determine if the range is interleaved or not.
Definition: addr_range.hh:260
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
ADD_STAT
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
Definition: group.hh:75
gem5::memory::AbstractMemory::checkLockedAddrList
bool checkLockedAddrList(PacketPtr pkt)
Definition: abstract_mem.cc:290
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::memory::AbstractMemory::AbstractMemory
AbstractMemory(const AbstractMemory &)
gem5::memory::AbstractMemory::toHostAddr
uint8_t * toHostAddr(Addr addr) const
Transform a gem5 address space address into its physical counterpart in the host address space.
Definition: abstract_mem.hh:291
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::memory::AbstractMemory
An abstract memory represents a contiguous block of physical memory, with an associated address range...
Definition: abstract_mem.hh:110
gem5::loader::MemoryImage
Definition: memory_image.hh:53
gem5::System::getRequestorName
std::string getRequestorName(RequestorID requestor_id)
Get the name of an object for a given request id.
Definition: system.cc:637
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::Packet::getConstPtr
const T * getConstPtr() const
Definition: packet.hh:1193
gem5::PortProxy
This object is a proxy for a port or other object which implements the functional response protocol,...
Definition: port_proxy.hh:86
gem5::Packet::isLLSC
bool isLLSC() const
Definition: packet.hh:609
gem5::MemCmd::WritebackClean
@ WritebackClean
Definition: packet.hh:93
gem5::Packet::PrintReqState::curPrefix
const std::string & curPrefix()
Returns the current line prefix.
Definition: packet.hh:497
gem5::AddrRange::size
Addr size() const
Get the size of the address range.
Definition: addr_range.hh:300
gem5::AddrRange::valid
bool valid() const
Determine if the range is valid.
Definition: addr_range.hh:310
gem5::Packet::cmd
MemCmd cmd
The command field of the packet.
Definition: packet.hh:361
gem5::Packet::isPrint
bool isPrint() const
Definition: packet.hh:611
gem5::Packet::needsResponse
bool needsResponse() const
Definition: packet.hh:597
gem5::Packet::writeData
void writeData(uint8_t *p) const
Copy data from the packet to the memory at the provided pointer.
Definition: packet.hh:1281
gem5::memory::AbstractMemory::range
AddrRange range
Definition: abstract_mem.hh:115
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::Packet::senderState
SenderState * senderState
This packet's sender state.
Definition: packet.hh:534
gem5::MemBackdoor
Definition: backdoor.hh:41
gem5::statistics::Group::regStats
virtual void regStats()
Callback to set stat parameters.
Definition: group.cc:69
DDUMP
#define DDUMP(x, data, count)
DPRINTF is a debugging trace facility that allows one to selectively enable tracing statements.
Definition: trace.hh:180
packet_access.hh
gem5::ClockedObject
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Definition: clocked_object.hh:234
gem5::memory::AbstractMemory::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: abstract_mem.cc:75
gem5::loader::createObjectFile
ObjectFile * createObjectFile(const std::string &fname, bool raw)
Definition: object_file.cc:123
gem5::memory::AbstractMemory::size
uint64_t size() const
Get the memory size.
Definition: abstract_mem.hh:301
gem5::Packet::isClean
bool isClean() const
Definition: packet.hh:600
gem5::memory::AbstractMemory::MemStats::regStats
void regStats() override
Callback to set stat parameters.
Definition: abstract_mem.cc:149
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::loader::SymbolTable::insert
bool insert(const Symbol &symbol)
Insert a new symbol in the table if it does not already exist.
Definition: symtab.cc:55
gem5::MemBackdoor::ptr
uint8_t * ptr() const
Definition: backdoor.hh:62
gem5::memory::AbstractMemory::MemStats::bytesRead
statistics::Vector bytesRead
Number of total bytes read from this memory.
Definition: abstract_mem.hh:182
gem5::loader::MemoryImage::minAddr
Addr minAddr() const
Definition: memory_image.hh:145
gem5::System::threads
Threads threads
Definition: system.hh:316
gem5::memory::AbstractMemory::backdoor
MemBackdoor backdoor
Definition: abstract_mem.hh:121
gem5::memory::AbstractMemory::system
System * system() const
read the system pointer Implemented for completeness with the setter
Definition: abstract_mem.hh:266
gem5::ArmISA::globalClearExclusive
void globalClearExclusive(XC *xc)
Definition: locked_mem.hh:152
gem5::Packet::makeResponse
void makeResponse()
Take a request packet and modify it in place to be suitable for returning as a response to that reque...
Definition: packet.hh:1031
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:246
gem5::simSeconds
statistics::Formula & simSeconds
Definition: stats.cc:45
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::memory::LockedAddr
Locked address class that represents a physical address and a context id.
Definition: abstract_mem.hh:67
gem5::loader::MemoryImage::write
bool write(const PortProxy &proxy) const
Definition: memory_image.cc:54
gem5::Packet::fromCache
bool fromCache() const
Definition: packet.hh:601
mem
bool_vector8 mem[]
Definition: reset_stim.h:43
gem5::ClockedObject::Params
ClockedObjectParams Params
Parameters of ClockedObject.
Definition: clocked_object.hh:240
gem5::loader::debugSymbolTable
SymbolTable debugSymbolTable
Global unified debugging symbol table (for target).
Definition: symtab.cc:44
gem5::AddrRange
The AddrRange class encapsulates an address range, and supports a number of tests to check if two ran...
Definition: addr_range.hh:71
std::list
STL list class.
Definition: stl.hh:51
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:225
gem5::memory::LockedAddr::mask
static Addr mask(Addr paddr)
Definition: abstract_mem.hh:84
gem5::memory::AbstractMemory::access
void access(PacketPtr pkt)
Perform an untimed memory access and update all the state (e.g.
Definition: abstract_mem.cc:380
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::statistics::total
const FlagsType total
Print the total.
Definition: info.hh:60
gem5::Packet::getAddrRange
AddrRange getAddrRange() const
Get address range to which this packet belongs.
Definition: packet.cc:225
object_file.hh
memory_image.hh
thread_context.hh
gem5::memory::AbstractMemory::trackLoadLocked
void trackLoadLocked(PacketPtr pkt)
Definition: abstract_mem.cc:258
gem5::Packet::getSize
unsigned getSize() const
Definition: packet.hh:791
gem5::Packet::isInvalidate
bool isInvalidate() const
Definition: packet.hh:598
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::Packet::PrintReqState
Object used to maintain state of a PrintReq.
Definition: packet.hh:468
gem5::memory::AbstractMemory::pmemAddr
uint8_t * pmemAddr
Definition: abstract_mem.hh:118

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