TLB Invalidate by Intermediate Physical Address. More...

#include <tlbi_op.hh>

Inheritance diagram for gem5::ArmISA::TLBIIPA:

Public Member Functions
	TLBIIPA (TranslationRegime _target_regime, bool _secure, Addr _addr, bool last_level)

void	operator() (ThreadContext *tc) override

bool	match (TlbEntry *entry, vmid_t curr_vmid) const override

bool	stage1Flush () const override
	Return true if the TLBI op needs to flush stage1 entries, Defaulting to true in the TLBIOp abstract class.

virtual TLBIMVAA	makeStage2 () const
	TLBIIPA is basically a TLBIMVAA for stage2 TLBs.

Public Member Functions inherited from gem5::ArmISA::TLBIOp
	TLBIOp (TranslationRegime _target_regime, bool _secure)

virtual	~TLBIOp ()

void	broadcast (ThreadContext *tc)
	Broadcast the TLB Invalidate operation to all TLBs in the Arm system.

virtual bool	stage2Flush () const
	Return true if the TLBI op needs to flush stage2 entries, Defaulting to false in the TLBIOp abstract class.

Public Attributes
Addr	addr

bool	lastLevel

Public Attributes inherited from gem5::ArmISA::TLBIOp
bool	secureLookup

TranslationRegime	targetRegime

Detailed Description

TLB Invalidate by Intermediate Physical Address.

Definition at line 415 of file tlbi_op.hh.

Constructor & Destructor Documentation

◆ TLBIIPA()

gem5::ArmISA::TLBIIPA::TLBIIPA	(	TranslationRegime	_target_regime,
		bool	_secure,
		Addr	_addr,
		bool	last_level )

inline

Definition at line 418 of file tlbi_op.hh.

Member Function Documentation

◆ makeStage2()

virtual TLBIMVAA gem5::ArmISA::TLBIIPA::makeStage2 ( ) const

inlinevirtual

TLBIIPA is basically a TLBIMVAA for stage2 TLBs.

Reimplemented in gem5::ArmISA::TLBIRIPA.

Definition at line 439 of file tlbi_op.hh.

References addr, lastLevel, gem5::ArmISA::TLBIOp::secureLookup, and gem5::ArmISA::TLBIOp::targetRegime.

Referenced by operator()().

◆ match()

bool gem5::ArmISA::TLBIIPA::match	(	TlbEntry *	entry,
		vmid_t	curr_vmid ) const

inlineoverridevirtual

Implements gem5::ArmISA::TLBIOp.

Definition at line 426 of file tlbi_op.hh.

References panic.

◆ operator()()

void gem5::ArmISA::TLBIIPA::operator() ( ThreadContext * tc )

overridevirtual

Reimplemented from gem5::ArmISA::TLBIOp.

Definition at line 296 of file tlbi_op.cc.

References gem5::ArmISA::MMU::flushStage2(), gem5::ThreadContext::getCheckerCpuPtr(), gem5::ArmISA::getMMUPtr(), and makeStage2().

◆ stage1Flush()

bool gem5::ArmISA::TLBIIPA::stage1Flush ( ) const

inlineoverridevirtual

Return true if the TLBI op needs to flush stage1 entries, Defaulting to true in the TLBIOp abstract class.

Reimplemented from gem5::ArmISA::TLBIOp.

Definition at line 432 of file tlbi_op.hh.

Member Data Documentation

◆ addr

Addr gem5::ArmISA::TLBIIPA::addr

Definition at line 444 of file tlbi_op.hh.

Referenced by makeStage2().

◆ lastLevel

bool gem5::ArmISA::TLBIIPA::lastLevel

Definition at line 445 of file tlbi_op.hh.

Referenced by makeStage2(), and gem5::ArmISA::TLBIRIPA::makeStage2().

The documentation for this class was generated from the following files:

arch/arm/tlbi_op.hh
arch/arm/tlbi_op.cc

Public Member Functions

Public Attributes