gem5 v24.1.0.1
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TLB Invalidate by Intermediate Physical Address. More...
#include <tlbi_op.hh>
Public Member Functions | |
TLBIIPA (TranslationRegime _target_regime, SecurityState _ss, Addr _addr, bool last_level, Attr _attr=Attr::None) | |
TLBIIPA (ThreadContext *tc, TranslationRegime _target_regime, SecurityState _ss, RegVal val, bool last_level, Attr _attr=Attr::None) | |
void | operator() (ThreadContext *tc) override |
bool | matchEntry (TlbEntry *entry, vmid_t curr_vmid) const override |
bool | stage1Flush () const override |
Return true if the TLBI op needs to flush stage1 entries, Defaulting to true in the TLBIOp abstract class. | |
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TLBIOp (TranslationRegime _target_regime, SecurityState _ss, Attr _attr) | |
virtual | ~TLBIOp () |
void | broadcast (ThreadContext *tc) |
Broadcast the TLB Invalidate operation to all TLBs in the Arm system. | |
bool | match (TlbEntry *entry, vmid_t curr_vmid) const |
virtual bool | stage2Flush () const |
Return true if the TLBI op needs to flush stage2 entries, Defaulting to false in the TLBIOp abstract class. | |
Public Attributes | |
Addr | addr |
bool | lastLevel |
PASpace | ipaSpace |
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SecurityState | ss |
TranslationRegime | targetRegime |
Attr | attr |
Protected Member Functions | |
TlbEntry::KeyType | lookupGen (vmid_t vmid) const |
Additional Inherited Members | |
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enum class | Attr { None , ExcludeXS } |
TLB Invalidate by Intermediate Physical Address.
Definition at line 405 of file tlbi_op.hh.
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inline |
Definition at line 410 of file tlbi_op.hh.
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inline |
Definition at line 418 of file tlbi_op.hh.
References addr, gem5::bits(), ipaSpace, gem5::ArmISA::NonSecure, panic, gem5::ArmSystem::physAddrRange(), gem5::ArmISA::Secure, gem5::ArmISA::TLBIOp::ss, and gem5::X86ISA::val.
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protected |
Definition at line 313 of file tlbi_op.cc.
References addr, gem5::ArmISA::TLBTypes::KeyType::functional, gem5::ArmISA::TLBTypes::KeyType::ignoreAsn, gem5::ArmISA::TLBTypes::KeyType::mode, gem5::BaseMMU::Read, gem5::ArmISA::TLBTypes::KeyType::ss, gem5::ArmISA::TLBIOp::ss, gem5::ArmISA::TLBTypes::KeyType::targetRegime, gem5::ArmISA::TLBIOp::targetRegime, gem5::ArmISA::TLBTypes::KeyType::va, and gem5::ArmISA::TLBTypes::KeyType::vmid.
Referenced by matchEntry(), and gem5::ArmISA::TLBIRIPA::matchEntry().
Implements gem5::ArmISA::TLBIOp.
Reimplemented in gem5::ArmISA::TLBIRIPA.
Definition at line 327 of file tlbi_op.cc.
References ipaSpace, lastLevel, lookupGen(), and gem5::ArmISA::te.
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overridevirtual |
Reimplemented from gem5::ArmISA::TLBIOp.
Definition at line 302 of file tlbi_op.cc.
References gem5::ArmISA::MMU::flushStage2(), gem5::ThreadContext::getCheckerCpuPtr(), and gem5::ArmISA::getMMUPtr().
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inlineoverridevirtual |
Return true if the TLBI op needs to flush stage1 entries, Defaulting to true in the TLBIOp abstract class.
Reimplemented from gem5::ArmISA::TLBIOp.
Definition at line 448 of file tlbi_op.hh.
Addr gem5::ArmISA::TLBIIPA::addr |
Definition at line 453 of file tlbi_op.hh.
Referenced by lookupGen(), TLBIIPA(), and gem5::ArmISA::TLBIRIPA::TLBIRIPA().
PASpace gem5::ArmISA::TLBIIPA::ipaSpace |
Definition at line 455 of file tlbi_op.hh.
Referenced by matchEntry(), gem5::ArmISA::TLBIRIPA::matchEntry(), and TLBIIPA().
bool gem5::ArmISA::TLBIIPA::lastLevel |
Definition at line 454 of file tlbi_op.hh.
Referenced by matchEntry(), and gem5::ArmISA::TLBIRIPA::matchEntry().