The TLBCoalescer is a ClockedObject sitting on the front side (CPUSide) of each TLB. More...

#include <tlb_coalescer.hh>

Inheritance diagram for gem5::TLBCoalescer:

Classes
class	CpuSidePort

class	MemSidePort

struct	TLBCoalescerStats

Public Types
typedef TLBCoalescerParams	Params

typedef std::vector< PacketPtr >	coalescedReq

typedef std::map< int64_t, std::vector< coalescedReq > >	CoalescingFIFO

typedef std::unordered_map< Addr, coalescedReq >	CoalescingTable

Public Types inherited from gem5::ClockedObject
using	Params = ClockedObjectParams
	Parameters of ClockedObject.

Public Types inherited from gem5::SimObject
typedef SimObjectParams	Params

Public Member Functions
	TLBCoalescer (const Params &p)

	~TLBCoalescer ()

bool	canCoalesce (PacketPtr pkt1, PacketPtr pkt2)

void	updatePhysAddresses (PacketPtr pkt)

Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID) override
	Get a port with a given name and index.

void	processProbeTLBEvent ()

void	processCleanupEvent ()

Public Member Functions inherited from gem5::ClockedObject
	ClockedObject (const ClockedObjectParams &p)

void	serialize (CheckpointOut &cp) const override
	Serialize an object.

void	unserialize (CheckpointIn &cp) override
	Unserialize an object.

Public Member Functions inherited from gem5::SimObject
const Params &	params () const

	SimObject (const Params &p)

virtual	~SimObject ()

virtual void	init ()
	init() is called after all C++ SimObjects have been created and all ports are connected.

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint.

virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint.

virtual void	regProbePoints ()
	Register probe points for this object.

virtual void	regProbeListeners ()
	Register probe listeners for this object.

ProbeManager *	getProbeManager ()
	Get the probe manager for this object.

virtual void	startup ()
	startup() is the final initialization call before simulation.

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining.

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes.

virtual void	memInvalidate ()
	Invalidate the contents of memory buffers.

void	serialize (CheckpointOut &cp) const override
	Serialize an object.

void	unserialize (CheckpointIn &cp) override
	Unserialize an object.

Public Member Functions inherited from gem5::EventManager
EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick) -1)
	This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers.

void	setCurTick (Tick newVal)

	EventManager (EventManager &em)
	Event manger manages events in the event queue.

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

Public Member Functions inherited from gem5::Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section.

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object.

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from gem5::Drainable
DrainState	drainState () const
	Return the current drain state of an object.

virtual void	notifyFork ()
	Notify a child process of a fork.

Public Member Functions inherited from gem5::statistics::Group
	Group (Group parent, const char name=nullptr)
	Construct a new statistics group.

virtual	~Group ()

virtual void	regStats ()
	Callback to set stat parameters.

virtual void	resetStats ()
	Callback to reset stats.

virtual void	preDumpStats ()
	Callback before stats are dumped.

void	addStat (statistics::Info *info)
	Register a stat with this group.

const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object.

const std::vector< Info * > &	getStats () const
	Get all stats associated with this object.

void	addStatGroup (const char name, Group block)
	Add a stat block as a child of this block.

const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group.

void	mergeStatGroup (Group *block)
	Merge the contents (stats & children) of a block to this block.

	Group ()=delete

	Group (const Group &)=delete

Group &	operator= (const Group &)=delete

Public Member Functions inherited from gem5::Named
	Named (const std::string &name_)

virtual	~Named ()=default

virtual std::string	name () const

Public Member Functions inherited from gem5::Clocked
void	updateClockPeriod ()
	Update the tick to the current tick.

Tick	clockEdge (Cycles cycles=Cycles(0)) const
	Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle.

Cycles	curCycle () const
	Determine the current cycle, corresponding to a tick aligned to a clock edge.

Tick	nextCycle () const
	Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future.

uint64_t	frequency () const

Tick	clockPeriod () const

double	voltage () const

Cycles	ticksToCycles (Tick t) const

Tick	cyclesToTicks (Cycles c) const

Public Attributes
int	TLBProbesPerCycle

int	coalescingWindow

bool	disableCoalescing

CoalescingFIFO	coalescerFIFO

CoalescingTable	issuedTranslationsTable

std::vector< CpuSidePort * >	cpuSidePort

std::vector< MemSidePort * >	memSidePort

EventFunctionWrapper	probeTLBEvent
	This event issues the TLB probes.

EventFunctionWrapper	cleanupEvent
	The cleanupEvent is scheduled after a TLBEvent triggers in order to free memory and do the required clean-up.

std::queue< Addr >	cleanupQueue

Public Attributes inherited from gem5::ClockedObject
PowerState *	powerState

Protected Attributes
gem5::TLBCoalescer::TLBCoalescerStats	stats

Protected Attributes inherited from gem5::SimObject
const SimObjectParams &	_params
	Cached copy of the object parameters.

Protected Attributes inherited from gem5::EventManager
EventQueue *	eventq
	A pointer to this object's event queue.

Additional Inherited Members
Static Public Member Functions inherited from gem5::SimObject
static void	serializeAll (const std::string &cpt_dir)
	Create a checkpoint by serializing all SimObjects in the system.

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it.

static void	setSimObjectResolver (SimObjectResolver *resolver)
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints.

static SimObjectResolver *	getSimObjectResolver ()
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints.

Static Public Member Functions inherited from gem5::Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section.

static void	generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
	Generate a checkpoint file so that the serialization can be routed to it.

Protected Member Functions inherited from gem5::Drainable
	Drainable ()

virtual	~Drainable ()

virtual void	drainResume ()
	Resume execution after a successful drain.

void	signalDrainDone () const
	Signal that an object is drained.

Protected Member Functions inherited from gem5::Clocked
	Clocked (ClockDomain &clk_domain)
	Create a clocked object and set the clock domain based on the parameters.

	Clocked (Clocked &)=delete

Clocked &	operator= (Clocked &)=delete

virtual	~Clocked ()
	Virtual destructor due to inheritance.

void	resetClock () const
	Reset the object's clock using the current global tick value.

virtual void	clockPeriodUpdated ()
	A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed.

Detailed Description

The TLBCoalescer is a ClockedObject sitting on the front side (CPUSide) of each TLB.

It receives packets and issues coalesced requests to the TLB below it. It controls how requests are coalesced (the rules) and the permitted number of TLB probes per cycle (i.e., how many coalesced requests it feeds the TLB per cycle).

Definition at line 66 of file tlb_coalescer.hh.

Member Typedef Documentation

◆ coalescedReq

typedef std::vector<PacketPtr> gem5::TLBCoalescer::coalescedReq

Definition at line 82 of file tlb_coalescer.hh.

◆ CoalescingFIFO

typedef std::map<int64_t, std::vector<coalescedReq> > gem5::TLBCoalescer::CoalescingFIFO

Definition at line 102 of file tlb_coalescer.hh.

◆ CoalescingTable

typedef std::unordered_map<Addr, coalescedReq> gem5::TLBCoalescer::CoalescingTable

Definition at line 115 of file tlb_coalescer.hh.

◆ Params

typedef TLBCoalescerParams gem5::TLBCoalescer::Params

Definition at line 69 of file tlb_coalescer.hh.

Constructor & Destructor Documentation

◆ TLBCoalescer()

gem5::TLBCoalescer::TLBCoalescer ( const Params & p )

Definition at line 45 of file tlb_coalescer.cc.

References processProbeTLBEvent().

◆ ~TLBCoalescer()

gem5::TLBCoalescer::~TLBCoalescer ( )

inline

Definition at line 71 of file tlb_coalescer.hh.

Member Function Documentation

◆ canCoalesce()

bool gem5::TLBCoalescer::canCoalesce	(	PacketPtr	pkt1,
		PacketPtr	pkt2 )

Definition at line 98 of file tlb_coalescer.cc.

References disableCoalescing, gem5::GpuTranslationState::isPrefetch, gem5::X86ISA::PageBytes, gem5::Packet::req, gem5::GpuTranslationState::reqCnt, gem5::roundDown(), gem5::safe_cast(), gem5::Packet::senderState, and gem5::GpuTranslationState::tlbMode.

Referenced by gem5::TLBCoalescer::CpuSidePort::recvTimingReq().

◆ getPort()

Port & gem5::TLBCoalescer::getPort	(	const std::string &	if_name,
		PortID	idx = InvalidPortID )

overridevirtual

Get a port with a given name and index.

This is used at binding time and returns a reference to a protocol-agnostic port.

gem5 has a request and response port interface. All memory objects are connected together via ports. These ports provide a rigid interface between these memory objects. These ports implement three different memory system modes: timing, atomic, and functional. The most important mode is the timing mode and here timing mode is used for conducting cycle-level timing experiments. The other modes are only used in special circumstances and should not be used to conduct cycle-level timing experiments. The other modes are only used in special circumstances. These ports allow SimObjects to communicate with each other.

Parameters

if_name	Port name
idx	Index in the case of a VectorPort

Returns: A reference to the given port

Reimplemented from gem5::SimObject.

Definition at line 72 of file tlb_coalescer.cc.

References cpuSidePort, memSidePort, and panic.

◆ processCleanupEvent()

void gem5::TLBCoalescer::processCleanupEvent ( )

Definition at line 515 of file tlb_coalescer.cc.

References cleanupQueue, DPRINTF, and issuedTranslationsTable.

◆ processProbeTLBEvent()

void gem5::TLBCoalescer::processProbeTLBEvent ( )

◆ updatePhysAddresses()

void gem5::TLBCoalescer::updatePhysAddresses ( PacketPtr pkt )

Definition at line 143 of file tlb_coalescer.cc.

References cleanupEvent, cleanupQueue, gem5::curTick(), DPRINTF, gem5::ThreadContext::getProcessPtr(), gem5::GpuTranslationState::hitLevel, gem5::ArmISA::i, gem5::GpuTranslationState::isPrefetch, gem5::Packet::isRequest(), issuedTranslationsTable, gem5::Packet::makeTimingResponse(), gem5::MipsISA::p, gem5::X86ISA::TlbEntry::paddr, gem5::X86ISA::PageBytes, gem5::GpuTranslationState::ports, gem5::Packet::req, gem5::GpuTranslationState::reqCnt, gem5::roundDown(), gem5::safe_cast(), gem5::EventManager::schedule(), gem5::Event::scheduled(), gem5::Packet::senderState, gem5::ResponsePort::sendTimingResp(), gem5::X86ISA::TlbEntry::size(), gem5::GpuTranslationState::tc, gem5::GpuTranslationState::tlbEntry, gem5::Request::UNCACHEABLE, gem5::X86ISA::TlbEntry::uncacheable, and gem5::X86ISA::TlbEntry::vaddr.

Member Data Documentation

◆ cleanupEvent

EventFunctionWrapper gem5::TLBCoalescer::cleanupEvent

The cleanupEvent is scheduled after a TLBEvent triggers in order to free memory and do the required clean-up.

Definition at line 192 of file tlb_coalescer.hh.

Referenced by updatePhysAddresses().

◆ cleanupQueue

std::queue<Addr> gem5::TLBCoalescer::cleanupQueue

Definition at line 196 of file tlb_coalescer.hh.

Referenced by processCleanupEvent(), and updatePhysAddresses().

◆ coalescerFIFO

CoalescingFIFO gem5::TLBCoalescer::coalescerFIFO

Definition at line 104 of file tlb_coalescer.hh.

Referenced by processProbeTLBEvent(), and gem5::TLBCoalescer::CpuSidePort::recvTimingReq().

◆ coalescingWindow

int gem5::TLBCoalescer::coalescingWindow

Definition at line 78 of file tlb_coalescer.hh.

Referenced by gem5::TLBCoalescer::CpuSidePort::recvTimingReq().

◆ cpuSidePort

std::vector<CpuSidePort*> gem5::TLBCoalescer::cpuSidePort

Definition at line 178 of file tlb_coalescer.hh.

Referenced by getPort().

◆ disableCoalescing

bool gem5::TLBCoalescer::disableCoalescing

Definition at line 85 of file tlb_coalescer.hh.

Referenced by canCoalesce().

◆ issuedTranslationsTable

CoalescingTable gem5::TLBCoalescer::issuedTranslationsTable

Definition at line 117 of file tlb_coalescer.hh.

Referenced by processCleanupEvent(), processProbeTLBEvent(), and updatePhysAddresses().

◆ memSidePort

std::vector<MemSidePort*> gem5::TLBCoalescer::memSidePort

Definition at line 180 of file tlb_coalescer.hh.

Referenced by getPort(), and processProbeTLBEvent().

◆ probeTLBEvent

EventFunctionWrapper gem5::TLBCoalescer::probeTLBEvent

This event issues the TLB probes.

Definition at line 187 of file tlb_coalescer.hh.

Referenced by gem5::TLBCoalescer::CpuSidePort::recvTimingReq().

◆ stats

gem5::TLBCoalescer::TLBCoalescerStats gem5::TLBCoalescer::stats

protected

Referenced by processProbeTLBEvent(), and gem5::TLBCoalescer::CpuSidePort::recvTimingReq().

◆ TLBProbesPerCycle

int gem5::TLBCoalescer::TLBProbesPerCycle

Definition at line 74 of file tlb_coalescer.hh.

Referenced by processProbeTLBEvent().

The documentation for this class was generated from the following files:

arch/amdgpu/common/tlb_coalescer.hh
arch/amdgpu/common/tlb_coalescer.cc

Classes

Public Types

Public Member Functions

Public Attributes

Protected Attributes

Additional Inherited Members

Detailed Description

Member Typedef Documentation

◆ coalescedReq

◆ CoalescingFIFO

◆ CoalescingTable

◆ Params

Constructor & Destructor Documentation

◆ TLBCoalescer()

◆ ~TLBCoalescer()

Member Function Documentation

◆ canCoalesce()

◆ getPort()

◆ processCleanupEvent()

◆ processProbeTLBEvent()

◆ updatePhysAddresses()

Member Data Documentation

◆ cleanupEvent

◆ cleanupQueue

◆ coalescerFIFO

◆ coalescingWindow

◆ cpuSidePort

◆ disableCoalescing

◆ issuedTranslationsTable

◆ memSidePort

◆ probeTLBEvent

◆ stats

◆ TLBProbesPerCycle