gem5  v21.1.0.2
cortex_a76.hh
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27 
28 #ifndef __ARCH_ARM_FASTMODEL_CORTEXA76_CORETEX_A76_HH__
29 #define __ARCH_ARM_FASTMODEL_CORTEXA76_CORETEX_A76_HH__
30 
34 #include "params/FastModelCortexA76.hh"
35 #include "params/FastModelCortexA76Cluster.hh"
36 #include "scx/scx.h"
37 #include "sim/port.hh"
39 
40 namespace gem5
41 {
42 
43 class BaseCPU;
44 
45 GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
46 namespace fastmodel
47 {
48 
49 // The fast model exports a class called scx_evs_CortexA76x1 which represents
50 // the subsystem described in LISA+. This class specializes it to export gem5
51 // ports and interface with its peer gem5 CPU. The gem5 CPU inherits from the
52 // gem5 BaseCPU class and implements its API, while this class actually does
53 // the work.
54 class CortexA76Cluster;
55 
56 class CortexA76 : public Iris::CPU<CortexA76TC>
57 {
58  protected:
60 
62  int num = 0;
63 
64  public:
65  PARAMS(FastModelCortexA76);
66  CortexA76(const Params &p) :
67  Base(p, scx::scx_get_iris_connection_interface())
68  {}
69 
70  void initState() override;
71 
72  template <class T>
73  void set_evs_param(const std::string &n, T val);
74 
75  void setCluster(CortexA76Cluster *_cluster, int _num);
76 
77  Port &getPort(const std::string &if_name,
78  PortID idx=InvalidPortID) override;
79 };
80 
82 {
83  private:
86 
87  public:
88  PARAMS(FastModelCortexA76Cluster);
89  template <class T>
90  void
91  set_evs_param(const std::string &n, T val)
92  {
93  scx::scx_set_parameter(evs->name() + std::string(".") + n, val);
94  }
95 
96  CortexA76 *getCore(int num) const { return cores.at(num); }
97  sc_core::sc_module *getEvs() const { return evs; }
98 
99  CortexA76Cluster(const Params &p);
100 
101  Port &getPort(const std::string &if_name,
102  PortID idx=InvalidPortID) override;
103 };
104 
105 template <class T>
106 inline void
107 CortexA76::set_evs_param(const std::string &n, T val)
108 {
109  for (auto &path: params().thread_paths)
110  cluster->set_evs_param(path + "." + n, val);
111 }
112 
113 } // namespace fastmodel
114 } // namespace gem5
115 
116 #endif // __ARCH_ARM_FASTMODEL_CORTEXA76_CORETEX_A76_HH__
gem5::fastmodel::CortexA76::Base
Iris::CPU< CortexA76TC > Base
Definition: cortex_a76.hh:59
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::fastmodel::CortexA76Cluster::cores
std::vector< CortexA76 * > cores
Definition: cortex_a76.hh:84
sc_core::sc_module
Definition: sc_module.hh:98
gem5::Serializable::path
static std::stack< std::string > path
Definition: serialize.hh:315
gem5::fastmodel::CortexA76Cluster::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: cortex_a76.cc:194
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::fastmodel::CortexA76Cluster::getCore
CortexA76 * getCore(int num) const
Definition: cortex_a76.hh:96
thread_context.hh
std::vector
STL vector class.
Definition: stl.hh:37
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:253
gem5::fastmodel::CortexA76::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: cortex_a76.cc:44
cpu.hh
gem5::fastmodel::CortexA76Cluster::evs
sc_core::sc_module * evs
Definition: cortex_a76.hh:85
gem5::fastmodel::CortexA76::PARAMS
PARAMS(FastModelCortexA76)
gem5::SimObject::Params
SimObjectParams Params
Definition: sim_object.hh:170
gem5::fastmodel::CortexA76::num
int num
Definition: cortex_a76.hh:62
gem5::fastmodel::CortexA76::setCluster
void setCluster(CortexA76Cluster *_cluster, int _num)
Definition: cortex_a76.cc:53
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::fastmodel::CortexA76::CortexA76
CortexA76(const Params &p)
Definition: cortex_a76.hh:66
gem5::fastmodel::CortexA76Cluster::getEvs
sc_core::sc_module * getEvs() const
Definition: cortex_a76.hh:97
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::fastmodel::CortexA76::cluster
CortexA76Cluster * cluster
Definition: cortex_a76.hh:61
gem5::fastmodel::CortexA76Cluster::PARAMS
PARAMS(FastModelCortexA76Cluster)
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::fastmodel::CortexA76Cluster::CortexA76Cluster
CortexA76Cluster(const Params &p)
Definition: cortex_a76.cc:107
port.hh
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
sc_module.hh
amba_ports.hh
gem5::fastmodel::CortexA76::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: cortex_a76.cc:99
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::ArmISA::n
Bitfield< 31 > n
Definition: misc_types.hh:455
gem5::fastmodel::CortexA76
Definition: cortex_a76.hh:56
sc_core::sc_object::name
const char * name() const
Definition: sc_object.cc:44
gem5::fastmodel::CortexA76::set_evs_param
void set_evs_param(const std::string &n, T val)
Definition: cortex_a76.hh:107
gem5::Iris::CPU
Definition: cpu.hh:113
gem5::fastmodel::CortexA76Cluster
Definition: cortex_a76.hh:81
gem5::ClockedObject::Params
ClockedObjectParams Params
Parameters of ClockedObject.
Definition: clocked_object.hh:240
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::fastmodel::CortexA76Cluster::set_evs_param
void set_evs_param(const std::string &n, T val)
Definition: cortex_a76.hh:91

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