64 params().enable_trace_special_hlt_imm16);
67 params().l2cache_maintenance_latency);
70 params().l2cache_read_access_latency);
74 params().l2cache_snoop_data_transfer_latency);
76 params().l2cache_snoop_issue_latency);
78 params().l2cache_write_access_latency);
107 if (if_name ==
"redistributor" || if_name ==
"core_reset" ||
108 if_name ==
"poweron_reset")
117 for (
int i = 0;
i <
p.cores.size();
i++)
118 p.cores[
i]->setCluster(
this,
i);
121 panic_if(!
e,
"EVS should be of type Iris::BaseCpuEvs");
134 p.dcache_maintenance_latency);
137 p.dcache_prefetch_enabled);
139 p.dcache_read_access_latency);
142 p.dcache_snoop_data_transfer_latency);
143 set_evs_param(
"core.dcache-state_modelled",
p.dcache_state_modelled);
145 p.dcache_write_access_latency);
146 set_evs_param(
"core.dcache-write_latency",
p.dcache_write_latency);
149 set_evs_param(
"core.enable_simulation_performance_optimizations",
150 p.enable_simulation_performance_optimizations);
152 p.ext_abort_device_read_is_sync);
154 p.ext_abort_device_write_is_sync);
156 p.ext_abort_so_read_is_sync);
158 p.ext_abort_so_write_is_sync);
160 p.gicv3_cpuintf_mmap_access_level);
163 p.has_statistical_profiling);
166 p.icache_maintenance_latency);
169 p.icache_prefetch_enabled);
171 p.icache_read_access_latency);
173 set_evs_param(
"core.icache-state_modelled",
p.icache_state_modelled);
176 p.l3cache_maintenance_latency);
177 set_evs_param(
"core.l3cache-miss_latency",
p.l3cache_miss_latency);
179 p.l3cache_read_access_latency);
180 set_evs_param(
"core.l3cache-read_latency",
p.l3cache_read_latency);
183 p.l3cache_snoop_data_transfer_latency);
185 p.l3cache_snoop_issue_latency);
187 p.l3cache_write_access_latency);
188 set_evs_param(
"core.l3cache-write_latency",
p.l3cache_write_latency);
190 p.pchannel_treat_simreset_as_poreset);
192 set_evs_param(
"core.periph_address_start",
p.periph_address_start);
196 p.treat_dcache_cmos_to_pou_as_nop);
203 if (if_name ==
"amba" || if_name ==
"top_reset" ||
204 if_name ==
"dbg_reset" || if_name ==
"model_reset") {
Base class for ARM GIC implementations.
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port on this CPU.
std::vector< ThreadContext * > threadContexts
Iris::BaseCpuEvs * evs_base_cpu
virtual void setSysCounterFrq(uint64_t sys_counter_frq)=0
virtual void setResetAddr(int core, Addr addr, bool secure)=0
Ports are used to interface objects to each other.
Abstract superclass for simulation objects.
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
sc_core::sc_module * getEvs() const
void set_evs_param(const std::string &n, T val)
CortexA76Cluster(const Params &p)
void setCluster(CortexA76Cluster *_cluster, int _num)
void set_evs_param(const std::string &n, T val)
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
void setResetAddr(Addr addr, bool secure=false) override
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
CortexA76Cluster * cluster
virtual gem5::Port & gem5_getPort(const std::string &if_name, int idx=-1)
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
const Params & params() const
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)