gem5  v22.0.0.1
operand.hh
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31 
32 #ifndef __ARCH_GCN3_OPERAND_HH__
33 #define __ARCH_GCN3_OPERAND_HH__
34 
35 #include <array>
36 
38 #include "arch/generic/vec_reg.hh"
41 #include "gpu-compute/wavefront.hh"
42 
43 namespace gem5
44 {
45 
52 namespace Gcn3ISA
53 {
59  template<typename T> struct OpTraits { typedef float FloatT; };
60  template<> struct OpTraits<ScalarRegF64> { typedef double FloatT; };
61  template<> struct OpTraits<ScalarRegU64> { typedef double FloatT; };
62 
63  class Operand
64  {
65  public:
66  Operand() = delete;
67 
68  Operand(GPUDynInstPtr gpuDynInst, int opIdx)
69  : _gpuDynInst(gpuDynInst), _opIdx(opIdx)
70  {
71  assert(_gpuDynInst);
72  assert(_opIdx >= 0);
73  }
74 
79  virtual void read() = 0;
80  virtual void write() = 0;
81 
82  protected:
93  int _opIdx;
94  };
95 
96  template<typename DataType, bool Const, size_t NumDwords>
98 
99  template<typename DataType, bool Const,
100  size_t NumDwords = sizeof(DataType) / sizeof(VecElemU32)>
101  class VecOperand final : public Operand
102  {
103  static_assert(NumDwords >= 1 && NumDwords <= MaxOperandDwords,
104  "Incorrect number of DWORDS for GCN3 operand.");
105 
106  public:
107  VecOperand() = delete;
108 
109  VecOperand(GPUDynInstPtr gpuDynInst, int opIdx)
110  : Operand(gpuDynInst, opIdx), scalar(false), absMod(false),
111  negMod(false), scRegData(gpuDynInst, _opIdx),
112  vrfData{{ nullptr }}
113  {
114  vecReg.zero();
115  }
116 
118  {
119  }
120 
129  void
131  {
132  if (isVectorReg(_opIdx)) {
134  ->reservedScalarRegs);
135  read();
136  } else {
137  readScalar();
138  }
139  }
140 
145  void
146  read() override
147  {
148  assert(_gpuDynInst);
149  assert(_gpuDynInst->wavefront());
150  assert(_gpuDynInst->computeUnit());
151  Wavefront *wf = _gpuDynInst->wavefront();
152  ComputeUnit *cu = _gpuDynInst->computeUnit();
153 
154  for (auto i = 0; i < NumDwords; ++i) {
155  int vgprIdx = cu->registerManager->mapVgpr(wf, _opIdx + i);
156  vrfData[i] = &cu->vrf[wf->simdId]->readWriteable(vgprIdx);
157 
158  DPRINTF(GPUVRF, "Read v[%d]\n", vgprIdx);
159  cu->vrf[wf->simdId]->printReg(wf, vgprIdx);
160  }
161 
162  if (NumDwords == 1) {
163  assert(vrfData[0]);
164  auto vgpr = vecReg.template as<DataType>();
165  auto reg_file_vgpr = vrfData[0]->template as<VecElemU32>();
166  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
167  std::memcpy((void*)&vgpr[lane],
168  (void*)&reg_file_vgpr[lane], sizeof(DataType));
169  }
170  } else if (NumDwords == 2) {
171  assert(vrfData[0]);
172  assert(vrfData[1]);
173  auto vgpr = vecReg.template as<VecElemU64>();
174  auto reg_file_vgpr0 = vrfData[0]->template as<VecElemU32>();
175  auto reg_file_vgpr1 = vrfData[1]->template as<VecElemU32>();
176 
177  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
178  VecElemU64 tmp_val(0);
179  ((VecElemU32*)&tmp_val)[0] = reg_file_vgpr0[lane];
180  ((VecElemU32*)&tmp_val)[1] = reg_file_vgpr1[lane];
181  vgpr[lane] = tmp_val;
182  }
183  }
184  }
185 
197  void
198  write() override
199  {
200  assert(_gpuDynInst);
201  assert(_gpuDynInst->wavefront());
202  assert(_gpuDynInst->computeUnit());
203  Wavefront *wf = _gpuDynInst->wavefront();
204  ComputeUnit *cu = _gpuDynInst->computeUnit();
205  VectorMask &exec_mask = _gpuDynInst->isLoad()
206  ? _gpuDynInst->exec_mask : wf->execMask();
207 
208  if (NumDwords == 1) {
209  int vgprIdx = cu->registerManager->mapVgpr(wf, _opIdx);
210  vrfData[0] = &cu->vrf[wf->simdId]->readWriteable(vgprIdx);
211  assert(vrfData[0]);
212  auto reg_file_vgpr = vrfData[0]->template as<VecElemU32>();
213  auto vgpr = vecReg.template as<DataType>();
214 
215  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
216  if (exec_mask[lane] || _gpuDynInst->ignoreExec()) {
217  std::memcpy((void*)&reg_file_vgpr[lane],
218  (void*)&vgpr[lane], sizeof(DataType));
219  }
220  }
221 
222  DPRINTF(GPUVRF, "Write v[%d]\n", vgprIdx);
223  cu->vrf[wf->simdId]->printReg(wf, vgprIdx);
224  } else if (NumDwords == 2) {
225  int vgprIdx0 = cu->registerManager->mapVgpr(wf, _opIdx);
226  int vgprIdx1 = cu->registerManager->mapVgpr(wf, _opIdx + 1);
227  vrfData[0] = &cu->vrf[wf->simdId]->readWriteable(vgprIdx0);
228  vrfData[1] = &cu->vrf[wf->simdId]->readWriteable(vgprIdx1);
229  assert(vrfData[0]);
230  assert(vrfData[1]);
231  auto reg_file_vgpr0 = vrfData[0]->template as<VecElemU32>();
232  auto reg_file_vgpr1 = vrfData[1]->template as<VecElemU32>();
233  auto vgpr = vecReg.template as<VecElemU64>();
234 
235  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
236  if (exec_mask[lane] || _gpuDynInst->ignoreExec()) {
237  reg_file_vgpr0[lane] = ((VecElemU32*)&vgpr[lane])[0];
238  reg_file_vgpr1[lane] = ((VecElemU32*)&vgpr[lane])[1];
239  }
240  }
241 
242  DPRINTF(GPUVRF, "Write v[%d:%d]\n", vgprIdx0, vgprIdx1);
243  cu->vrf[wf->simdId]->printReg(wf, vgprIdx0);
244  cu->vrf[wf->simdId]->printReg(wf, vgprIdx1);
245  }
246  }
247 
248  void
250  {
251  negMod = true;
252  }
253 
254  void
256  {
257  absMod = true;
258  }
259 
265  template<bool Condition = (NumDwords == 1 || NumDwords == 2) && Const>
266  typename std::enable_if_t<Condition, const DataType>
267  operator[](size_t idx) const
268  {
269  assert(idx < NumVecElemPerVecReg);
270 
271  if (scalar) {
272  DataType ret_val = scRegData.rawData();
273 
274  if (absMod) {
275  assert(std::is_floating_point_v<DataType>);
276  ret_val = std::fabs(ret_val);
277  }
278 
279  if (negMod) {
280  assert(std::is_floating_point_v<DataType>);
281  ret_val = -ret_val;
282  }
283 
284  return ret_val;
285  } else {
286  auto vgpr = vecReg.template as<DataType>();
287  DataType ret_val = vgpr[idx];
288 
289  if (absMod) {
290  assert(std::is_floating_point_v<DataType>);
291  ret_val = std::fabs(ret_val);
292  }
293 
294  if (negMod) {
295  assert(std::is_floating_point_v<DataType>);
296  ret_val = -ret_val;
297  }
298 
299  return ret_val;
300  }
301  }
302 
308  template<bool Condition = (NumDwords == 1 || NumDwords == 2) && !Const>
309  typename std::enable_if_t<Condition, DataType&>
310  operator[](size_t idx)
311  {
312  assert(!scalar);
313  assert(idx < NumVecElemPerVecReg);
314 
315  return vecReg.template as<DataType>()[idx];
316  }
317 
318  private:
323  void
325  {
326  scalar = true;
327  scRegData.read();
328  }
329 
330  using VecRegCont =
332 
336  bool scalar;
343  bool absMod;
344  bool negMod;
360  std::array<VecRegContainerU32*, NumDwords> vrfData;
361  };
362 
363  template<typename DataType, bool Const,
364  size_t NumDwords = sizeof(DataType) / sizeof(ScalarRegU32)>
365  class ScalarOperand final : public Operand
366  {
367  static_assert(NumDwords >= 1 && NumDwords <= MaxOperandDwords,
368  "Incorrect number of DWORDS for GCN3 operand.");
369  public:
370  ScalarOperand() = delete;
371 
372  ScalarOperand(GPUDynInstPtr gpuDynInst, int opIdx)
373  : Operand(gpuDynInst, opIdx)
374  {
375  std::memset(srfData.data(), 0, NumDwords * sizeof(ScalarRegU32));
376  }
377 
379  {
380  }
381 
389  template<bool Condition = NumDwords == 1 || NumDwords == 2>
390  typename std::enable_if_t<Condition, DataType>
391  rawData() const
392  {
393  assert(sizeof(DataType) <= sizeof(srfData));
394  DataType raw_data((DataType)0);
395  std::memcpy((void*)&raw_data, (void*)srfData.data(),
396  sizeof(DataType));
397 
398  return raw_data;
399  }
400 
401  void*
403  {
404  return (void*)srfData.data();
405  }
406 
407  void
408  read() override
409  {
410  Wavefront *wf = _gpuDynInst->wavefront();
411  ComputeUnit *cu = _gpuDynInst->computeUnit();
412 
413  if (!isScalarReg(_opIdx)) {
414  readSpecialVal();
415  } else {
416  for (auto i = 0; i < NumDwords; ++i) {
417  int sgprIdx = regIdx(i);
418  srfData[i] = cu->srf[wf->simdId]->read(sgprIdx);
419  DPRINTF(GPUSRF, "Read s[%d]\n", sgprIdx);
420  cu->srf[wf->simdId]->printReg(wf, sgprIdx);
421  }
422  }
423  }
424 
425  void
426  write() override
427  {
428  Wavefront *wf = _gpuDynInst->wavefront();
429  ComputeUnit *cu = _gpuDynInst->computeUnit();
430 
431  if (!isScalarReg(_opIdx)) {
432  if (_opIdx == REG_EXEC_LO) {
433  ScalarRegU64 new_exec_mask_val
434  = wf->execMask().to_ullong();
435  if (NumDwords == 1) {
436  std::memcpy((void*)&new_exec_mask_val,
437  (void*)srfData.data(), sizeof(VecElemU32));
438  } else if (NumDwords == 2) {
439  std::memcpy((void*)&new_exec_mask_val,
440  (void*)srfData.data(), sizeof(VecElemU64));
441  } else {
442  panic("Trying to write more than 2 DWORDS to EXEC\n");
443  }
444  VectorMask new_exec_mask(new_exec_mask_val);
445  wf->execMask() = new_exec_mask;
446  DPRINTF(GPUSRF, "Write EXEC\n");
447  DPRINTF(GPUSRF, "EXEC = %#x\n", new_exec_mask_val);
448  } else if (_opIdx == REG_EXEC_HI) {
453  assert(NumDwords == 1);
454  ScalarRegU32 new_exec_mask_hi_val(0);
455  ScalarRegU64 new_exec_mask_val
456  = wf->execMask().to_ullong();
457  std::memcpy((void*)&new_exec_mask_hi_val,
458  (void*)srfData.data(), sizeof(new_exec_mask_hi_val));
459  replaceBits(new_exec_mask_val, 63, 32,
460  new_exec_mask_hi_val);
461  VectorMask new_exec_mask(new_exec_mask_val);
462  wf->execMask() = new_exec_mask;
463  DPRINTF(GPUSRF, "Write EXEC\n");
464  DPRINTF(GPUSRF, "EXEC = %#x\n", new_exec_mask_val);
465  } else {
466  _gpuDynInst->writeMiscReg(_opIdx, srfData[0]);
467  }
468  } else {
469  for (auto i = 0; i < NumDwords; ++i) {
470  int sgprIdx = regIdx(i);
471  auto &sgpr = cu->srf[wf->simdId]->readWriteable(sgprIdx);
472  if (_gpuDynInst->isLoad()) {
473  assert(sizeof(DataType) <= sizeof(ScalarRegU64));
474  sgpr = reinterpret_cast<ScalarRegU32*>(
475  _gpuDynInst->scalar_data)[i];
476  } else {
477  sgpr = srfData[i];
478  }
479  DPRINTF(GPUSRF, "Write s[%d]\n", sgprIdx);
480  cu->srf[wf->simdId]->printReg(wf, sgprIdx);
481  }
482  }
483  }
484 
488  template<bool Condition = NumDwords == 1 || NumDwords == 2>
489  typename std::enable_if_t<Condition, void>
490  setBit(int bit, int bit_val)
491  {
492  DataType &sgpr = *((DataType*)srfData.data());
493  replaceBits(sgpr, bit, bit_val);
494  }
495 
496  template<bool Condition = (NumDwords == 1 || NumDwords == 2) && !Const>
497  typename std::enable_if_t<Condition, ScalarOperand&>
498  operator=(DataType rhs)
499  {
500  std::memcpy((void*)srfData.data(), (void*)&rhs, sizeof(DataType));
501  return *this;
502  }
503 
504  private:
511  void
513  {
514  assert(NumDwords == 1 || NumDwords == 2);
515 
516  switch(_opIdx) {
517  case REG_EXEC_LO:
518  {
519  if (NumDwords == 1) {
520  ScalarRegU32 exec_mask = _gpuDynInst->wavefront()->
521  execMask().to_ulong();
522  std::memcpy((void*)srfData.data(), (void*)&exec_mask,
523  sizeof(exec_mask));
524  DPRINTF(GPUSRF, "Read EXEC\n");
525  DPRINTF(GPUSRF, "EXEC = %#x\n", exec_mask);
526  } else {
527  assert(NumDwords == 2);
528  ScalarRegU64 exec_mask = _gpuDynInst->wavefront()->
529  execMask().to_ullong();
530  std::memcpy((void*)srfData.data(), (void*)&exec_mask,
531  sizeof(exec_mask));
532  DPRINTF(GPUSRF, "Read EXEC\n");
533  DPRINTF(GPUSRF, "EXEC = %#x\n", exec_mask);
534  }
535  }
536  break;
537  case REG_EXEC_HI:
538  {
543  assert(NumDwords == 1);
544  ScalarRegU64 exec_mask = _gpuDynInst->wavefront()
545  ->execMask().to_ullong();
546 
547  ScalarRegU32 exec_mask_hi = bits(exec_mask, 63, 32);
548  std::memcpy((void*)srfData.data(), (void*)&exec_mask_hi,
549  sizeof(exec_mask_hi));
550  DPRINTF(GPUSRF, "Read EXEC_HI\n");
551  DPRINTF(GPUSRF, "EXEC_HI = %#x\n", exec_mask_hi);
552  }
553  break;
554  case REG_SRC_SWDA:
555  case REG_SRC_DPP:
556  case REG_SRC_LITERAL:
557  assert(NumDwords == 1);
558  srfData[0] = _gpuDynInst->srcLiteral();
559  break;
560  case REG_POS_HALF:
561  {
562  typename OpTraits<DataType>::FloatT pos_half = 0.5;
563  std::memcpy((void*)srfData.data(), (void*)&pos_half,
564  sizeof(pos_half));
565 
566  }
567  break;
568  case REG_NEG_HALF:
569  {
570  typename OpTraits<DataType>::FloatT neg_half = -0.5;
571  std::memcpy((void*)srfData.data(), (void*)&neg_half,
572  sizeof(neg_half));
573  }
574  break;
575  case REG_POS_ONE:
576  {
577  typename OpTraits<DataType>::FloatT pos_one = 1.0;
578  std::memcpy(srfData.data(), &pos_one, sizeof(pos_one));
579  }
580  break;
581  case REG_NEG_ONE:
582  {
583  typename OpTraits<DataType>::FloatT neg_one = -1.0;
584  std::memcpy(srfData.data(), &neg_one, sizeof(neg_one));
585  }
586  break;
587  case REG_POS_TWO:
588  {
589  typename OpTraits<DataType>::FloatT pos_two = 2.0;
590  std::memcpy(srfData.data(), &pos_two, sizeof(pos_two));
591  }
592  break;
593  case REG_NEG_TWO:
594  {
595  typename OpTraits<DataType>::FloatT neg_two = -2.0;
596  std::memcpy(srfData.data(), &neg_two, sizeof(neg_two));
597  }
598  break;
599  case REG_POS_FOUR:
600  {
601  typename OpTraits<DataType>::FloatT pos_four = 4.0;
602  std::memcpy(srfData.data(), &pos_four, sizeof(pos_four));
603  }
604  break;
605  case REG_NEG_FOUR:
606  {
607  typename OpTraits<DataType>::FloatT neg_four = -4.0;
608  std::memcpy((void*)srfData.data(), (void*)&neg_four ,
609  sizeof(neg_four));
610  }
611  break;
612  case REG_PI:
613  {
614  assert(sizeof(DataType) == sizeof(ScalarRegF64)
615  || sizeof(DataType) == sizeof(ScalarRegF32));
616 
617  const ScalarRegU32 pi_u32(0x3e22f983UL);
618  const ScalarRegU64 pi_u64(0x3fc45f306dc9c882ULL);
619 
620  if (sizeof(DataType) == sizeof(ScalarRegF64)) {
621  std::memcpy((void*)srfData.data(),
622  (void*)&pi_u64, sizeof(pi_u64));
623  } else {
624  std::memcpy((void*)srfData.data(),
625  (void*)&pi_u32, sizeof(pi_u32));
626  }
627  }
628  break;
629  default:
630  {
631  assert(sizeof(DataType) <= sizeof(srfData));
632  DataType misc_val(0);
633  if (isConstVal(_opIdx)) {
634  misc_val = (DataType)_gpuDynInst
635  ->readConstVal<DataType>(_opIdx);
636  } else {
637  misc_val = (DataType)_gpuDynInst->readMiscReg(_opIdx);
638  }
639  std::memcpy((void*)srfData.data(), (void*)&misc_val,
640  sizeof(DataType));
641  }
642  }
643  }
644 
650  int
651  regIdx(int dword) const
652  {
653  Wavefront *wf = _gpuDynInst->wavefront();
654  ComputeUnit *cu = _gpuDynInst->computeUnit();
655  int sgprIdx(-1);
656 
657  if (_opIdx == REG_VCC_LO) {
658  sgprIdx = cu->registerManager
659  ->mapSgpr(wf, wf->reservedScalarRegs - 2 + dword);
660  } else if (_opIdx == REG_FLAT_SCRATCH_HI) {
661  sgprIdx = cu->registerManager
662  ->mapSgpr(wf, wf->reservedScalarRegs - 3 + dword);
663  } else if (_opIdx == REG_FLAT_SCRATCH_LO) {
664  assert(NumDwords == 1);
665  sgprIdx = cu->registerManager
666  ->mapSgpr(wf, wf->reservedScalarRegs - 4 + dword);
667  } else {
668  sgprIdx = cu->registerManager->mapSgpr(wf, _opIdx + dword);
669  }
670 
671  assert(sgprIdx > -1);
672 
673  return sgprIdx;
674  }
675 
684  std::array<ScalarRegU32, NumDwords> srfData;
685  };
686 
687  // typedefs for the various sizes/types of scalar operands
701  // non-writeable versions of scalar operands
715  // typedefs for the various sizes/types of vector operands
730  // non-writeable versions of vector operands
745 }
746 
747 } // namespace gem5
748 
749 #endif // __ARCH_GCN3_OPERAND_HH__
gem5::Gcn3ISA::Operand::Operand
Operand()=delete
gem5::Gcn3ISA::REG_NEG_TWO
@ REG_NEG_TWO
Definition: gpu_registers.hh:119
gem5::Gcn3ISA::VecOperand::scalar
bool scalar
whether this operand a scalar or not.
Definition: operand.hh:336
gem5::Gcn3ISA::REG_SRC_DPP
@ REG_SRC_DPP
Definition: gpu_registers.hh:125
gem5::Gcn3ISA::REG_EXEC_LO
@ REG_EXEC_LO
Definition: gpu_registers.hh:76
gem5::Gcn3ISA::Operand::Operand
Operand(GPUDynInstPtr gpuDynInst, int opIdx)
Definition: operand.hh:68
gem5::Gcn3ISA::ScalarOperand::rawDataPtr
void * rawDataPtr()
Definition: operand.hh:402
gem5::Gcn3ISA::isScalarReg
bool isScalarReg(int opIdx)
Definition: registers.cc:216
gem5::Gcn3ISA::VecOperand::negMod
bool negMod
Definition: operand.hh:344
gem5::Gcn3ISA::Operand::write
virtual void write()=0
gem5::Gcn3ISA::ScalarRegF32
float ScalarRegF32
Definition: gpu_registers.hh:155
gem5::Gcn3ISA::OpTraits::FloatT
float FloatT
Definition: operand.hh:59
gem5::ComputeUnit::srf
std::vector< ScalarRegisterFile * > srf
Definition: compute_unit.hh:297
gem5::Gcn3ISA::VecOperand::readScalar
void readScalar()
if we determine that this operand is a scalar (reg or constant) then we read the scalar data into the...
Definition: operand.hh:324
gem5::Gcn3ISA::VecOperand::~VecOperand
~VecOperand()
Definition: operand.hh:117
gem5::Gcn3ISA::VecElemU32
uint32_t VecElemU32
Definition: gpu_registers.hh:165
gem5::Gcn3ISA::ScalarOperand::read
void read() override
Definition: operand.hh:408
gem5::Gcn3ISA::REG_POS_TWO
@ REG_POS_TWO
Definition: gpu_registers.hh:118
gem5::Gcn3ISA::ScalarOperand::ScalarOperand
ScalarOperand(GPUDynInstPtr gpuDynInst, int opIdx)
Definition: operand.hh:372
gem5::Wavefront
Definition: wavefront.hh:60
gpu_registers.hh
gem5::replaceBits
constexpr void replaceBits(T &val, unsigned first, unsigned last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
Definition: bitfield.hh:197
gem5::Gcn3ISA::REG_EXEC_HI
@ REG_EXEC_HI
Definition: gpu_registers.hh:77
gem5::VectorMask
std::bitset< std::numeric_limits< unsigned long long >::digits > VectorMask
Definition: misc.hh:45
gem5::Gcn3ISA::REG_SRC_LITERAL
@ REG_SRC_LITERAL
Definition: gpu_registers.hh:130
gem5::Gcn3ISA::ScalarOperand::~ScalarOperand
~ScalarOperand()
Definition: operand.hh:378
gem5::Gcn3ISA::Operand::_opIdx
int _opIdx
op selector value for this operand.
Definition: operand.hh:93
gem5::Gcn3ISA::REG_NEG_FOUR
@ REG_NEG_FOUR
Definition: gpu_registers.hh:121
gem5::Gcn3ISA::VecOperand::operator[]
std::enable_if_t< Condition, DataType & > operator[](size_t idx)
setter [] operator.
Definition: operand.hh:310
gem5::Gcn3ISA::OpTraits< ScalarRegU64 >::FloatT
double FloatT
Definition: operand.hh:61
gem5::Gcn3ISA::VecOperand
Definition: operand.hh:101
gem5::Gcn3ISA::REG_NEG_ONE
@ REG_NEG_ONE
Definition: gpu_registers.hh:117
gem5::Gcn3ISA::VecOperand::VecRegCont
VecRegContainer< sizeof(DataType) *NumVecElemPerVecReg > VecRegCont
Definition: operand.hh:331
gem5::Gcn3ISA::Operand
Definition: operand.hh:63
gem5::Gcn3ISA::REG_VCC_LO
@ REG_VCC_LO
Definition: gpu_registers.hh:56
gem5::Gcn3ISA::VecOperand::absMod
bool absMod
absolute value and negative modifiers.
Definition: operand.hh:343
gem5::Gcn3ISA::ScalarOperand::regIdx
int regIdx(int dword) const
for scalars we need to do some extra work to figure out how to map the op selector to the sgpr idx be...
Definition: operand.hh:651
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::Gcn3ISA::VecOperand::write
void write() override
write to the vrf.
Definition: operand.hh:198
gem5::Gcn3ISA::VecOperand::readSrc
void readSrc()
certain vector operands can read from the vrf/srf or constants.
Definition: operand.hh:130
gem5::ComputeUnit::vrf
std::vector< VectorRegisterFile * > vrf
Definition: compute_unit.hh:295
wavefront.hh
gem5::RegisterManager::mapSgpr
int mapSgpr(Wavefront *w, int sgprIndex)
Definition: register_manager.cc:102
gem5::ComputeUnit
Definition: compute_unit.hh:201
gem5::Gcn3ISA::VecOperand::negModifier
void negModifier()
Definition: operand.hh:249
gem5::Gcn3ISA::Operand::read
virtual void read()=0
read from and write to the underlying register(s) that this operand is referring to.
vector_register_file.hh
gem5::VecRegContainer
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
Definition: vec_reg.hh:123
gem5::Wavefront::reservedScalarRegs
int reservedScalarRegs
Definition: wavefront.hh:196
gem5::Gcn3ISA::isVectorReg
bool isVectorReg(int opIdx)
Definition: registers.cc:229
gem5::Gcn3ISA::OpTraits< ScalarRegF64 >::FloatT
double FloatT
Definition: operand.hh:60
gem5::Gcn3ISA::ScalarOperand::operator=
std::enable_if_t< Condition, ScalarOperand & > operator=(DataType rhs)
Definition: operand.hh:498
gem5::Gcn3ISA::REG_FLAT_SCRATCH_LO
@ REG_FLAT_SCRATCH_LO
Definition: gpu_registers.hh:52
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Gcn3ISA::opSelectorToRegIdx
int opSelectorToRegIdx(int opIdx, int numScalarRegs)
Definition: registers.cc:122
gem5::Gcn3ISA::ScalarOperand::write
void write() override
Definition: operand.hh:426
gem5::Gcn3ISA::NumVecElemPerVecReg
const int NumVecElemPerVecReg(64)
gem5::Gcn3ISA::ScalarOperand
Definition: operand.hh:97
gem5::Gcn3ISA::ScalarOperand::ScalarOperand
ScalarOperand()=delete
gem5::Gcn3ISA::VecOperand::vrfData
std::array< VecRegContainerU32 *, NumDwords > vrfData
pointers to the underlyding registers (i.e., the actual registers in the register file).
Definition: operand.hh:360
gem5::Gcn3ISA::VecOperand::scRegData
ScalarOperand< DataType, Const, NumDwords > scRegData
for src operands that read scalars (i.e., scalar regs or a scalar constant).
Definition: operand.hh:355
gem5::ComputeUnit::registerManager
RegisterManager * registerManager
Definition: compute_unit.hh:278
gem5::Gcn3ISA::REG_FLAT_SCRATCH_HI
@ REG_FLAT_SCRATCH_HI
Definition: gpu_registers.hh:53
scalar_register_file.hh
gem5::Gcn3ISA::VecOperand::absModifier
void absModifier()
Definition: operand.hh:255
gem5::Gcn3ISA::VecOperand::operator[]
std::enable_if_t< Condition, const DataType > operator[](size_t idx) const
getter [] operator.
Definition: operand.hh:267
gem5::Gcn3ISA::REG_NEG_HALF
@ REG_NEG_HALF
Definition: gpu_registers.hh:115
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::Wavefront::execMask
VectorMask & execMask()
Definition: wavefront.cc:1375
gem5::Gcn3ISA::ScalarRegU64
uint64_t ScalarRegU64
Definition: gpu_registers.hh:156
gem5::Gcn3ISA::VecOperand::read
void read() override
read from the vrf.
Definition: operand.hh:146
gem5::Gcn3ISA::VecOperand::VecOperand
VecOperand()=delete
gem5::RegisterManager::mapVgpr
int mapVgpr(Wavefront *w, int vgprIndex)
Definition: register_manager.cc:95
gem5::GPUDynInstPtr
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition: misc.hh:49
vec_reg.hh
gem5::Gcn3ISA::REG_POS_HALF
@ REG_POS_HALF
Definition: gpu_registers.hh:114
gem5::Gcn3ISA::Operand::_gpuDynInst
GPUDynInstPtr _gpuDynInst
instruction object that owns this operand
Definition: operand.hh:86
gem5::Gcn3ISA::REG_POS_FOUR
@ REG_POS_FOUR
Definition: gpu_registers.hh:120
gem5::Gcn3ISA::ScalarOperand::srfData
std::array< ScalarRegU32, NumDwords > srfData
in GCN3 each register is represented as a 32b unsigned value, however operands may require up to 16 r...
Definition: operand.hh:684
gem5::Gcn3ISA::MaxOperandDwords
constexpr size_t MaxOperandDwords(16)
gem5::Gcn3ISA::ScalarRegF64
double ScalarRegF64
Definition: gpu_registers.hh:158
gem5::Gcn3ISA::REG_POS_ONE
@ REG_POS_ONE
Definition: gpu_registers.hh:116
gem5::Gcn3ISA::VecOperand::vecReg
VecRegCont vecReg
this holds all the operand data in a single vector register object (i.e., if an operand is 64b,...
Definition: operand.hh:350
gem5::Gcn3ISA::ScalarOperand::setBit
std::enable_if_t< Condition, void > setBit(int bit, int bit_val)
bit access to scalar data.
Definition: operand.hh:490
gem5::Gcn3ISA::REG_SRC_SWDA
@ REG_SRC_SWDA
Definition: gpu_registers.hh:124
gem5::VecRegContainer::zero
void zero()
Zero the container.
Definition: vec_reg.hh:142
gem5::Gcn3ISA::OpTraits
convenience traits so we can automatically infer the correct FP type without looking at the number of...
Definition: operand.hh:59
gem5::Gcn3ISA::VecOperand::VecOperand
VecOperand(GPUDynInstPtr gpuDynInst, int opIdx)
Definition: operand.hh:109
gem5::Gcn3ISA::REG_PI
@ REG_PI
Definition: gpu_registers.hh:122
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::Gcn3ISA::isConstVal
bool isConstVal(int opIdx)
Definition: registers.cc:185
gem5::Gcn3ISA::ScalarOperand::readSpecialVal
void readSpecialVal()
we have determined that we are not reading our scalar operand data from the register file,...
Definition: operand.hh:512
gem5::Gcn3ISA::ScalarRegU32
uint32_t ScalarRegU32
Definition: gpu_registers.hh:153
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::Gcn3ISA::ScalarOperand::rawData
std::enable_if_t< Condition, DataType > rawData() const
we store scalar data in a std::array, however if we need the full operand data we use this method to ...
Definition: operand.hh:391
gem5::Gcn3ISA::VecElemU64
uint64_t VecElemU64
Definition: gpu_registers.hh:168
gem5::Wavefront::simdId
const int simdId
Definition: wavefront.hh:99

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