gem5  v21.1.0.2
operand.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2017-2021 Advanced Micro Devices, Inc.
3  * All rights reserved.
4  *
5  * For use for simulation and test purposes only
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions are met:
9  *
10  * 1. Redistributions of source code must retain the above copyright notice,
11  * this list of conditions and the following disclaimer.
12  *
13  * 2. Redistributions in binary form must reproduce the above copyright notice,
14  * this list of conditions and the following disclaimer in the documentation
15  * and/or other materials provided with the distribution.
16  *
17  * 3. Neither the name of the copyright holder nor the names of its
18  * contributors may be used to endorse or promote products derived from this
19  * software without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31  * POSSIBILITY OF SUCH DAMAGE.
32  */
33 
34 #ifndef __ARCH_GCN3_OPERAND_HH__
35 #define __ARCH_GCN3_OPERAND_HH__
36 
37 #include <array>
38 
40 #include "arch/generic/vec_reg.hh"
43 #include "gpu-compute/wavefront.hh"
44 
45 namespace gem5
46 {
47 
54 namespace Gcn3ISA
55 {
61  template<typename T> struct OpTraits { typedef float FloatT; };
62  template<> struct OpTraits<ScalarRegF64> { typedef double FloatT; };
63  template<> struct OpTraits<ScalarRegU64> { typedef double FloatT; };
64 
65  class Operand
66  {
67  public:
68  Operand() = delete;
69 
70  Operand(GPUDynInstPtr gpuDynInst, int opIdx)
71  : _gpuDynInst(gpuDynInst), _opIdx(opIdx)
72  {
73  assert(_gpuDynInst);
74  assert(_opIdx >= 0);
75  }
76 
81  virtual void read() = 0;
82  virtual void write() = 0;
83 
84  protected:
95  int _opIdx;
96  };
97 
98  template<typename DataType, bool Const, size_t NumDwords>
100 
101  template<typename DataType, bool Const,
102  size_t NumDwords = sizeof(DataType) / sizeof(VecElemU32)>
103  class VecOperand final : public Operand
104  {
105  static_assert(NumDwords >= 1 && NumDwords <= MaxOperandDwords,
106  "Incorrect number of DWORDS for GCN3 operand.");
107 
108  public:
109  VecOperand() = delete;
110 
111  VecOperand(GPUDynInstPtr gpuDynInst, int opIdx)
112  : Operand(gpuDynInst, opIdx), scalar(false), absMod(false),
113  negMod(false), scRegData(gpuDynInst, _opIdx),
114  vrfData{{ nullptr }}
115  {
116  vecReg.zero();
117  }
118 
120  {
121  }
122 
131  void
133  {
134  if (isVectorReg(_opIdx)) {
136  ->reservedScalarRegs);
137  read();
138  } else {
139  readScalar();
140  }
141  }
142 
147  void
148  read() override
149  {
150  assert(_gpuDynInst);
151  assert(_gpuDynInst->wavefront());
152  assert(_gpuDynInst->computeUnit());
153  Wavefront *wf = _gpuDynInst->wavefront();
154  ComputeUnit *cu = _gpuDynInst->computeUnit();
155 
156  for (auto i = 0; i < NumDwords; ++i) {
157  int vgprIdx = cu->registerManager->mapVgpr(wf, _opIdx + i);
158  vrfData[i] = &cu->vrf[wf->simdId]->readWriteable(vgprIdx);
159 
160  DPRINTF(GPUVRF, "Read v[%d]\n", vgprIdx);
161  cu->vrf[wf->simdId]->printReg(wf, vgprIdx);
162  }
163 
164  if (NumDwords == 1) {
165  assert(vrfData[0]);
166  auto vgpr = vecReg.template as<DataType>();
167  auto reg_file_vgpr = vrfData[0]->template as<VecElemU32>();
168  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
169  std::memcpy((void*)&vgpr[lane],
170  (void*)&reg_file_vgpr[lane], sizeof(DataType));
171  }
172  } else if (NumDwords == 2) {
173  assert(vrfData[0]);
174  assert(vrfData[1]);
175  auto vgpr = vecReg.template as<VecElemU64>();
176  auto reg_file_vgpr0 = vrfData[0]->template as<VecElemU32>();
177  auto reg_file_vgpr1 = vrfData[1]->template as<VecElemU32>();
178 
179  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
180  VecElemU64 tmp_val(0);
181  ((VecElemU32*)&tmp_val)[0] = reg_file_vgpr0[lane];
182  ((VecElemU32*)&tmp_val)[1] = reg_file_vgpr1[lane];
183  vgpr[lane] = tmp_val;
184  }
185  }
186  }
187 
199  void
200  write() override
201  {
202  assert(_gpuDynInst);
203  assert(_gpuDynInst->wavefront());
204  assert(_gpuDynInst->computeUnit());
205  Wavefront *wf = _gpuDynInst->wavefront();
206  ComputeUnit *cu = _gpuDynInst->computeUnit();
207  VectorMask &exec_mask = _gpuDynInst->isLoad()
208  ? _gpuDynInst->exec_mask : wf->execMask();
209 
210  if (NumDwords == 1) {
211  int vgprIdx = cu->registerManager->mapVgpr(wf, _opIdx);
212  vrfData[0] = &cu->vrf[wf->simdId]->readWriteable(vgprIdx);
213  assert(vrfData[0]);
214  auto reg_file_vgpr = vrfData[0]->template as<VecElemU32>();
215  auto vgpr = vecReg.template as<DataType>();
216 
217  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
218  if (exec_mask[lane] || _gpuDynInst->ignoreExec()) {
219  std::memcpy((void*)&reg_file_vgpr[lane],
220  (void*)&vgpr[lane], sizeof(DataType));
221  }
222  }
223 
224  DPRINTF(GPUVRF, "Write v[%d]\n", vgprIdx);
225  cu->vrf[wf->simdId]->printReg(wf, vgprIdx);
226  } else if (NumDwords == 2) {
227  int vgprIdx0 = cu->registerManager->mapVgpr(wf, _opIdx);
228  int vgprIdx1 = cu->registerManager->mapVgpr(wf, _opIdx + 1);
229  vrfData[0] = &cu->vrf[wf->simdId]->readWriteable(vgprIdx0);
230  vrfData[1] = &cu->vrf[wf->simdId]->readWriteable(vgprIdx1);
231  assert(vrfData[0]);
232  assert(vrfData[1]);
233  auto reg_file_vgpr0 = vrfData[0]->template as<VecElemU32>();
234  auto reg_file_vgpr1 = vrfData[1]->template as<VecElemU32>();
235  auto vgpr = vecReg.template as<VecElemU64>();
236 
237  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
238  if (exec_mask[lane] || _gpuDynInst->ignoreExec()) {
239  reg_file_vgpr0[lane] = ((VecElemU32*)&vgpr[lane])[0];
240  reg_file_vgpr1[lane] = ((VecElemU32*)&vgpr[lane])[1];
241  }
242  }
243 
244  DPRINTF(GPUVRF, "Write v[%d:%d]\n", vgprIdx0, vgprIdx1);
245  cu->vrf[wf->simdId]->printReg(wf, vgprIdx0);
246  cu->vrf[wf->simdId]->printReg(wf, vgprIdx1);
247  }
248  }
249 
250  void
252  {
253  negMod = true;
254  }
255 
256  void
258  {
259  absMod = true;
260  }
261 
267  template<bool Condition = (NumDwords == 1 || NumDwords == 2) && Const>
268  typename std::enable_if_t<Condition, const DataType>
269  operator[](size_t idx) const
270  {
271  assert(idx < NumVecElemPerVecReg);
272 
273  if (scalar) {
274  DataType ret_val = scRegData.rawData();
275 
276  if (absMod) {
277  assert(std::is_floating_point<DataType>::value);
278  ret_val = std::fabs(ret_val);
279  }
280 
281  if (negMod) {
282  assert(std::is_floating_point<DataType>::value);
283  ret_val = -ret_val;
284  }
285 
286  return ret_val;
287  } else {
288  auto vgpr = vecReg.template as<DataType>();
289  DataType ret_val = vgpr[idx];
290 
291  if (absMod) {
292  assert(std::is_floating_point<DataType>::value);
293  ret_val = std::fabs(ret_val);
294  }
295 
296  if (negMod) {
297  assert(std::is_floating_point<DataType>::value);
298  ret_val = -ret_val;
299  }
300 
301  return ret_val;
302  }
303  }
304 
310  template<bool Condition = (NumDwords == 1 || NumDwords == 2) && !Const>
311  typename std::enable_if_t<Condition, DataType&>
312  operator[](size_t idx)
313  {
314  assert(!scalar);
315  assert(idx < NumVecElemPerVecReg);
316 
317  return vecReg.template as<DataType>()[idx];
318  }
319 
320  private:
325  void
327  {
328  scalar = true;
329  scRegData.read();
330  }
331 
332  using VecRegCont =
334 
338  bool scalar;
345  bool absMod;
346  bool negMod;
362  std::array<VecRegContainerU32*, NumDwords> vrfData;
363  };
364 
365  template<typename DataType, bool Const,
366  size_t NumDwords = sizeof(DataType) / sizeof(ScalarRegU32)>
367  class ScalarOperand final : public Operand
368  {
369  static_assert(NumDwords >= 1 && NumDwords <= MaxOperandDwords,
370  "Incorrect number of DWORDS for GCN3 operand.");
371  public:
372  ScalarOperand() = delete;
373 
374  ScalarOperand(GPUDynInstPtr gpuDynInst, int opIdx)
375  : Operand(gpuDynInst, opIdx)
376  {
377  std::memset(srfData.data(), 0, NumDwords * sizeof(ScalarRegU32));
378  }
379 
381  {
382  }
383 
391  template<bool Condition = NumDwords == 1 || NumDwords == 2>
392  typename std::enable_if_t<Condition, DataType>
393  rawData() const
394  {
395  assert(sizeof(DataType) <= sizeof(srfData));
396  DataType raw_data((DataType)0);
397  std::memcpy((void*)&raw_data, (void*)srfData.data(),
398  sizeof(DataType));
399 
400  return raw_data;
401  }
402 
403  void*
405  {
406  return (void*)srfData.data();
407  }
408 
409  void
410  read() override
411  {
412  Wavefront *wf = _gpuDynInst->wavefront();
413  ComputeUnit *cu = _gpuDynInst->computeUnit();
414 
415  if (!isScalarReg(_opIdx)) {
416  readSpecialVal();
417  } else {
418  for (auto i = 0; i < NumDwords; ++i) {
419  int sgprIdx = regIdx(i);
420  srfData[i] = cu->srf[wf->simdId]->read(sgprIdx);
421  DPRINTF(GPUSRF, "Read s[%d]\n", sgprIdx);
422  cu->srf[wf->simdId]->printReg(wf, sgprIdx);
423  }
424  }
425  }
426 
427  void
428  write() override
429  {
430  Wavefront *wf = _gpuDynInst->wavefront();
431  ComputeUnit *cu = _gpuDynInst->computeUnit();
432 
433  if (!isScalarReg(_opIdx)) {
434  if (_opIdx == REG_EXEC_LO) {
435  ScalarRegU64 new_exec_mask_val
436  = wf->execMask().to_ullong();
437  if (NumDwords == 1) {
438  std::memcpy((void*)&new_exec_mask_val,
439  (void*)srfData.data(), sizeof(VecElemU32));
440  } else if (NumDwords == 2) {
441  std::memcpy((void*)&new_exec_mask_val,
442  (void*)srfData.data(), sizeof(VecElemU64));
443  } else {
444  panic("Trying to write more than 2 DWORDS to EXEC\n");
445  }
446  VectorMask new_exec_mask(new_exec_mask_val);
447  wf->execMask() = new_exec_mask;
448  DPRINTF(GPUSRF, "Write EXEC\n");
449  DPRINTF(GPUSRF, "EXEC = %#x\n", new_exec_mask_val);
450  } else if (_opIdx == REG_EXEC_HI) {
455  assert(NumDwords == 1);
456  ScalarRegU32 new_exec_mask_hi_val(0);
457  ScalarRegU64 new_exec_mask_val
458  = wf->execMask().to_ullong();
459  std::memcpy((void*)&new_exec_mask_hi_val,
460  (void*)srfData.data(), sizeof(new_exec_mask_hi_val));
461  replaceBits(new_exec_mask_val, 63, 32,
462  new_exec_mask_hi_val);
463  VectorMask new_exec_mask(new_exec_mask_val);
464  wf->execMask() = new_exec_mask;
465  DPRINTF(GPUSRF, "Write EXEC\n");
466  DPRINTF(GPUSRF, "EXEC = %#x\n", new_exec_mask_val);
467  } else {
468  _gpuDynInst->writeMiscReg(_opIdx, srfData[0]);
469  }
470  } else {
471  for (auto i = 0; i < NumDwords; ++i) {
472  int sgprIdx = regIdx(i);
473  auto &sgpr = cu->srf[wf->simdId]->readWriteable(sgprIdx);
474  if (_gpuDynInst->isLoad()) {
475  assert(sizeof(DataType) <= sizeof(ScalarRegU64));
476  sgpr = reinterpret_cast<ScalarRegU32*>(
477  _gpuDynInst->scalar_data)[i];
478  } else {
479  sgpr = srfData[i];
480  }
481  DPRINTF(GPUSRF, "Write s[%d]\n", sgprIdx);
482  cu->srf[wf->simdId]->printReg(wf, sgprIdx);
483  }
484  }
485  }
486 
490  template<bool Condition = NumDwords == 1 || NumDwords == 2>
491  typename std::enable_if_t<Condition, void>
492  setBit(int bit, int bit_val)
493  {
494  DataType &sgpr = *((DataType*)srfData.data());
495  replaceBits(sgpr, bit, bit_val);
496  }
497 
498  template<bool Condition = (NumDwords == 1 || NumDwords == 2) && !Const>
499  typename std::enable_if_t<Condition, ScalarOperand&>
500  operator=(DataType rhs)
501  {
502  std::memcpy((void*)srfData.data(), (void*)&rhs, sizeof(DataType));
503  return *this;
504  }
505 
506  private:
513  void
515  {
516  assert(NumDwords == 1 || NumDwords == 2);
517 
518  switch(_opIdx) {
519  case REG_EXEC_LO:
520  {
521  if (NumDwords == 1) {
522  ScalarRegU32 exec_mask = _gpuDynInst->wavefront()->
523  execMask().to_ulong();
524  std::memcpy((void*)srfData.data(), (void*)&exec_mask,
525  sizeof(exec_mask));
526  DPRINTF(GPUSRF, "Read EXEC\n");
527  DPRINTF(GPUSRF, "EXEC = %#x\n", exec_mask);
528  } else {
529  assert(NumDwords == 2);
530  ScalarRegU64 exec_mask = _gpuDynInst->wavefront()->
531  execMask().to_ullong();
532  std::memcpy((void*)srfData.data(), (void*)&exec_mask,
533  sizeof(exec_mask));
534  DPRINTF(GPUSRF, "Read EXEC\n");
535  DPRINTF(GPUSRF, "EXEC = %#x\n", exec_mask);
536  }
537  }
538  break;
539  case REG_EXEC_HI:
540  {
545  assert(NumDwords == 1);
546  ScalarRegU64 exec_mask = _gpuDynInst->wavefront()
547  ->execMask().to_ullong();
548 
549  ScalarRegU32 exec_mask_hi = bits(exec_mask, 63, 32);
550  std::memcpy((void*)srfData.data(), (void*)&exec_mask_hi,
551  sizeof(exec_mask_hi));
552  DPRINTF(GPUSRF, "Read EXEC_HI\n");
553  DPRINTF(GPUSRF, "EXEC_HI = %#x\n", exec_mask_hi);
554  }
555  break;
556  case REG_SRC_SWDA:
557  case REG_SRC_DPP:
558  case REG_SRC_LITERAL:
559  assert(NumDwords == 1);
560  srfData[0] = _gpuDynInst->srcLiteral();
561  break;
562  case REG_POS_HALF:
563  {
564  typename OpTraits<DataType>::FloatT pos_half = 0.5;
565  std::memcpy((void*)srfData.data(), (void*)&pos_half,
566  sizeof(pos_half));
567 
568  }
569  break;
570  case REG_NEG_HALF:
571  {
572  typename OpTraits<DataType>::FloatT neg_half = -0.5;
573  std::memcpy((void*)srfData.data(), (void*)&neg_half,
574  sizeof(neg_half));
575  }
576  break;
577  case REG_POS_ONE:
578  {
579  typename OpTraits<DataType>::FloatT pos_one = 1.0;
580  std::memcpy(srfData.data(), &pos_one, sizeof(pos_one));
581  }
582  break;
583  case REG_NEG_ONE:
584  {
585  typename OpTraits<DataType>::FloatT neg_one = -1.0;
586  std::memcpy(srfData.data(), &neg_one, sizeof(neg_one));
587  }
588  break;
589  case REG_POS_TWO:
590  {
591  typename OpTraits<DataType>::FloatT pos_two = 2.0;
592  std::memcpy(srfData.data(), &pos_two, sizeof(pos_two));
593  }
594  break;
595  case REG_NEG_TWO:
596  {
597  typename OpTraits<DataType>::FloatT neg_two = -2.0;
598  std::memcpy(srfData.data(), &neg_two, sizeof(neg_two));
599  }
600  break;
601  case REG_POS_FOUR:
602  {
603  typename OpTraits<DataType>::FloatT pos_four = 4.0;
604  std::memcpy(srfData.data(), &pos_four, sizeof(pos_four));
605  }
606  break;
607  case REG_NEG_FOUR:
608  {
609  typename OpTraits<DataType>::FloatT neg_four = -4.0;
610  std::memcpy((void*)srfData.data(), (void*)&neg_four ,
611  sizeof(neg_four));
612  }
613  break;
614  case REG_PI:
615  {
616  assert(sizeof(DataType) == sizeof(ScalarRegF64)
617  || sizeof(DataType) == sizeof(ScalarRegF32));
618 
619  const ScalarRegU32 pi_u32(0x3e22f983UL);
620  const ScalarRegU64 pi_u64(0x3fc45f306dc9c882ULL);
621 
622  if (sizeof(DataType) == sizeof(ScalarRegF64)) {
623  std::memcpy((void*)srfData.data(),
624  (void*)&pi_u64, sizeof(pi_u64));
625  } else {
626  std::memcpy((void*)srfData.data(),
627  (void*)&pi_u32, sizeof(pi_u32));
628  }
629  }
630  break;
631  default:
632  {
633  assert(sizeof(DataType) <= sizeof(srfData));
634  DataType misc_val(0);
635  if (isConstVal(_opIdx)) {
636  misc_val = (DataType)_gpuDynInst
637  ->readConstVal<DataType>(_opIdx);
638  } else {
639  misc_val = (DataType)_gpuDynInst->readMiscReg(_opIdx);
640  }
641  std::memcpy((void*)srfData.data(), (void*)&misc_val,
642  sizeof(DataType));
643  }
644  }
645  }
646 
652  int
653  regIdx(int dword) const
654  {
655  Wavefront *wf = _gpuDynInst->wavefront();
656  ComputeUnit *cu = _gpuDynInst->computeUnit();
657  int sgprIdx(-1);
658 
659  if (_opIdx == REG_VCC_LO) {
660  sgprIdx = cu->registerManager
661  ->mapSgpr(wf, wf->reservedScalarRegs - 2 + dword);
662  } else if (_opIdx == REG_FLAT_SCRATCH_HI) {
663  sgprIdx = cu->registerManager
664  ->mapSgpr(wf, wf->reservedScalarRegs - 3 + dword);
665  } else if (_opIdx == REG_FLAT_SCRATCH_LO) {
666  assert(NumDwords == 1);
667  sgprIdx = cu->registerManager
668  ->mapSgpr(wf, wf->reservedScalarRegs - 4 + dword);
669  } else {
670  sgprIdx = cu->registerManager->mapSgpr(wf, _opIdx + dword);
671  }
672 
673  assert(sgprIdx > -1);
674 
675  return sgprIdx;
676  }
677 
686  std::array<ScalarRegU32, NumDwords> srfData;
687  };
688 
689  // typedefs for the various sizes/types of scalar operands
703  // non-writeable versions of scalar operands
717  // typedefs for the various sizes/types of vector operands
732  // non-writeable versions of vector operands
747 }
748 
749 } // namespace gem5
750 
751 #endif // __ARCH_GCN3_OPERAND_HH__
gem5::Gcn3ISA::Operand::Operand
Operand()=delete
gem5::Gcn3ISA::REG_SRC_SWDA
@ REG_SRC_SWDA
Definition: gpu_registers.hh:126
gem5::Gcn3ISA::VecOperand::scalar
bool scalar
whether this operand a scalar or not.
Definition: operand.hh:338
gem5::Gcn3ISA::Operand::Operand
Operand(GPUDynInstPtr gpuDynInst, int opIdx)
Definition: operand.hh:70
gem5::Gcn3ISA::ScalarOperand::rawDataPtr
void * rawDataPtr()
Definition: operand.hh:404
gem5::Gcn3ISA::isScalarReg
bool isScalarReg(int opIdx)
Definition: registers.cc:218
gem5::Gcn3ISA::VecOperand::negMod
bool negMod
Definition: operand.hh:346
gem5::Gcn3ISA::Operand::write
virtual void write()=0
gem5::Gcn3ISA::ScalarRegF32
float ScalarRegF32
Definition: gpu_registers.hh:157
gem5::Gcn3ISA::OpTraits::FloatT
float FloatT
Definition: operand.hh:61
gem5::Gcn3ISA::REG_EXEC_LO
@ REG_EXEC_LO
Definition: gpu_registers.hh:78
gem5::ComputeUnit::srf
std::vector< ScalarRegisterFile * > srf
Definition: compute_unit.hh:299
gem5::Gcn3ISA::VecOperand::readScalar
void readScalar()
if we determine that this operand is a scalar (reg or constant) then we read the scalar data into the...
Definition: operand.hh:326
gem5::Gcn3ISA::VecOperand::~VecOperand
~VecOperand()
Definition: operand.hh:119
gem5::Gcn3ISA::VecElemU32
uint32_t VecElemU32
Definition: gpu_registers.hh:167
gem5::Gcn3ISA::ScalarOperand::read
void read() override
Definition: operand.hh:410
gem5::Gcn3ISA::ScalarOperand::ScalarOperand
ScalarOperand(GPUDynInstPtr gpuDynInst, int opIdx)
Definition: operand.hh:374
gem5::Wavefront
Definition: wavefront.hh:62
gem5::Gcn3ISA::REG_NEG_FOUR
@ REG_NEG_FOUR
Definition: gpu_registers.hh:123
gpu_registers.hh
gem5::replaceBits
constexpr void replaceBits(T &val, unsigned first, unsigned last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
Definition: bitfield.hh:197
gem5::Gcn3ISA::REG_EXEC_HI
@ REG_EXEC_HI
Definition: gpu_registers.hh:79
gem5::VectorMask
std::bitset< std::numeric_limits< unsigned long long >::digits > VectorMask
Definition: misc.hh:47
gem5::Gcn3ISA::ScalarOperand::~ScalarOperand
~ScalarOperand()
Definition: operand.hh:380
gem5::Gcn3ISA::Operand::_opIdx
int _opIdx
op selector value for this operand.
Definition: operand.hh:95
gem5::Gcn3ISA::VecOperand::operator[]
std::enable_if_t< Condition, DataType & > operator[](size_t idx)
setter [] operator.
Definition: operand.hh:312
gem5::Gcn3ISA::OpTraits< ScalarRegU64 >::FloatT
double FloatT
Definition: operand.hh:63
gem5::Gcn3ISA::VecOperand
Definition: operand.hh:103
gem5::Gcn3ISA::REG_POS_ONE
@ REG_POS_ONE
Definition: gpu_registers.hh:118
gem5::Gcn3ISA::VecOperand::VecRegCont
VecRegContainer< sizeof(DataType) *NumVecElemPerVecReg > VecRegCont
Definition: operand.hh:333
gem5::Gcn3ISA::Operand
Definition: operand.hh:65
gem5::Gcn3ISA::VecOperand::absMod
bool absMod
absolute value and negative modifiers.
Definition: operand.hh:345
gem5::Gcn3ISA::ScalarOperand::regIdx
int regIdx(int dword) const
for scalars we need to do some extra work to figure out how to map the op selector to the sgpr idx be...
Definition: operand.hh:653
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::Gcn3ISA::REG_POS_HALF
@ REG_POS_HALF
Definition: gpu_registers.hh:116
gem5::Gcn3ISA::VecOperand::write
void write() override
write to the vrf.
Definition: operand.hh:200
gem5::Gcn3ISA::VecOperand::readSrc
void readSrc()
certain vector operands can read from the vrf/srf or constants.
Definition: operand.hh:132
gem5::Gcn3ISA::REG_POS_FOUR
@ REG_POS_FOUR
Definition: gpu_registers.hh:122
gem5::ComputeUnit::vrf
std::vector< VectorRegisterFile * > vrf
Definition: compute_unit.hh:297
wavefront.hh
gem5::Gcn3ISA::REG_FLAT_SCRATCH_LO
@ REG_FLAT_SCRATCH_LO
Definition: gpu_registers.hh:54
gem5::RegisterManager::mapSgpr
int mapSgpr(Wavefront *w, int sgprIndex)
Definition: register_manager.cc:104
gem5::ComputeUnit
Definition: compute_unit.hh:203
gem5::Gcn3ISA::VecOperand::negModifier
void negModifier()
Definition: operand.hh:251
gem5::Gcn3ISA::Operand::read
virtual void read()=0
read from and write to the underlying register(s) that this operand is referring to.
vector_register_file.hh
gem5::VecRegContainer
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
Definition: vec_reg.hh:121
gem5::Gcn3ISA::REG_POS_TWO
@ REG_POS_TWO
Definition: gpu_registers.hh:120
gem5::Wavefront::reservedScalarRegs
int reservedScalarRegs
Definition: wavefront.hh:198
gem5::Gcn3ISA::isVectorReg
bool isVectorReg(int opIdx)
Definition: registers.cc:231
gem5::Gcn3ISA::OpTraits< ScalarRegF64 >::FloatT
double FloatT
Definition: operand.hh:62
gem5::Gcn3ISA::ScalarOperand::operator=
std::enable_if_t< Condition, ScalarOperand & > operator=(DataType rhs)
Definition: operand.hh:500
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Gcn3ISA::opSelectorToRegIdx
int opSelectorToRegIdx(int opIdx, int numScalarRegs)
Definition: registers.cc:124
gem5::Gcn3ISA::ScalarOperand::write
void write() override
Definition: operand.hh:428
gem5::Gcn3ISA::NumVecElemPerVecReg
const int NumVecElemPerVecReg(64)
gem5::Gcn3ISA::ScalarOperand
Definition: operand.hh:99
gem5::Gcn3ISA::REG_NEG_ONE
@ REG_NEG_ONE
Definition: gpu_registers.hh:119
gem5::Gcn3ISA::ScalarOperand::ScalarOperand
ScalarOperand()=delete
gem5::Gcn3ISA::VecOperand::vrfData
std::array< VecRegContainerU32 *, NumDwords > vrfData
pointers to the underlyding registers (i.e., the actual registers in the register file).
Definition: operand.hh:362
gem5::Gcn3ISA::VecOperand::scRegData
ScalarOperand< DataType, Const, NumDwords > scRegData
for src operands that read scalars (i.e., scalar regs or a scalar constant).
Definition: operand.hh:357
gem5::ComputeUnit::registerManager
RegisterManager * registerManager
Definition: compute_unit.hh:280
scalar_register_file.hh
gem5::Gcn3ISA::VecOperand::absModifier
void absModifier()
Definition: operand.hh:257
gem5::Gcn3ISA::VecOperand::operator[]
std::enable_if_t< Condition, const DataType > operator[](size_t idx) const
getter [] operator.
Definition: operand.hh:269
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::Wavefront::execMask
VectorMask & execMask()
Definition: wavefront.cc:1377
gem5::Gcn3ISA::REG_NEG_TWO
@ REG_NEG_TWO
Definition: gpu_registers.hh:121
gem5::Gcn3ISA::ScalarRegU64
uint64_t ScalarRegU64
Definition: gpu_registers.hh:158
gem5::Gcn3ISA::VecOperand::read
void read() override
read from the vrf.
Definition: operand.hh:148
gem5::Gcn3ISA::VecOperand::VecOperand
VecOperand()=delete
gem5::RegisterManager::mapVgpr
int mapVgpr(Wavefront *w, int vgprIndex)
Definition: register_manager.cc:97
gem5::GPUDynInstPtr
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition: misc.hh:51
gem5::Gcn3ISA::REG_VCC_LO
@ REG_VCC_LO
Definition: gpu_registers.hh:58
gem5::Gcn3ISA::REG_FLAT_SCRATCH_HI
@ REG_FLAT_SCRATCH_HI
Definition: gpu_registers.hh:55
vec_reg.hh
gem5::Gcn3ISA::Operand::_gpuDynInst
GPUDynInstPtr _gpuDynInst
instruction object that owns this operand
Definition: operand.hh:88
gem5::Gcn3ISA::REG_NEG_HALF
@ REG_NEG_HALF
Definition: gpu_registers.hh:117
gem5::Gcn3ISA::ScalarOperand::srfData
std::array< ScalarRegU32, NumDwords > srfData
in GCN3 each register is represented as a 32b unsigned value, however operands may require up to 16 r...
Definition: operand.hh:686
gem5::Gcn3ISA::MaxOperandDwords
constexpr size_t MaxOperandDwords(16)
gem5::Gcn3ISA::ScalarRegF64
double ScalarRegF64
Definition: gpu_registers.hh:160
gem5::Gcn3ISA::REG_SRC_DPP
@ REG_SRC_DPP
Definition: gpu_registers.hh:127
gem5::Gcn3ISA::VecOperand::vecReg
VecRegCont vecReg
this holds all the operand data in a single vector register object (i.e., if an operand is 64b,...
Definition: operand.hh:352
gem5::Gcn3ISA::ScalarOperand::setBit
std::enable_if_t< Condition, void > setBit(int bit, int bit_val)
bit access to scalar data.
Definition: operand.hh:492
gem5::VecRegContainer::zero
void zero()
Zero the container.
Definition: vec_reg.hh:140
gem5::Gcn3ISA::REG_SRC_LITERAL
@ REG_SRC_LITERAL
Definition: gpu_registers.hh:132
gem5::Gcn3ISA::REG_PI
@ REG_PI
Definition: gpu_registers.hh:124
gem5::Gcn3ISA::OpTraits
convenience traits so we can automatically infer the correct FP type without looking at the number of...
Definition: operand.hh:61
gem5::Gcn3ISA::VecOperand::VecOperand
VecOperand(GPUDynInstPtr gpuDynInst, int opIdx)
Definition: operand.hh:111
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::Gcn3ISA::isConstVal
bool isConstVal(int opIdx)
Definition: registers.cc:187
gem5::Gcn3ISA::ScalarOperand::readSpecialVal
void readSpecialVal()
we have determined that we are not reading our scalar operand data from the register file,...
Definition: operand.hh:514
gem5::Gcn3ISA::ScalarRegU32
uint32_t ScalarRegU32
Definition: gpu_registers.hh:155
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::Gcn3ISA::ScalarOperand::rawData
std::enable_if_t< Condition, DataType > rawData() const
we store scalar data in a std::array, however if we need the full operand data we use this method to ...
Definition: operand.hh:393
gem5::Gcn3ISA::VecElemU64
uint64_t VecElemU64
Definition: gpu_registers.hh:170
gem5::Wavefront::simdId
const int simdId
Definition: wavefront.hh:101

Generated on Tue Sep 21 2021 12:24:21 for gem5 by doxygen 1.8.17