hdlcd.hh

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#ifndef __DEV_ARM_HDLCD_HH__
#define __DEV_ARM_HDLCD_HH__
 
#include <fstream>
#include <memory>
#include <vector>
 
#include "base/framebuffer.hh"
#include "base/imgwriter.hh"
#include "base/output.hh"
#include "dev/arm/amba_device.hh"
#include "dev/pixelpump.hh"
#include "sim/serialize.hh"
 
namespace gem5
{
 
class VncInput;
struct HDLcdParams;
class HDLcdPixelPump;
 
class HDLcd: public AmbaDmaDevice
{
  public:
    HDLcd(const HDLcdParams &p);
 
    void serialize(CheckpointOut &cp) const override;
    void unserialize(CheckpointIn &cp) override;
 
    void drainResume() override;
 
  public: // IO device interface
    Tick read(PacketPtr pkt) override;
    Tick write(PacketPtr pkt) override;
 
    AddrRangeList getAddrRanges() const override { return addrRanges; }
 
  protected: // Parameters
    VncInput *vnc;
    const bool workaroundSwapRB;
    const bool workaroundDmaLineCount;
    const AddrRangeList addrRanges;
    const bool enableCapture;
    const Addr pixelBufferSize;
    const Tick virtRefreshRate;
 
  protected: // Register handling
    enum RegisterOffset
    {
        Version          = 0x0000,
        Int_RawStat      = 0x0010,
        Int_Clear        = 0x0014,
        Int_Mask         = 0x0018,
        Int_Status       = 0x001C,
        Fb_Base          = 0x0100,
        Fb_Line_Length   = 0x0104,
        Fb_Line_Count    = 0x0108,
        Fb_Line_Pitch    = 0x010C,
        Bus_Options      = 0x0110,
        V_Sync           = 0x0200,
        V_Back_Porch     = 0x0204,
        V_Data           = 0x0208,
        V_Front_Porch    = 0x020C,
        H_Sync           = 0x0210,
        H_Back_Porch     = 0x0214,
        H_Data           = 0x0218,
        H_Front_Porch    = 0x021C,
        Polarities       = 0x0220,
        Command          = 0x0230,
        Pixel_Format     = 0x0240,
        Red_Select       = 0x0244,
        Green_Select     = 0x0248,
        Blue_Select      = 0x024C,
    };
 
    static constexpr size_t BUS_OPTIONS_RESETV = 0x408;
 
    static constexpr size_t VERSION_RESETV = 0x1CDC0000;
 
    static constexpr size_t AXI_PORT_WIDTH = 8;
 
    static constexpr size_t MAX_BURST_LEN = 16;
 
    static constexpr size_t MAX_PIXEL_SIZE = 4;
 
    BitUnion32(VersionReg)
        Bitfield<7,0>   version_minor;
        Bitfield<15,8>  version_major;
        Bitfield<31,16> product_id;
    EndBitUnion(VersionReg)
 
    static constexpr uint32_t INT_DMA_END = (1UL << 0);
    static constexpr uint32_t INT_BUS_ERROR = (1UL << 1);
    static constexpr uint32_t INT_VSYNC = (1UL << 2);
    static constexpr uint32_t INT_UNDERRUN = (1UL << 3);
 
    BitUnion32(FbLineCountReg)
        Bitfield<11,0>  fb_line_count;
        Bitfield<31,12> reserved_31_12;
    EndBitUnion(FbLineCountReg)
 
    BitUnion32(BusOptsReg)
        Bitfield<4,0>   burst_len;
        Bitfield<7,5>   reserved_7_5;
        Bitfield<11,8>  max_outstanding;
        Bitfield<31,12> reserved_31_12;
    EndBitUnion(BusOptsReg)
 
    BitUnion32(TimingReg)
        Bitfield<11,0>  val;
        Bitfield<31,12> reserved_31_12;
    EndBitUnion(TimingReg)
 
    BitUnion32(PolaritiesReg)
        Bitfield<0>    vsync_polarity;
        Bitfield<1>    hsync_polarity;
        Bitfield<2>    dataen_polarity;
        Bitfield<3>    data_polarity;
        Bitfield<4>    pxlclk_polarity;
        Bitfield<31,5> reserved_31_5;
    EndBitUnion(PolaritiesReg)
 
    BitUnion32(CommandReg)
        Bitfield<0>    enable;
        Bitfield<31,1> reserved_31_1;
    EndBitUnion(CommandReg)
 
    BitUnion32(PixelFormatReg)
        Bitfield<2,0>  reserved_2_0;
        Bitfield<4,3>  bytes_per_pixel;
        Bitfield<30,5> reserved_30_5;
        Bitfield<31>   big_endian;
    EndBitUnion(PixelFormatReg)
 
    BitUnion32(ColorSelectReg)
        Bitfield<4,0>   offset;
        Bitfield<7,5>   reserved_7_5;
        Bitfield<11,8>  size;
        Bitfield<15,12> reserved_15_12;
        Bitfield<23,16> default_color;
        Bitfield<31,24> reserved_31_24;
    EndBitUnion(ColorSelectReg)
    const VersionReg version = VERSION_RESETV;
    uint32_t int_rawstat = 0;       
    uint32_t int_mask = 0;          
    uint32_t fb_base = 0;           
    uint32_t fb_line_length = 0;    
    FbLineCountReg fb_line_count = 0;
    int32_t fb_line_pitch = 0;      
    BusOptsReg bus_options = BUS_OPTIONS_RESETV;
    TimingReg v_sync = 0;           
    TimingReg v_back_porch = 0;     
    TimingReg v_data = 0;           
    TimingReg v_front_porch = 0;    
    TimingReg h_sync = 0;           
    TimingReg h_back_porch = 0;     
    TimingReg h_data = 0;           
    TimingReg h_front_porch = 0;    
    PolaritiesReg polarities = 0;   
    CommandReg command = 0;         
    PixelFormatReg pixel_format = 0;
    ColorSelectReg red_select = 0;  
    ColorSelectReg green_select = 0;
    ColorSelectReg blue_select = 0; 
    std::vector<uint8_t> lineBuffer;
 
    uint32_t readReg(Addr offset);
    void writeReg(Addr offset, uint32_t value);
 
    PixelConverter pixelConverter() const;
    DisplayTimings displayTimings() const;
 
    void createDmaEngine();
 
    void cmdEnable();
    void cmdDisable();
 
    bool enabled() const { return command.enable; }
 
  public: // Pixel pump callbacks
    bool pxlNext(Pixel &p);
    size_t lineNext(std::vector<Pixel>::iterator pixel_it, size_t line_length);
    void pxlVSyncBegin();
    void pxlVSyncEnd();
    void pxlUnderrun();
    void pxlFrameDone();
 
  protected: // Interrupt handling
    void setInterrupts(uint32_t ints, uint32_t mask);
 
    void intMask(uint32_t mask) { setInterrupts(int_rawstat, mask); }
 
    void
    intRaise(uint32_t ints)
    {
        setInterrupts(int_rawstat | ints, int_mask);
    }
 
    void
    intClear(uint32_t ints)
    {
        setInterrupts(int_rawstat & ~ints, int_mask);
    }
 
    uint32_t intStatus() const { return int_rawstat & int_mask; }
 
  protected: // Pixel output
    class PixelPump : public BasePixelPump
    {
      public:
        PixelPump(HDLcd &p, ClockDomain &pxl_clk, unsigned pixel_chunk)
            : BasePixelPump(p, pxl_clk, pixel_chunk), parent(p)
        {}
 
        void dumpSettings();
 
      protected:
        bool nextPixel(Pixel &p) override { return parent.pxlNext(p); }
        size_t
        nextLine(std::vector<Pixel>::iterator pixel_it,
                 size_t line_length) override
        {
            return parent.lineNext(pixel_it, line_length);
        }
 
        void onVSyncBegin() override { return parent.pxlVSyncBegin(); }
        void onVSyncEnd() override { return parent.pxlVSyncEnd(); }
 
        void
        onUnderrun(unsigned x, unsigned y) override
        {
            parent.pxlUnderrun();
        }
 
        void onFrameDone() override { parent.pxlFrameDone(); }
 
      protected:
        HDLcd &parent;
    };
 
    Addr bypassLineAddress = 0;
 
    void virtRefresh();
    EventFunctionWrapper virtRefreshEvent;
 
    std::unique_ptr<ImgWriter> imgWriter;
 
    enums::ImageFormat imgFormat;
 
    OutputStream *pic = nullptr;
 
    PixelConverter conv = PixelConverter::rgba8888_le;
 
    PixelPump pixelPump;
 
  protected: // DMA handling
    class DmaEngine : public DmaReadFifo
    {
      public:
        DmaEngine(HDLcd &_parent, size_t size,
                  unsigned request_size, unsigned max_pending,
                  size_t line_size, ssize_t line_pitch, unsigned num_lines);
 
        void startFrame(Addr fb_base);
        void abortFrame();
        void dumpSettings();
 
        void serialize(CheckpointOut &cp) const override;
        void unserialize(CheckpointIn &cp) override;
 
      protected:
        void onEndOfBlock() override;
        void onIdle() override;
 
        HDLcd &parent;
        const size_t lineSize;
        const ssize_t linePitch;
        const unsigned numLines;
 
        Addr nextLineAddr;
        Addr frameEnd;
    };
 
    std::unique_ptr<DmaEngine> dmaEngine;
 
  protected: // Statistics
    struct HDLcdStats: public statistics::Group
    {
        HDLcdStats(statistics::Group *parent);
        statistics::Scalar underruns;
    } stats;
};
 
} // namespace gem5
 
#endif