gem5  v21.1.0.2
hdlcd.hh
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37 
38 
73 #ifndef __DEV_ARM_HDLCD_HH__
74 #define __DEV_ARM_HDLCD_HH__
75 
76 #include <fstream>
77 #include <memory>
78 #include <vector>
79 
80 #include "base/framebuffer.hh"
81 #include "base/imgwriter.hh"
82 #include "base/output.hh"
83 #include "dev/arm/amba_device.hh"
84 #include "dev/pixelpump.hh"
85 #include "sim/serialize.hh"
86 
87 namespace gem5
88 {
89 
90 class VncInput;
91 struct HDLcdParams;
92 class HDLcdPixelPump;
93 
94 class HDLcd: public AmbaDmaDevice
95 {
96  public:
97  HDLcd(const HDLcdParams &p);
98 
99  void serialize(CheckpointOut &cp) const override;
100  void unserialize(CheckpointIn &cp) override;
101 
102  void drainResume() override;
103 
104  public: // IO device interface
105  Tick read(PacketPtr pkt) override;
106  Tick write(PacketPtr pkt) override;
107 
108  AddrRangeList getAddrRanges() const override { return addrRanges; }
109 
110  protected: // Parameters
112  const bool workaroundSwapRB;
115  const bool enableCapture;
118 
119  protected: // Register handling
122  {
123  Version = 0x0000,
124  Int_RawStat = 0x0010,
125  Int_Clear = 0x0014,
126  Int_Mask = 0x0018,
127  Int_Status = 0x001C,
128  Fb_Base = 0x0100,
129  Fb_Line_Length = 0x0104,
130  Fb_Line_Count = 0x0108,
131  Fb_Line_Pitch = 0x010C,
132  Bus_Options = 0x0110,
133  V_Sync = 0x0200,
134  V_Back_Porch = 0x0204,
135  V_Data = 0x0208,
136  V_Front_Porch = 0x020C,
137  H_Sync = 0x0210,
138  H_Back_Porch = 0x0214,
139  H_Data = 0x0218,
140  H_Front_Porch = 0x021C,
141  Polarities = 0x0220,
142  Command = 0x0230,
143  Pixel_Format = 0x0240,
144  Red_Select = 0x0244,
145  Green_Select = 0x0248,
146  Blue_Select = 0x024C,
147  };
148 
150  static constexpr size_t BUS_OPTIONS_RESETV = 0x408;
151 
153  static constexpr size_t VERSION_RESETV = 0x1CDC0000;
154 
156  static constexpr size_t AXI_PORT_WIDTH = 8;
157 
159  static constexpr size_t MAX_BURST_LEN = 16;
160 
162  static constexpr size_t MAX_PIXEL_SIZE = 4;
163 
169  BitUnion32(VersionReg)
170  Bitfield<7,0> version_minor;
171  Bitfield<15,8> version_major;
172  Bitfield<31,16> product_id;
173  EndBitUnion(VersionReg)
174 
175  static constexpr uint32_t INT_DMA_END = (1UL << 0);
176  static constexpr uint32_t INT_BUS_ERROR = (1UL << 1);
177  static constexpr uint32_t INT_VSYNC = (1UL << 2);
178  static constexpr uint32_t INT_UNDERRUN = (1UL << 3);
179 
180  BitUnion32(FbLineCountReg)
181  Bitfield<11,0> fb_line_count;
182  Bitfield<31,12> reserved_31_12;
183  EndBitUnion(FbLineCountReg)
184 
185  BitUnion32(BusOptsReg)
186  Bitfield<4,0> burst_len;
187  Bitfield<7,5> reserved_7_5;
188  Bitfield<11,8> max_outstanding;
189  Bitfield<31,12> reserved_31_12;
190  EndBitUnion(BusOptsReg)
191 
192  BitUnion32(TimingReg)
193  Bitfield<11,0> val;
194  Bitfield<31,12> reserved_31_12;
195  EndBitUnion(TimingReg)
196 
197  BitUnion32(PolaritiesReg)
198  Bitfield<0> vsync_polarity;
199  Bitfield<1> hsync_polarity;
200  Bitfield<2> dataen_polarity;
201  Bitfield<3> data_polarity;
202  Bitfield<4> pxlclk_polarity;
203  Bitfield<31,5> reserved_31_5;
204  EndBitUnion(PolaritiesReg)
205 
206  BitUnion32(CommandReg)
207  Bitfield<0> enable;
208  Bitfield<31,1> reserved_31_1;
209  EndBitUnion(CommandReg)
210 
211  BitUnion32(PixelFormatReg)
212  Bitfield<2,0> reserved_2_0;
213  Bitfield<4,3> bytes_per_pixel;
214  Bitfield<30,5> reserved_30_5;
215  Bitfield<31> big_endian;
216  EndBitUnion(PixelFormatReg)
217 
218  BitUnion32(ColorSelectReg)
219  Bitfield<4,0> offset;
220  Bitfield<7,5> reserved_7_5;
221  Bitfield<11,8> size;
222  Bitfield<15,12> reserved_15_12;
223  Bitfield<23,16> default_color;
224  Bitfield<31,24> reserved_31_24;
225  EndBitUnion(ColorSelectReg)
233  const VersionReg version = VERSION_RESETV;
235  uint32_t int_rawstat = 0;
236  uint32_t int_mask = 0;
237  uint32_t fb_base = 0;
238  uint32_t fb_line_length = 0;
240  FbLineCountReg fb_line_count = 0;
241  int32_t fb_line_pitch = 0;
244  TimingReg v_sync = 0;
245  TimingReg v_back_porch = 0;
246  TimingReg v_data = 0;
247  TimingReg v_front_porch = 0;
248  TimingReg h_sync = 0;
249  TimingReg h_back_porch = 0;
250  TimingReg h_data = 0;
251  TimingReg h_front_porch = 0;
252  PolaritiesReg polarities = 0;
253  CommandReg command = 0;
254  PixelFormatReg pixel_format = 0;
255  ColorSelectReg red_select = 0;
256  ColorSelectReg green_select = 0;
257  ColorSelectReg blue_select = 0;
260  std::vector<uint8_t> lineBuffer;
261 
262  uint32_t readReg(Addr offset);
263  void writeReg(Addr offset, uint32_t value);
264 
267 
268  void createDmaEngine();
269 
270  void cmdEnable();
271  void cmdDisable();
272 
273  bool enabled() const { return command.enable; }
274 
275  public: // Pixel pump callbacks
276  bool pxlNext(Pixel &p);
277  size_t lineNext(std::vector<Pixel>::iterator pixel_it, size_t line_length);
278  void pxlVSyncBegin();
279  void pxlVSyncEnd();
280  void pxlUnderrun();
281  void pxlFrameDone();
282 
283  protected: // Interrupt handling
295  void setInterrupts(uint32_t ints, uint32_t mask);
296 
303  void intMask(uint32_t mask) { setInterrupts(int_rawstat, mask); }
304 
311  void
312  intRaise(uint32_t ints)
313  {
315  }
316 
323  void
324  intClear(uint32_t ints)
325  {
327  }
328 
330  uint32_t intStatus() const { return int_rawstat & int_mask; }
331 
332  protected: // Pixel output
333  class PixelPump : public BasePixelPump
334  {
335  public:
336  PixelPump(HDLcd &p, ClockDomain &pxl_clk, unsigned pixel_chunk)
337  : BasePixelPump(p, pxl_clk, pixel_chunk), parent(p)
338  {}
339 
340  void dumpSettings();
341 
342  protected:
343  bool nextPixel(Pixel &p) override { return parent.pxlNext(p); }
344  size_t
346  size_t line_length) override
347  {
348  return parent.lineNext(pixel_it, line_length);
349  }
350 
351  void onVSyncBegin() override { return parent.pxlVSyncBegin(); }
352  void onVSyncEnd() override { return parent.pxlVSyncEnd(); }
353 
354  void
355  onUnderrun(unsigned x, unsigned y) override
356  {
358  }
359 
360  void onFrameDone() override { parent.pxlFrameDone(); }
361 
362  protected:
364  };
365 
367 
369  void virtRefresh();
371 
373  std::unique_ptr<ImgWriter> imgWriter;
374 
376  enums::ImageFormat imgFormat;
377 
379  OutputStream *pic = nullptr;
380 
383 
385 
386  protected: // DMA handling
387  class DmaEngine : public DmaReadFifo
388  {
389  public:
390  DmaEngine(HDLcd &_parent, size_t size,
391  unsigned request_size, unsigned max_pending,
392  size_t line_size, ssize_t line_pitch, unsigned num_lines);
393 
394  void startFrame(Addr fb_base);
395  void abortFrame();
396  void dumpSettings();
397 
398  void serialize(CheckpointOut &cp) const override;
399  void unserialize(CheckpointIn &cp) override;
400 
401  protected:
402  void onEndOfBlock() override;
403  void onIdle() override;
404 
406  const size_t lineSize;
407  const ssize_t linePitch;
408  const unsigned numLines;
409 
412  };
413 
414  std::unique_ptr<DmaEngine> dmaEngine;
415 
416  protected: // Statistics
418  {
419  HDLcdStats(statistics::Group *parent);
421  } stats;
422 };
423 
424 } // namespace gem5
425 
426 #endif
gem5::HDLcd::PixelPump::nextLine
size_t nextLine(std::vector< Pixel >::iterator pixel_it, size_t line_length) override
Get the next line of pixels directly from memory.
Definition: hdlcd.hh:345
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1927
gem5::HDLcd::addrRanges
const AddrRangeList addrRanges
Definition: hdlcd.hh:114
gem5::HDLcd::DmaEngine::abortFrame
void abortFrame()
Definition: hdlcd.cc:642
gem5::HDLcd::reserved_31_5
Bitfield< 31, 5 > reserved_31_5
Definition: hdlcd.hh:203
gem5::HDLcd::Fb_Base
@ Fb_Base
Definition: hdlcd.hh:128
gem5::HDLcd::HDLcdStats::HDLcdStats
HDLcdStats(statistics::Group *parent)
Definition: hdlcd.cc:83
gem5::HDLcd::data_polarity
Bitfield< 3 > data_polarity
Definition: hdlcd.hh:201
gem5::HDLcd::imgWriter
std::unique_ptr< ImgWriter > imgWriter
Helper to write out bitmaps.
Definition: hdlcd.hh:373
gem5::HDLcd::AXI_PORT_WIDTH
static constexpr size_t AXI_PORT_WIDTH
AXI port width in bytes.
Definition: hdlcd.hh:156
gem5::HDLcd::lineNext
size_t lineNext(std::vector< Pixel >::iterator pixel_it, size_t line_length)
Definition: hdlcd.cc:512
gem5::HDLcd::cmdDisable
void cmdDisable()
Definition: hdlcd.cc:487
gem5::HDLcd::v_data
TimingReg v_data
Vertical data width register.
Definition: hdlcd.hh:246
gem5::HDLcd::Fb_Line_Length
@ Fb_Line_Length
Definition: hdlcd.hh:129
gem5::HDLcd::stats
gem5::HDLcd::HDLcdStats stats
gem5::HDLcd::virtRefresh
void virtRefresh()
Handler for fast frame refresh in KVM-mode.
Definition: hdlcd.cc:207
serialize.hh
gem5::HDLcd::MAX_BURST_LEN
static constexpr size_t MAX_BURST_LEN
max number of beats delivered in one dma burst
Definition: hdlcd.hh:159
gem5::X86ISA::vector
Bitfield< 15, 8 > vector
Definition: intmessage.hh:48
gem5::HDLcd::PixelPump::nextPixel
bool nextPixel(Pixel &p) override
Get the next pixel from the scan line buffer.
Definition: hdlcd.hh:343
gem5::HDLcd::product_id
Bitfield< 31, 16 > product_id
Definition: hdlcd.hh:172
gem5::HDLcd::red_select
ColorSelectReg red_select
Red color select register.
Definition: hdlcd.hh:255
gem5::DmaReadFifo
Buffered DMA engine helper class.
Definition: dma_device.hh:364
gem5::HDLcd::bypassLineAddress
Addr bypassLineAddress
Definition: hdlcd.hh:366
gem5::HDLcd::h_sync
TimingReg h_sync
Horizontal sync width register.
Definition: hdlcd.hh:248
amba_device.hh
gem5::HDLcd::PixelPump::PixelPump
PixelPump(HDLcd &p, ClockDomain &pxl_clk, unsigned pixel_chunk)
Definition: hdlcd.hh:336
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::HDLcd::H_Data
@ H_Data
Definition: hdlcd.hh:139
gem5::HDLcd::int_mask
uint32_t int_mask
Interrupt mask register.
Definition: hdlcd.hh:236
gem5::HDLcd::pxlVSyncBegin
void pxlVSyncBegin()
Definition: hdlcd.cc:531
gem5::HDLcd::v_front_porch
TimingReg v_front_porch
Vertical front porch width register.
Definition: hdlcd.hh:247
gem5::HDLcd::reserved_31_12
Bitfield< 31, 12 > reserved_31_12
Definition: hdlcd.hh:182
gem5::HDLcd::polarities
PolaritiesReg polarities
Polarities register.
Definition: hdlcd.hh:252
gem5::HDLcd::Int_Clear
@ Int_Clear
Definition: hdlcd.hh:125
gem5::HDLcd::displayTimings
DisplayTimings displayTimings() const
Definition: hdlcd.cc:437
gem5::HDLcd::RegisterOffset
RegisterOffset
ARM HDLcd register offsets.
Definition: hdlcd.hh:121
gem5::HDLcd::V_Back_Porch
@ V_Back_Porch
Definition: hdlcd.hh:134
gem5::HDLcd::conv
PixelConverter conv
Cached pixel converter, set when the converter is enabled.
Definition: hdlcd.hh:382
gem5::HDLcd::max_outstanding
Bitfield< 11, 8 > max_outstanding
Definition: hdlcd.hh:188
gem5::HDLcd::readReg
uint32_t readReg(Addr offset)
Definition: hdlcd.cc:254
pixelpump.hh
std::vector
STL vector class.
Definition: stl.hh:37
gem5::HDLcd::fb_line_length
uint32_t fb_line_length
Frame buffer Line length register.
Definition: hdlcd.hh:238
gem5::HDLcd::DmaEngine::lineSize
const size_t lineSize
Definition: hdlcd.hh:406
gem5::HDLcd::intStatus
uint32_t intStatus() const
Masked interrupt status register.
Definition: hdlcd.hh:330
gem5::HDLcd::PixelPump::dumpSettings
void dumpSettings()
Definition: hdlcd.cc:678
gem5::HDLcd::DmaEngine::dumpSettings
void dumpSettings()
Definition: hdlcd.cc:651
imgwriter.hh
gem5::HDLcd::createDmaEngine
void createDmaEngine()
Definition: hdlcd.cc:446
gem5::HDLcd::vnc
VncInput * vnc
Definition: hdlcd.hh:111
gem5::HDLcd::bytes_per_pixel
Bitfield< 4, 3 > bytes_per_pixel
Definition: hdlcd.hh:213
gem5::HDLcd::Pixel_Format
@ Pixel_Format
Definition: hdlcd.hh:143
output.hh
gem5::DisplayTimings
Definition: pixelpump.hh:51
gem5::HDLcd::lineBuffer
std::vector< uint8_t > lineBuffer
Definition: hdlcd.hh:260
gem5::HDLcd::version_major
Bitfield< 15, 8 > version_major
Definition: hdlcd.hh:171
gem5::mask
constexpr uint64_t mask(unsigned nbits)
Generate a 64-bit mask of 'nbits' 1s, right justified.
Definition: bitfield.hh:63
gem5::HDLcd::DmaEngine::startFrame
void startFrame(Addr fb_base)
Definition: hdlcd.cc:633
gem5::HDLcd::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: hdlcd.cc:235
gem5::HDLcd::reserved_7_5
Bitfield< 7, 5 > reserved_7_5
Definition: hdlcd.hh:187
gem5::HDLcd::V_Front_Porch
@ V_Front_Porch
Definition: hdlcd.hh:136
gem5::HDLcd::pixel_format
PixelFormatReg pixel_format
Pixel format register.
Definition: hdlcd.hh:254
gem5::DmaReadFifo::size
size_t size() const
Get the amount of data stored in the FIFO.
Definition: dma_device.hh:427
gem5::HDLcd::command
CommandReg command
Command register.
Definition: hdlcd.hh:253
gem5::HDLcd::HDLcdStats::underruns
statistics::Scalar underruns
Definition: hdlcd.hh:420
gem5::HDLcd::Fb_Line_Pitch
@ Fb_Line_Pitch
Definition: hdlcd.hh:131
gem5::HDLcd::bus_options
BusOptsReg bus_options
Bus options register.
Definition: hdlcd.hh:242
gem5::HDLcd::Version
@ Version
Definition: hdlcd.hh:123
gem5::HDLcd::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: hdlcd.cc:215
gem5::HDLcd::Red_Select
@ Red_Select
Definition: hdlcd.hh:144
gem5::HDLcd::INT_BUS_ERROR
static constexpr uint32_t INT_BUS_ERROR
Definition: hdlcd.hh:176
gem5::HDLcd::PixelPump::onVSyncEnd
void onVSyncEnd() override
Callback on the first pixel of the line after the end VSync region (typically the first pixel of the ...
Definition: hdlcd.hh:352
gem5::HDLcd::PixelPump
Definition: hdlcd.hh:333
gem5::HDLcd::DmaEngine::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: hdlcd.cc:615
gem5::HDLcd::DmaEngine::onEndOfBlock
void onEndOfBlock() override
End of block callback.
Definition: hdlcd.cc:659
gem5::HDLcd::dmaEngine
std::unique_ptr< DmaEngine > dmaEngine
Definition: hdlcd.hh:414
gem5::HDLcd::h_data
TimingReg h_data
Horizontal data width register.
Definition: hdlcd.hh:250
gem5::HDLcd::PixelPump::onFrameDone
void onFrameDone() override
Finished displaying the visible region of a frame.
Definition: hdlcd.hh:360
gem5::X86ISA::enable
Bitfield< 11 > enable
Definition: misc.hh:1057
gem5::HDLcd::fb_line_count
fb_line_count
Definition: hdlcd.hh:181
gem5::ClockDomain
The ClockDomain provides clock to group of clocked objects bundled under the same clock domain.
Definition: clock_domain.hh:71
gem5::HDLcd::Polarities
@ Polarities
Definition: hdlcd.hh:141
gem5::HDLcd::Fb_Line_Count
@ Fb_Line_Count
Definition: hdlcd.hh:130
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::HDLcd::EndBitUnion
EndBitUnion(VersionReg) static const expr uint32_t INT_DMA_END
gem5::HDLcd::fb_line_pitch
int32_t fb_line_pitch
Frame buffer Line pitch register.
Definition: hdlcd.hh:241
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::HDLcd::virtRefreshRate
const Tick virtRefreshRate
Definition: hdlcd.hh:117
gem5::HDLcd::DmaEngine::nextLineAddr
Addr nextLineAddr
Definition: hdlcd.hh:410
gem5::HDLcd::int_rawstat
uint32_t int_rawstat
Interrupt raw status register.
Definition: hdlcd.hh:235
gem5::HDLcd::H_Sync
@ H_Sync
Definition: hdlcd.hh:137
gem5::HDLcd::Int_Mask
@ Int_Mask
Definition: hdlcd.hh:126
gem5::HDLcd::blue_select
ColorSelectReg blue_select
Blue color select register.
Definition: hdlcd.hh:257
gem5::HDLcd::big_endian
Bitfield< 31 > big_endian
Definition: hdlcd.hh:215
gem5::HDLcd::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: hdlcd.cc:94
gem5::HDLcd::drainResume
void drainResume() override
Resume execution after a successful drain.
Definition: hdlcd.cc:182
gem5::HDLcd::fb_base
uint32_t fb_base
Frame buffer base address register.
Definition: hdlcd.hh:237
gem5::HDLcd::DmaEngine::DmaEngine
DmaEngine(HDLcd &_parent, size_t size, unsigned request_size, unsigned max_pending, size_t line_size, ssize_t line_pitch, unsigned num_lines)
Definition: hdlcd.cc:602
gem5::HDLcd::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: hdlcd.cc:131
gem5::HDLcd::hsync_polarity
Bitfield< 1 > hsync_polarity
Definition: hdlcd.hh:199
gem5::HDLcd::PixelPump::onUnderrun
void onUnderrun(unsigned x, unsigned y) override
Buffer underrun occurred on a frame.
Definition: hdlcd.hh:355
gem5::HDLcd::enableCapture
const bool enableCapture
Definition: hdlcd.hh:115
gem5::HDLcd::version_minor
version_minor
Definition: hdlcd.hh:170
gem5::HDLcd::Int_RawStat
@ Int_RawStat
Definition: hdlcd.hh:124
gem5::HDLcd::pxlUnderrun
void pxlUnderrun()
Definition: hdlcd.cc:549
gem5::HDLcd::Command
@ Command
Definition: hdlcd.hh:142
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::HDLcd::DmaEngine::frameEnd
Addr frameEnd
Definition: hdlcd.hh:411
gem5::HDLcd::HDLcdStats
Definition: hdlcd.hh:417
gem5::HDLcd::default_color
Bitfield< 23, 16 > default_color
Definition: hdlcd.hh:223
gem5::HDLcd::V_Sync
@ V_Sync
Definition: hdlcd.hh:133
gem5::HDLcd::getAddrRanges
AddrRangeList getAddrRanges() const override
Every PIO device is obliged to provide an implementation that returns the address ranges the device r...
Definition: hdlcd.hh:108
framebuffer.hh
gem5::Pixel
Internal gem5 representation of a Pixel.
Definition: pixel.hh:58
gem5::PixelConverter
Configurable RGB pixel converter.
Definition: pixel.hh:91
gem5::HDLcd::virtRefreshEvent
EventFunctionWrapper virtRefreshEvent
Definition: hdlcd.hh:370
gem5::HDLcd::size
Bitfield< 11, 8 > size
Definition: hdlcd.hh:221
gem5::HDLcd::v_sync
TimingReg v_sync
Vertical sync width register.
Definition: hdlcd.hh:244
gem5::HDLcd::DmaEngine::parent
HDLcd & parent
Definition: hdlcd.hh:405
gem5::HDLcd::pxlclk_polarity
Bitfield< 4 > pxlclk_polarity
Definition: hdlcd.hh:202
gem5::HDLcd::writeReg
void writeReg(Addr offset, uint32_t value)
Definition: hdlcd.cc:293
gem5::HDLcd::H_Front_Porch
@ H_Front_Porch
Definition: hdlcd.hh:140
gem5::HDLcd::PixelPump::parent
HDLcd & parent
Definition: hdlcd.hh:363
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::HDLcd::BUS_OPTIONS_RESETV
static constexpr size_t BUS_OPTIONS_RESETV
Reset value for Bus_Options register.
Definition: hdlcd.hh:150
gem5::HDLcd::DmaEngine::numLines
const unsigned numLines
Definition: hdlcd.hh:408
gem5::HDLcd::Bus_Options
@ Bus_Options
Definition: hdlcd.hh:132
gem5::HDLcd::offset
offset
Definition: hdlcd.hh:219
gem5::AmbaDmaDevice
Definition: amba_device.hh:99
gem5::HDLcd::pxlVSyncEnd
void pxlVSyncEnd()
Definition: hdlcd.cc:538
gem5::RiscvISA::x
Bitfield< 3 > x
Definition: pagetable.hh:73
gem5::HDLcd::DmaEngine::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: hdlcd.cc:624
gem5::HDLcd::intClear
void intClear(uint32_t ints)
Convenience function to clear interrupts.
Definition: hdlcd.hh:324
gem5::HDLcd::dataen_polarity
Bitfield< 2 > dataen_polarity
Definition: hdlcd.hh:200
std
Overload hash function for BasicBlockRange type.
Definition: types.hh:111
gem5::HDLcd::Blue_Select
@ Blue_Select
Definition: hdlcd.hh:146
gem5::HDLcd::pic
OutputStream * pic
Picture of what the current frame buffer looks like.
Definition: hdlcd.hh:379
gem5::HDLcd::reserved_31_1
Bitfield< 31, 1 > reserved_31_1
Definition: hdlcd.hh:208
gem5::HDLcd::intRaise
void intRaise(uint32_t ints)
Convenience function to raise a new interrupt.
Definition: hdlcd.hh:312
gem5::HDLcd::Int_Status
@ Int_Status
Definition: hdlcd.hh:127
gem5::HDLcd::pixelBufferSize
const Addr pixelBufferSize
Definition: hdlcd.hh:116
gem5::HDLcd::MAX_PIXEL_SIZE
static constexpr size_t MAX_PIXEL_SIZE
Maximum number of bytes per pixel.
Definition: hdlcd.hh:162
gem5::HDLcd::reserved_30_5
Bitfield< 30, 5 > reserved_30_5
Definition: hdlcd.hh:214
gem5::HDLcd::pixelConverter
PixelConverter pixelConverter() const
Definition: hdlcd.cc:414
gem5::HDLcd::BitUnion32
BitUnion32(VersionReg) Bitfield< 7
gem5::HDLcd::pxlNext
bool pxlNext(Pixel &p)
Definition: hdlcd.cc:499
gem5::VncInput
Definition: vncinput.hh:89
gem5::HDLcd::pxlFrameDone
void pxlFrameDone()
Definition: hdlcd.cc:558
gem5::HDLcd::workaroundDmaLineCount
const bool workaroundDmaLineCount
Definition: hdlcd.hh:113
gem5::HDLcd::DmaEngine::onIdle
void onIdle() override
Last response received callback.
Definition: hdlcd.cc:672
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::HDLcd::imgFormat
enums::ImageFormat imgFormat
Image Format.
Definition: hdlcd.hh:376
gem5::HDLcd::INT_VSYNC
static constexpr uint32_t INT_VSYNC
Definition: hdlcd.hh:177
gem5::HDLcd::PixelPump::onVSyncBegin
void onVSyncBegin() override
First pixel clock of the first VSync line.
Definition: hdlcd.hh:351
gem5::HDLcd::h_front_porch
TimingReg h_front_porch
Horizontal front porch width reg.
Definition: hdlcd.hh:251
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::HDLcd::HDLcd
HDLcd(const HDLcdParams &p)
Definition: hdlcd.cc:60
gem5::HDLcd::enabled
bool enabled() const
Definition: hdlcd.hh:273
gem5::HDLcd::pixelPump
PixelPump pixelPump
Definition: hdlcd.hh:384
gem5::HDLcd::Green_Select
@ Green_Select
Definition: hdlcd.hh:145
std::list< AddrRange >
gem5::HDLcd::setInterrupts
void setInterrupts(uint32_t ints, uint32_t mask)
Assign new interrupt values and update interrupt signals.
Definition: hdlcd.cc:588
gem5::HDLcd::reserved_2_0
reserved_2_0
Definition: hdlcd.hh:212
gem5::HDLcd::intMask
void intMask(uint32_t mask)
Convenience function to update the interrupt mask.
Definition: hdlcd.hh:303
gem5::HDLcd::workaroundSwapRB
const bool workaroundSwapRB
Definition: hdlcd.hh:112
gem5::HDLcd::DmaEngine::linePitch
const ssize_t linePitch
Definition: hdlcd.hh:407
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::HDLcd
Definition: hdlcd.hh:94
gem5::BasePixelPump
Timing generator for a pixel-based display.
Definition: pixelpump.hh:163
gem5::HDLcd::green_select
ColorSelectReg green_select
Green color select register.
Definition: hdlcd.hh:256
gem5::OutputStream
Definition: output.hh:56
gem5::HDLcd::reserved_31_24
Bitfield< 31, 24 > reserved_31_24
Definition: hdlcd.hh:224
gem5::HDLcd::v_back_porch
TimingReg v_back_porch
Vertical back porch width register.
Definition: hdlcd.hh:245
gem5::HDLcd::V_Data
@ V_Data
Definition: hdlcd.hh:135
gem5::HDLcd::DmaEngine
Definition: hdlcd.hh:387
gem5::HDLcd::VERSION_RESETV
static constexpr size_t VERSION_RESETV
Reset value for Version register.
Definition: hdlcd.hh:153
gem5::HDLcd::val
val
Definition: hdlcd.hh:193
gem5::HDLcd::reserved_15_12
Bitfield< 15, 12 > reserved_15_12
Definition: hdlcd.hh:222
gem5::HDLcd::cmdEnable
void cmdEnable()
Definition: hdlcd.cc:471
gem5::HDLcd::INT_UNDERRUN
static constexpr uint32_t INT_UNDERRUN
Definition: hdlcd.hh:178
gem5::HDLcd::h_back_porch
TimingReg h_back_porch
Horizontal back porch width reg.
Definition: hdlcd.hh:249
gem5::HDLcd::burst_len
burst_len
Definition: hdlcd.hh:186
gem5::PixelConverter::rgba8888_le
static const PixelConverter rgba8888_le
Predefined 32-bit RGB (red in least significant bits, 8 bits/channel, little endian) conversion helpe...
Definition: pixel.hh:203
gem5::HDLcd::H_Back_Porch
@ H_Back_Porch
Definition: hdlcd.hh:138

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