gem5  v21.1.0.2
dma_device.hh
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40 
41 #ifndef __DEV_DMA_DEVICE_HH__
42 #define __DEV_DMA_DEVICE_HH__
43 
44 #include <deque>
45 #include <memory>
46 
47 #include "base/addr_range_map.hh"
48 #include "base/chunk_generator.hh"
49 #include "base/circlebuf.hh"
50 #include "dev/io_device.hh"
51 #include "mem/backdoor.hh"
52 #include "params/DmaDevice.hh"
53 #include "sim/drain.hh"
54 #include "sim/system.hh"
55 
56 namespace gem5
57 {
58 
59 class ClockedObject;
60 
61 class DmaPort : public RequestPort, public Drainable
62 {
63  private:
65 
71  void trySendTimingReq();
72 
80  void sendDma();
81 
83  {
87 
89  const Addr totBytes;
90 
93 
95  const Tick delay;
96 
99 
101  uint8_t *const data = nullptr;
102 
105 
108 
110  const uint32_t sid;
111  const uint32_t ssid;
112 
115 
117  uint8_t *_data, Request::Flags _flags, RequestorID _id,
118  uint32_t _sid, uint32_t _ssid, Event *ce, Tick _delay)
119  : completionEvent(ce), totBytes(tb), delay(_delay),
120  gen(addr, tb, chunk_sz), data(_data), flags(_flags), id(_id),
121  sid(_sid), ssid(_ssid), cmd(_cmd)
122  {}
123 
125  };
126 
128  bool sendAtomicReq(DmaReqState *state);
133  bool sendAtomicBdReq(DmaReqState *state);
134 
145  void handleRespPacket(PacketPtr pkt, Tick delay=0);
146  void handleResp(DmaReqState *state, Addr addr, Addr size, Tick delay=0);
147 
148  public:
151 
154  System *const sys;
155 
158 
159  protected:
162 
165 
167  uint32_t pendingCount = 0;
168 
170  PacketPtr inRetry = nullptr;
171 
173  const uint32_t defaultSid;
174 
176  const uint32_t defaultSSid;
177 
178  const int cacheLineSize;
179 
180  protected:
181 
182  bool recvTimingResp(PacketPtr pkt) override;
183  void recvReqRetry() override;
184 
185  public:
186 
187  DmaPort(ClockedObject *dev, System *s, uint32_t sid=0, uint32_t ssid=0);
188 
189  void
190  dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
191  uint8_t *data, Tick delay, Request::Flags flag=0);
192 
193  void
194  dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
195  uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay,
196  Request::Flags flag=0);
197 
198  bool dmaPending() const { return pendingCount > 0; }
199 
200  DrainState drain() override;
201 };
202 
203 class DmaDevice : public PioDevice
204 {
205  protected:
207 
208  public:
209  typedef DmaDeviceParams Params;
210  DmaDevice(const Params &p);
211  virtual ~DmaDevice() = default;
212 
213  void
214  dmaWrite(Addr addr, int size, Event *event, uint8_t *data,
215  uint32_t sid, uint32_t ssid, Tick delay=0)
216  {
218  sid, ssid, delay);
219  }
220 
221  void
222  dmaWrite(Addr addr, int size, Event *event, uint8_t *data, Tick delay=0)
223  {
224  dmaPort.dmaAction(MemCmd::WriteReq, addr, size, event, data, delay);
225  }
226 
227  void
228  dmaRead(Addr addr, int size, Event *event, uint8_t *data,
229  uint32_t sid, uint32_t ssid, Tick delay=0)
230  {
232  sid, ssid, delay);
233  }
234 
235  void
236  dmaRead(Addr addr, int size, Event *event, uint8_t *data, Tick delay=0)
237  {
238  dmaPort.dmaAction(MemCmd::ReadReq, addr, size, event, data, delay);
239  }
240 
241  bool dmaPending() const { return dmaPort.dmaPending(); }
242 
243  void init() override;
244 
245  unsigned int cacheBlockSize() const { return sys->cacheLineSize(); }
246 
247  Port &getPort(const std::string &if_name,
248  PortID idx=InvalidPortID) override;
249 
250 };
251 
260 class DmaCallback : public Drainable
261 {
262  public:
263  virtual const std::string name() const { return "DmaCallback"; }
264 
272  DrainState
273  drain() override
274  {
276  }
277 
278  protected:
279  int count = 0;
280 
281  virtual ~DmaCallback() = default;
282 
286  virtual void process() = 0;
287 
288  private:
294  void
296  {
297  if (--count == 0) {
298  process();
299  // Need to notify DrainManager that this object is finished
300  // draining, even though it is immediately deleted.
301  signalDrainDone();
302  delete this;
303  }
304  }
305 
306  public:
307 
312  Event *
314  {
315  ++count;
316  return new EventFunctionWrapper([this]{ chunkComplete(); }, name(),
317  true);
318  }
319 };
320 
364 class DmaReadFifo : public Drainable, public Serializable
365 {
366  public:
367  DmaReadFifo(DmaPort &port, size_t size,
368  unsigned max_req_size,
369  unsigned max_pending,
370  Request::Flags flags=0);
371 
372  ~DmaReadFifo();
373 
374  public: // Serializable
375  void serialize(CheckpointOut &cp) const override;
376  void unserialize(CheckpointIn &cp) override;
377 
378  public: // Drainable
379  DrainState drain() override;
380 
381  public: // FIFO access
398  bool tryGet(uint8_t *dst, size_t len);
399 
400  template<typename T>
401  bool
402  tryGet(T &value)
403  {
404  return tryGet(static_cast<T *>(&value), sizeof(T));
405  };
406 
415  void get(uint8_t *dst, size_t len);
416 
417  template<typename T>
418  T
419  get()
420  {
421  T value;
422  get(static_cast<uint8_t *>(&value), sizeof(T));
423  return value;
424  };
425 
427  size_t size() const { return buffer.size(); }
429  void flush() { buffer.flush(); }
430 
432  public: // FIFO fill control
447  void startFill(Addr start, size_t size);
448 
457  void stopFill();
458 
463  bool atEndOfBlock() const { return nextAddr == endAddr; }
464 
469  bool
470  isActive() const
471  {
472  return !(pendingRequests.empty() && atEndOfBlock());
473  }
474 
476  protected: // Callbacks
488  virtual void onEndOfBlock() {};
489 
501  virtual void onIdle() {};
502 
504  private: // Configuration
506  const Addr maxReqSize;
508  const size_t fifoSize;
511 
513 
514  const int cacheLineSize;
515 
516  private:
517  class DmaDoneEvent : public Event
518  {
519  public:
520  DmaDoneEvent(DmaReadFifo *_parent, size_t max_size);
521 
522  void kill();
523  void cancel();
524  bool canceled() const { return _canceled; }
525  void reset(size_t size);
526  void process();
527 
528  bool done() const { return _done; }
529  size_t requestSize() const { return _requestSize; }
530  const uint8_t *data() const { return _data.data(); }
531  uint8_t *data() { return _data.data(); }
532 
533  private:
535  bool _done = false;
536  bool _canceled = false;
537  size_t _requestSize;
539  };
540 
541  typedef std::unique_ptr<DmaDoneEvent> DmaDoneEventUPtr;
542 
547  void dmaDone();
548 
550  void handlePending();
551 
553  void resumeFill();
554 
556  void resumeFillTiming();
557 
559  void resumeFillBypass();
560 
561  private: // Internal state
563 
566 
569 };
570 
571 } // namespace gem5
572 
573 #endif // __DEV_DMA_DEVICE_HH__
gem5::MipsISA::ce
Bitfield< 29, 28 > ce
Definition: pra_constants.hh:180
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::DmaReadFifo::DmaDoneEvent::data
const uint8_t * data() const
Definition: dma_device.hh:530
gem5::DmaReadFifo::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: dma_device.cc:412
gem5::DmaReadFifo::DmaDoneEvent::done
bool done() const
Definition: dma_device.hh:528
gem5::DmaPort::sendEvent
EventFunctionWrapper sendEvent
Event used to schedule a future sending from the transmit list.
Definition: dma_device.hh:164
io_device.hh
gem5::ArmISA::len
Bitfield< 18, 16 > len
Definition: misc_types.hh:444
gem5::DmaPort::device
ClockedObject *const device
The device that owns this port.
Definition: dma_device.hh:150
gem5::Fifo< uint8_t >
gem5::DmaReadFifo::endAddr
Addr endAddr
Definition: dma_device.hh:565
gem5::AddrRangeMap
The AddrRangeMap uses an STL map to implement an interval tree for address decoding.
Definition: addr_range_map.hh:62
system.hh
gem5::DmaPort::DmaReqState::ssid
const uint32_t ssid
Definition: dma_device.hh:111
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::DmaCallback::name
virtual const std::string name() const
Definition: dma_device.hh:263
gem5::DmaReadFifo::tryGet
bool tryGet(uint8_t *dst, size_t len)
Try to read data from the FIFO.
Definition: dma_device.cc:420
gem5::PioDevice
This device is the base class which all devices senstive to an address range inherit from.
Definition: io_device.hh:102
gem5::DmaReadFifo::startFill
void startFill(Addr start, size_t size)
Start filling the FIFO.
Definition: dma_device.cc:438
gem5::Fifo::flush
void flush()
Definition: circlebuf.hh:225
gem5::DmaDevice::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: dma_device.cc:363
gem5::DmaPort::DmaReqState::flags
const Request::Flags flags
The flags to use for requests.
Definition: dma_device.hh:104
gem5::DmaReadFifo::DmaDoneEvent::_requestSize
size_t _requestSize
Definition: dma_device.hh:537
gem5::DmaReadFifo::port
DmaPort & port
Definition: dma_device.hh:512
circlebuf.hh
gem5::DmaReadFifo::isActive
bool isActive() const
Is the DMA engine active (i.e., are there still in-flight accesses)?
Definition: dma_device.hh:470
gem5::DmaReadFifo
Buffered DMA engine helper class.
Definition: dma_device.hh:364
gem5::DmaReadFifo::onEndOfBlock
virtual void onEndOfBlock()
End of block callback.
Definition: dma_device.hh:488
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::DmaReadFifo::DmaDoneEvent::canceled
bool canceled() const
Definition: dma_device.hh:524
gem5::MipsISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:300
gem5::DmaPort::dmaAction
void dmaAction(Packet::Command cmd, Addr addr, int size, Event *event, uint8_t *data, Tick delay, Request::Flags flag=0)
Definition: dma_device.cc:196
gem5::MemCmd::Command
Command
List of all commands associated with a packet.
Definition: packet.hh:83
gem5::DmaPort::DmaReqState::delay
const Tick delay
Amount to delay completion of dma by.
Definition: dma_device.hh:95
gem5::DmaPort::inRetry
PacketPtr inRetry
The packet (if any) waiting for a retry to send.
Definition: dma_device.hh:170
gem5::DmaReadFifo::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: dma_device.cc:402
gem5::DmaDevice::dmaRead
void dmaRead(Addr addr, int size, Event *event, uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay=0)
Definition: dma_device.hh:228
std::vector< uint8_t >
gem5::Fifo::size
size_t size() const
Definition: circlebuf.hh:222
gem5::DmaPort::DmaReqState::DmaReqState
DmaReqState(Packet::Command _cmd, Addr addr, Addr chunk_sz, Addr tb, uint8_t *_data, Request::Flags _flags, RequestorID _id, uint32_t _sid, uint32_t _ssid, Event *ce, Tick _delay)
Definition: dma_device.hh:116
gem5::DmaReadFifo::cacheLineSize
const int cacheLineSize
Definition: dma_device.hh:514
backdoor.hh
gem5::DmaReadFifo::DmaDoneEvent::_canceled
bool _canceled
Definition: dma_device.hh:536
gem5::DmaPort::DmaReqState::gen
ChunkGenerator gen
Object to track what chunks of bytes to send at a time.
Definition: dma_device.hh:98
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:253
gem5::DmaReadFifo::DmaDoneEvent::data
uint8_t * data()
Definition: dma_device.hh:531
gem5::DmaCallback::process
virtual void process()=0
Callback function invoked on completion of all chunks.
gem5::DmaPort::DmaReqState::id
const RequestorID id
The requestor ID to use for requests.
Definition: dma_device.hh:107
gem5::DmaCallback::~DmaCallback
virtual ~DmaCallback()=default
gem5::DmaCallback::drain
DrainState drain() override
DmaPort ensures that all oustanding DMA accesses have completed before it finishes draining.
Definition: dma_device.hh:273
gem5::DmaCallback::count
int count
Definition: dma_device.hh:279
gem5::System::cacheLineSize
unsigned int cacheLineSize() const
Get the cache line size of the system.
Definition: system.hh:314
gem5::DmaCallback::getChunkEvent
Event * getChunkEvent()
Request a chunk event.
Definition: dma_device.hh:313
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::DmaPort::DmaReqState
Definition: dma_device.hh:82
gem5::DmaReadFifo::DmaDoneEvent::_data
std::vector< uint8_t > _data
Definition: dma_device.hh:538
gem5::ChunkGenerator
This class takes an arbitrary memory region (address/length pair) and generates a series of appropria...
Definition: chunk_generator.hh:59
gem5::DmaReadFifo::size
size_t size() const
Get the amount of data stored in the FIFO.
Definition: dma_device.hh:427
gem5::DmaPort::DmaReqState::totBytes
const Addr totBytes
Total number of bytes that this transaction involves.
Definition: dma_device.hh:89
gem5::DmaPort::pendingCount
uint32_t pendingCount
Number of outstanding packets the dma port has.
Definition: dma_device.hh:167
gem5::Serializable
Basic support for object serialization.
Definition: serialize.hh:169
gem5::DmaDevice::dmaPort
DmaPort dmaPort
Definition: dma_device.hh:206
gem5::Flags< FlagsType >
gem5::DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:74
gem5::DmaPort::DmaReqState::numBytes
Addr numBytes
Number of bytes that have been acked for this transaction.
Definition: dma_device.hh:92
gem5::DmaReadFifo::nextAddr
Addr nextAddr
Definition: dma_device.hh:564
gem5::DmaPort::dmaPending
bool dmaPending() const
Definition: dma_device.hh:198
gem5::DmaPort::transmitList
std::deque< DmaReqState * > transmitList
Use a deque as we never do any insertion or removal in the middle.
Definition: dma_device.hh:161
gem5::DmaReadFifo::DmaDoneEvent::DmaDoneEvent
DmaDoneEvent(DmaReadFifo *_parent, size_t max_size)
Definition: dma_device.cc:566
gem5::System
Definition: system.hh:77
gem5::DmaDevice::~DmaDevice
virtual ~DmaDevice()=default
gem5::DmaReadFifo::onIdle
virtual void onIdle()
Last response received callback.
Definition: dma_device.hh:501
gem5::DmaPort::cacheLineSize
const int cacheLineSize
Definition: dma_device.hh:178
gem5::DmaReadFifo::freeRequests
std::deque< DmaDoneEventUPtr > freeRequests
Definition: dma_device.hh:568
gem5::DmaReadFifo::tryGet
bool tryGet(T &value)
Definition: dma_device.hh:402
addr_range_map.hh
gem5::DmaDevice::dmaWrite
void dmaWrite(Addr addr, int size, Event *event, uint8_t *data, Tick delay=0)
Definition: dma_device.hh:222
gem5::Event
Definition: eventq.hh:251
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::DmaPort::sendDma
void sendDma()
For timing, attempt to send the first item on the transmit list, and if it is successful and there ar...
Definition: dma_device.cc:330
gem5::DmaDevice::dmaPending
bool dmaPending() const
Definition: dma_device.hh:241
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::DmaDevice::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: dma_device.cc:148
gem5::PioDevice::sys
System * sys
Definition: io_device.hh:105
gem5::DmaDevice::dmaRead
void dmaRead(Addr addr, int size, Event *event, uint8_t *data, Tick delay=0)
Definition: dma_device.hh:236
gem5::ArmISA::s
Bitfield< 4 > s
Definition: misc_types.hh:561
gem5::DmaReadFifo::DmaDoneEvent::cancel
void cancel()
Definition: dma_device.cc:579
gem5::MemCmd::ReadReq
@ ReadReq
Definition: packet.hh:86
gem5::DmaPort::memBackdoors
AddrRangeMap< MemBackdoorPtr, 1 > memBackdoors
Definition: dma_device.hh:64
gem5::DmaDevice
Definition: dma_device.hh:203
gem5::DmaPort::DmaReqState::cmd
const Packet::Command cmd
Command for the request.
Definition: dma_device.hh:114
gem5::DmaReadFifo::DmaDoneEvent::kill
void kill()
Definition: dma_device.cc:572
gem5::DmaReadFifo::resumeFill
void resumeFill()
Try to issue new DMA requests or bypass DMA requests.
Definition: dma_device.cc:461
gem5::DmaDevice::cacheBlockSize
unsigned int cacheBlockSize() const
Definition: dma_device.hh:245
gem5::DmaPort::DmaReqState::data
uint8_t *const data
Pointer to a buffer for the data.
Definition: dma_device.hh:101
gem5::DmaReadFifo::reqFlags
const Request::Flags reqFlags
Request flags.
Definition: dma_device.hh:510
gem5::DmaDevice::Params
DmaDeviceParams Params
Definition: dma_device.hh:209
gem5::DmaReadFifo::dmaDone
void dmaDone()
DMA request done, handle incoming data and issue new request.
Definition: dma_device.cc:528
gem5::DmaDevice::dmaWrite
void dmaWrite(Addr addr, int size, Event *event, uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay=0)
Definition: dma_device.hh:214
gem5::DrainState::Drained
@ Drained
Buffers drained, ready for serialization/handover.
gem5::DmaReadFifo::get
T get()
Definition: dma_device.hh:419
gem5::Packet::SenderState
A virtual base opaque structure used to hold state associated with the packet (e.g....
Definition: packet.hh:457
gem5::DmaReadFifo::stopFill
void stopFill()
Stop the DMA engine.
Definition: dma_device.cc:448
gem5::DmaReadFifo::DmaDoneEvent
Definition: dma_device.hh:517
gem5::DmaReadFifo::resumeFillTiming
void resumeFillTiming()
Try to issue new DMA requests during normal execution.
Definition: dma_device.cc:502
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::DmaPort::handleResp
void handleResp(DmaReqState *state, Addr addr, Addr size, Tick delay=0)
Definition: dma_device.cc:82
gem5::ClockedObject
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Definition: clocked_object.hh:234
gem5::DmaReadFifo::DmaDoneEvent::reset
void reset(size_t size)
Definition: dma_device.cc:585
gem5::DmaReadFifo::maxReqSize
const Addr maxReqSize
Maximum request size in bytes.
Definition: dma_device.hh:501
gem5::DmaReadFifo::fifoSize
const size_t fifoSize
Maximum FIFO size in bytes.
Definition: dma_device.hh:508
gem5::DmaReadFifo::atEndOfBlock
bool atEndOfBlock() const
Has the DMA engine sent out the last request for the active block?
Definition: dma_device.hh:463
gem5::DmaReadFifo::DmaDoneEvent::process
void process()
Definition: dma_device.cc:594
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::Drainable::signalDrainDone
void signalDrainDone() const
Signal that an object is drained.
Definition: drain.hh:305
gem5::DmaPort::sendAtomicReq
bool sendAtomicReq(DmaReqState *state)
Send the next packet from a DMA request in atomic mode.
Definition: dma_device.cc:244
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::DmaReadFifo::flush
void flush()
Flush the FIFO.
Definition: dma_device.hh:429
gem5::DmaPort::handleRespPacket
void handleRespPacket(PacketPtr pkt, Tick delay=0)
Handle a response packet by updating the corresponding DMA request state to reflect the bytes receive...
Definition: dma_device.cc:67
gem5::DmaPort::recvReqRetry
void recvReqRetry() override
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Definition: dma_device.cc:167
gem5::MipsISA::tb
Bitfield< 27 > tb
Definition: dt_constants.hh:77
std::deque
STL deque class.
Definition: stl.hh:44
gem5::DmaPort::recvTimingResp
bool recvTimingResp(PacketPtr pkt) override
Receive a timing response from the peer.
Definition: dma_device.cc:132
gem5::DmaPort::requestorId
const RequestorID requestorId
Id for all requests.
Definition: dma_device.hh:157
gem5::DmaPort::trySendTimingReq
void trySendTimingReq()
Take the first request on the transmit list and attempt to send a timing packet from it.
Definition: dma_device.cc:204
gem5::Drainable
Interface for objects that might require draining before checkpointing.
Definition: drain.hh:234
gem5::MemCmd::WriteReq
@ WriteReq
Definition: packet.hh:89
gem5::DmaDevice::DmaDevice
DmaDevice(const Params &p)
Definition: dma_device.cc:143
gem5::DmaPort::DmaReqState::createPacket
PacketPtr createPacket()
Definition: dma_device.cc:114
chunk_generator.hh
gem5::DmaReadFifo::buffer
Fifo< uint8_t > buffer
Definition: dma_device.hh:562
gem5::DmaCallback
DMA callback class.
Definition: dma_device.hh:260
gem5::DmaReadFifo::DmaDoneEventUPtr
std::unique_ptr< DmaDoneEvent > DmaDoneEventUPtr
Definition: dma_device.hh:541
gem5::DmaCallback::chunkComplete
void chunkComplete()
Called by DMA engine completion event on each chunk completion.
Definition: dma_device.hh:295
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::DmaPort
Definition: dma_device.hh:61
drain.hh
gem5::DmaPort::DmaPort
DmaPort(ClockedObject *dev, System *s, uint32_t sid=0, uint32_t ssid=0)
Definition: dma_device.cc:58
gem5::DmaReadFifo::DmaReadFifo
DmaReadFifo(DmaPort &port, size_t size, unsigned max_req_size, unsigned max_pending, Request::Flags flags=0)
Definition: dma_device.cc:371
gem5::RequestorID
uint16_t RequestorID
Definition: request.hh:95
gem5::DmaPort::defaultSSid
const uint32_t defaultSSid
Default substreamId.
Definition: dma_device.hh:176
gem5::DmaPort::sendAtomicBdReq
bool sendAtomicBdReq(DmaReqState *state)
Send the next packet from a DMA request in atomic mode, and request and/or use memory backdoors if po...
Definition: dma_device.cc:258
gem5::DmaPort::DmaReqState::completionEvent
Event * completionEvent
Event to call on the device when this transaction (all packets) complete.
Definition: dma_device.hh:86
gem5::DmaReadFifo::DmaDoneEvent::_done
bool _done
Definition: dma_device.hh:535
gem5::DmaPort::drain
DrainState drain() override
Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are pa...
Definition: dma_device.cc:156
gem5::DmaPort::DmaReqState::sid
const uint32_t sid
Stream IDs.
Definition: dma_device.hh:110
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::DmaPort::sys
System *const sys
The system that device/port are in.
Definition: dma_device.hh:154
gem5::DmaReadFifo::pendingRequests
std::deque< DmaDoneEventUPtr > pendingRequests
Definition: dma_device.hh:567
gem5::DmaReadFifo::handlePending
void handlePending()
Handle pending requests that have been flagged as done.
Definition: dma_device.cc:540
gem5::DmaReadFifo::DmaDoneEvent::parent
DmaReadFifo * parent
Definition: dma_device.hh:534
gem5::DmaReadFifo::~DmaReadFifo
~DmaReadFifo()
Definition: dma_device.cc:385
gem5::DmaReadFifo::drain
DrainState drain() override
Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are pa...
Definition: dma_device.cc:559
gem5::DrainState::Draining
@ Draining
Draining buffers pending serialization/handover.
gem5::DmaReadFifo::resumeFillBypass
void resumeFillBypass()
Try to bypass DMA requests in non-caching mode.
Definition: dma_device.cc:480
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::DmaPort::defaultSid
const uint32_t defaultSid
Default streamId.
Definition: dma_device.hh:173
gem5::DmaReadFifo::DmaDoneEvent::requestSize
size_t requestSize() const
Definition: dma_device.hh:529

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