gem5  v21.1.0.2
hdlcd.cc
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37 
38 #include "dev/arm/hdlcd.hh"
39 
40 #include "base/compiler.hh"
41 #include "base/output.hh"
42 #include "base/trace.hh"
43 #include "base/vnc/vncinput.hh"
44 #include "debug/Checkpoint.hh"
45 #include "debug/HDLcd.hh"
46 #include "dev/arm/amba_device.hh"
47 #include "dev/arm/base_gic.hh"
48 #include "enums/ImageFormat.hh"
49 #include "mem/packet.hh"
50 #include "mem/packet_access.hh"
51 #include "params/HDLcd.hh"
52 #include "sim/system.hh"
53 
54 using std::vector;
55 
56 namespace gem5
57 {
58 
59 // initialize hdlcd registers
60 HDLcd::HDLcd(const HDLcdParams &p)
61  : AmbaDmaDevice(p, 0xFFFF),
62  // Parameters
63  vnc(p.vnc),
64  workaroundSwapRB(p.workaround_swap_rb),
65  workaroundDmaLineCount(p.workaround_dma_line_count),
66  addrRanges{RangeSize(pioAddr, pioSize)},
67  enableCapture(p.enable_capture),
68  pixelBufferSize(p.pixel_buffer_size),
69  virtRefreshRate(p.virt_refresh_rate),
70 
71  virtRefreshEvent([this]{ virtRefresh(); }, name()),
72  // Other
73  imgFormat(p.frame_format),
74  pixelPump(*this, *p.pxl_clk, p.pixel_chunk),
75  stats(this)
76 {
77  if (vnc)
78  vnc->setFrameBuffer(&pixelPump.fb);
79 
80  imgWriter = createImgWriter(imgFormat, &pixelPump.fb);
81 }
82 
84  : statistics::Group(parent, "HDLcd"),
85  ADD_STAT(underruns, statistics::units::Count::get(),
86  "Number of buffer underruns")
87 {
88  using namespace statistics;
89 
91 }
92 
93 void
95 {
96  DPRINTF(Checkpoint, "Serializing ARM HDLCD\n");
97 
100 
106 
111 
116 
118 
124 
126  if (enabled())
127  dmaEngine->serializeSection(cp, "dmaEngine");
128 }
129 
130 void
132 {
133  DPRINTF(Checkpoint, "Unserializing ARM HDLCD\n");
134 
137 
143 
148 
153 
155 
161 
162  {
163  // Try to unserialize the pixel pump. It might not exist if
164  // we're unserializing an old checkpoint.
165  ScopedCheckpointSection sec(cp, "pixelPump");
168  }
169 
170  if (enabled()) {
171  // Create the DMA engine and read its state from the
172  // checkpoint. We don't need to worry about the pixel pump as
173  // it is a proper SimObject.
174  createDmaEngine();
175  dmaEngine->unserializeSection(cp, "dmaEngine");
176 
177  conv = pixelConverter();
178  }
179 }
180 
181 void
183 {
185 
186  if (enabled()) {
187  if (sys->bypassCaches()) {
188  // We restart the HDLCD if we are in KVM mode. This
189  // ensures that we always use the fast refresh logic if we
190  // resume in KVM mode.
191  cmdDisable();
192  cmdEnable();
193  } else if (!pixelPump.active()) {
194  // We restored from an old checkpoint without a pixel
195  // pump, start an new refresh. This typically happens when
196  // restoring from old checkpoints.
197  cmdEnable();
198  }
199  }
200 
201  // We restored from a checkpoint and need to update the VNC server
202  if (pixelPump.active() && vnc)
203  vnc->setDirty();
204 }
205 
206 void
208 {
211 }
212 
213 // read registers and frame buffer
214 Tick
216 {
217  assert(pkt->getAddr() >= pioAddr &&
218  pkt->getAddr() < pioAddr + pioSize);
219 
220  const Addr daddr = pkt->getAddr() - pioAddr;
221  panic_if(pkt->getSize() != 4,
222  "Unhandled read size (address: 0x.4x, size: %u)",
223  daddr, pkt->getSize());
224 
225  const uint32_t data = readReg(daddr);
226  DPRINTF(HDLcd, "read register 0x%04x: 0x%x\n", daddr, data);
227 
228  pkt->setLE<uint32_t>(data);
229  pkt->makeAtomicResponse();
230  return pioDelay;
231 }
232 
233 // write registers and frame buffer
234 Tick
236 {
237  assert(pkt->getAddr() >= pioAddr &&
238  pkt->getAddr() < pioAddr + pioSize);
239 
240  const Addr daddr = pkt->getAddr() - pioAddr;
241  panic_if(pkt->getSize() != 4,
242  "Unhandled read size (address: 0x.4x, size: %u)",
243  daddr, pkt->getSize());
244  const uint32_t data = pkt->getLE<uint32_t>();
245  DPRINTF(HDLcd, "write register 0x%04x: 0x%x\n", daddr, data);
246 
247  writeReg(daddr, data);
248 
249  pkt->makeAtomicResponse();
250  return pioDelay;
251 }
252 
253 uint32_t
255 {
256  switch (offset) {
257  case Version: return version;
258 
259  case Int_RawStat: return int_rawstat;
260  case Int_Clear:
261  panic("HDLCD INT_CLEAR register is Write-Only\n");
262  case Int_Mask: return int_mask;
263  case Int_Status: return intStatus();
264 
265  case Fb_Base: return fb_base;
266  case Fb_Line_Length: return fb_line_length;
267  case Fb_Line_Count: return fb_line_count;
268  case Fb_Line_Pitch: return fb_line_pitch;
269  case Bus_Options: return bus_options;
270 
271  case V_Sync: return v_sync;
272  case V_Back_Porch: return v_back_porch;
273  case V_Data: return v_data;
274  case V_Front_Porch: return v_front_porch;
275  case H_Sync: return h_sync;
276  case H_Back_Porch: return h_back_porch;
277  case H_Data: return h_data;
278  case H_Front_Porch: return h_front_porch;
279  case Polarities: return polarities;
280 
281  case Command: return command;
282  case Pixel_Format: return pixel_format;
283  case Red_Select: return red_select;
284  case Green_Select: return green_select;
285  case Blue_Select: return blue_select;
286 
287  default:
288  panic("Tried to read HDLCD register that doesn't exist\n", offset);
289  }
290 }
291 
292 void
293 HDLcd::writeReg(Addr offset, uint32_t value)
294 {
295  switch (offset) {
296  case Version:
297  panic("HDLCD VERSION register is read-Only\n");
298 
299  case Int_RawStat:
300  intRaise(value);
301  return;
302  case Int_Clear:
303  intClear(value);
304  return;
305  case Int_Mask:
306  intMask(value);
307  return;
308  case Int_Status:
309  panic("HDLCD INT_STATUS register is read-Only\n");
310  break;
311 
312  case Fb_Base:
313  fb_base = value;
314  return;
315 
316  case Fb_Line_Length:
317  fb_line_length = value;
318  return;
319 
320  case Fb_Line_Count:
321  fb_line_count = value;
322  return;
323 
324  case Fb_Line_Pitch:
325  fb_line_pitch = value;
326  return;
327 
328  case Bus_Options: {
329  const BusOptsReg old_bus_options(bus_options);
330  bus_options = value;
331 
332  if (bus_options.max_outstanding != old_bus_options.max_outstanding) {
333  DPRINTF(HDLcd,
334  "Changing HDLcd outstanding DMA transactions: %d -> %d\n",
335  old_bus_options.max_outstanding,
336  bus_options.max_outstanding);
337 
338  }
339 
340  if (bus_options.burst_len != old_bus_options.burst_len) {
341  DPRINTF(HDLcd,
342  "Changing HDLcd DMA burst flags: 0x%x -> 0x%x\n",
343  old_bus_options.burst_len, bus_options.burst_len);
344  }
345  } return;
346 
347  case V_Sync:
348  v_sync = value;
349  return;
350  case V_Back_Porch:
351  v_back_porch = value;
352  return;
353  case V_Data:
354  v_data = value;
355  return;
356  case V_Front_Porch:
357  v_front_porch = value;
358  return;
359 
360  case H_Sync:
361  h_sync = value;
362  return;
363  case H_Back_Porch:
364  h_back_porch = value;
365  return;
366  case H_Data:
367  h_data = value;
368  return;
369  case H_Front_Porch:
370  h_front_porch = value;
371  return;
372 
373  case Polarities:
374  polarities = value;
375  return;
376 
377  case Command: {
378  const CommandReg new_command(value);
379 
380  if (new_command.enable != command.enable) {
381  DPRINTF(HDLcd, "HDLCD switched %s\n",
382  new_command.enable ? "on" : "off");
383 
384  if (new_command.enable) {
385  cmdEnable();
386  } else {
387  cmdDisable();
388  }
389  }
390  command = new_command;
391  } return;
392 
393  case Pixel_Format:
394  pixel_format = value;
395  return;
396 
397  case Red_Select:
398  red_select = value;
399  return;
400  case Green_Select:
401  green_select = value;
402  return;
403  case Blue_Select:
404  blue_select = value;
405  return;
406 
407  default:
408  panic("Tried to write HDLCD register that doesn't exist\n", offset);
409  return;
410  }
411 }
412 
415 {
416  ByteOrder byte_order =
417  pixel_format.big_endian ? ByteOrder::big : ByteOrder::little;
418 
419  /* Some Linux kernels have a broken driver that swaps the red and
420  * blue color select registers. */
421  if (!workaroundSwapRB) {
422  return PixelConverter(
423  pixel_format.bytes_per_pixel + 1,
424  red_select.offset, green_select.offset, blue_select.offset,
425  red_select.size, green_select.size, blue_select.size,
426  byte_order);
427  } else {
428  return PixelConverter(
429  pixel_format.bytes_per_pixel + 1,
430  blue_select.offset, green_select.offset, red_select.offset,
431  blue_select.size, green_select.size, red_select.size,
432  byte_order);
433  }
434 }
435 
438 {
439  return DisplayTimings(
440  h_data.val + 1, v_data.val + 1,
441  h_back_porch.val + 1, h_sync.val + 1, h_front_porch.val + 1,
442  v_back_porch.val + 1, v_sync.val + 1, v_front_porch.val + 1);
443 }
444 
445 void
447 {
448  if (bus_options.max_outstanding == 0) {
449  warn("Maximum number of outstanding DMA transfers set to 0.");
450  return;
451  }
452 
453  const uint32_t dma_burst_flags = bus_options.burst_len;
454  const uint32_t dma_burst_len = dma_burst_flags ?
455  (1UL << (findMsbSet(dma_burst_flags) - 1)) : MAX_BURST_LEN;
456  // Some drivers seem to set the DMA line count incorrectly. This
457  // could either be a driver bug or a specification bug. Unlike for
458  // timings, the specification does not require 1 to be added to
459  // the DMA engine's line count.
460  const uint32_t dma_lines =
462 
463  dmaEngine.reset(new DmaEngine(
464  *this, pixelBufferSize,
465  AXI_PORT_WIDTH * dma_burst_len,
466  bus_options.max_outstanding,
467  fb_line_length, fb_line_pitch, dma_lines));
468 }
469 
470 void
472 {
473  createDmaEngine();
474  conv = pixelConverter();
475 
476  // Update timing parameter before rendering frames
478 
479  if (sys->bypassCaches()) {
481  } else {
482  pixelPump.start();
483  }
484 }
485 
486 void
488 {
489  pixelPump.stop();
490  // Disable the virtual refresh event
491  if (virtRefreshEvent.scheduled()) {
492  assert(sys->bypassCaches());
494  }
495  dmaEngine->abortFrame();
496 }
497 
498 bool
500 {
501  uint8_t pixel_data[MAX_PIXEL_SIZE];
502  assert(conv.length <= sizeof(pixel_data));
503  if (dmaEngine->tryGet(pixel_data, conv.length)) {
504  p = conv.toPixel(pixel_data);
505  return true;
506  } else {
507  return false;
508  }
509 }
510 
511 size_t
512 HDLcd::lineNext(std::vector<Pixel>::iterator pixel_it, size_t line_length)
513 {
514  const size_t byte_count = line_length * conv.length;
515 
516  lineBuffer.resize(byte_count);
517  dmaRead(bypassLineAddress, byte_count, nullptr, lineBuffer.data());
518 
520 
521  uint8_t *bufPtr = lineBuffer.data();
522  for (size_t i = 0; i < line_length; i++) {
523  *pixel_it++ = conv.toPixel(bufPtr);
524  bufPtr += conv.length;
525  }
526 
527  return line_length;
528 }
529 
530 void
532 {
533  DPRINTF(HDLcd, "Raising VSYNC interrupt.\n");
535 }
536 
537 void
539 {
540  DPRINTF(HDLcd, "End of VSYNC, starting DMA engine\n");
541  if (sys->bypassCaches()) {
543  } else {
544  dmaEngine->startFrame(fb_base);
545  }
546 }
547 
548 void
550 {
551  DPRINTF(HDLcd, "Buffer underrun, stopping DMA fill.\n");
552  ++stats.underruns;
554  dmaEngine->abortFrame();
555 }
556 
557 void
559 {
560  DPRINTF(HDLcd, "Reached end of last visible line.\n");
561 
562  if (dmaEngine->size()) {
563  warn("HDLCD %u bytes still in FIFO after frame: Ensure that DMA "
564  "and PixelPump configuration is consistent\n",
565  dmaEngine->size());
566  dmaEngine->dumpSettings();
568  }
569 
570  if (vnc)
571  vnc->setDirty();
572 
573  if (enableCapture) {
574  if (!pic) {
575  pic = simout.create(
576  csprintf("%s.framebuffer.%s",
577  sys->name(), imgWriter->getImgExtension()),
578  true);
579  }
580 
581  assert(pic);
582  pic->stream()->seekp(0);
583  imgWriter->write(*pic->stream());
584  }
585 }
586 
587 void
588 HDLcd::setInterrupts(uint32_t ints, uint32_t mask)
589 {
590  const bool old_ints = intStatus();
591 
592  int_mask = mask;
593  int_rawstat = ints;
594 
595  if (!old_ints && intStatus()) {
596  interrupt->raise();
597  } else if (old_ints && !intStatus()) {
598  interrupt->clear();
599  }
600 }
601 
603  unsigned request_size, unsigned max_pending,
604  size_t line_size, ssize_t line_pitch, unsigned num_lines)
605  : DmaReadFifo(
606  _parent.dmaPort, size, request_size, max_pending,
607  Request::UNCACHEABLE),
608  parent(_parent),
609  lineSize(line_size), linePitch(line_pitch), numLines(num_lines),
610  nextLineAddr(0)
611 {
612 }
613 
614 void
616 {
618 
619  SERIALIZE_SCALAR(nextLineAddr);
620  SERIALIZE_SCALAR(frameEnd);
621 }
622 
623 void
625 {
627 
628  UNSERIALIZE_SCALAR(nextLineAddr);
629  UNSERIALIZE_SCALAR(frameEnd);
630 }
631 
632 void
634 {
635  nextLineAddr = fb_base;
636  frameEnd = fb_base + numLines * linePitch;
637 
638  startFill(nextLineAddr, lineSize);
639 }
640 
641 void
643 {
644  nextLineAddr = frameEnd;
645  stopFill();
646  flush();
647 }
648 
649 
650 void
652 {
653  inform("DMA line size: %u bytes", lineSize);
654  inform("DMA line pitch: %i bytes", linePitch);
655  inform("DMA num lines: %u", numLines);
656 }
657 
658 void
660 {
661  if (nextLineAddr == frameEnd)
662  // We're done with this frame. Ignore calls to this method
663  // until the next frame has been started.
664  return;
665 
666  nextLineAddr += linePitch;
667  if (nextLineAddr != frameEnd)
668  startFill(nextLineAddr, lineSize);
669 }
670 
671 void
673 {
674  parent.intRaise(INT_DMA_END);
675 }
676 
677 void
679 {
680  const DisplayTimings &t = timings();
681 
682  inform("PixelPump width: %u", t.width);
683  inform("PixelPump height: %u", t.height);
684 
685  inform("PixelPump horizontal back porch: %u", t.hBackPorch);
686  inform("PixelPump horizontal fron porch: %u", t.hFrontPorch);
687  inform("PixelPump horizontal fron porch: %u", t.hSync);
688 
689  inform("PixelPump vertical back porch: %u", t.vBackPorch);
690  inform("PixelPump vertical fron porch: %u", t.vFrontPorch);
691  inform("PixelPump vertical fron porch: %u", t.vSync);
692 }
693 
694 } // namespace gem5
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::HDLcd::DmaEngine::abortFrame
void abortFrame()
Definition: hdlcd.cc:642
gem5::AmbaDmaDevice::pioAddr
Addr pioAddr
Definition: amba_device.hh:103
gem5::BasePixelPump::stop
void stop()
Immediately stop pushing pixels.
Definition: pixelpump.cc:166
gem5::HDLcd::Fb_Base
@ Fb_Base
Definition: hdlcd.hh:128
gem5::HDLcd::HDLcdStats::HDLcdStats
HDLcdStats(statistics::Group *parent)
Definition: hdlcd.cc:83
gem5::HDLcd::imgWriter
std::unique_ptr< ImgWriter > imgWriter
Helper to write out bitmaps.
Definition: hdlcd.hh:373
gem5::DmaReadFifo::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: dma_device.cc:412
gem5::HDLcd::AXI_PORT_WIDTH
static constexpr size_t AXI_PORT_WIDTH
AXI port width in bytes.
Definition: hdlcd.hh:156
gem5::HDLcd::lineNext
size_t lineNext(std::vector< Pixel >::iterator pixel_it, size_t line_length)
Definition: hdlcd.cc:512
gem5::HDLcd::cmdDisable
void cmdDisable()
Definition: hdlcd.cc:487
warn
#define warn(...)
Definition: logging.hh:245
gem5::HDLcd::v_data
TimingReg v_data
Vertical data width register.
Definition: hdlcd.hh:246
system.hh
gem5::HDLcd::Fb_Line_Length
@ Fb_Line_Length
Definition: hdlcd.hh:129
hdlcd.hh
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::HDLcd::virtRefresh
void virtRefresh()
Handler for fast frame refresh in KVM-mode.
Definition: hdlcd.cc:207
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::HDLcd::MAX_BURST_LEN
static constexpr size_t MAX_BURST_LEN
max number of beats delivered in one dma burst
Definition: hdlcd.hh:159
gem5::X86ISA::vector
Bitfield< 15, 8 > vector
Definition: intmessage.hh:48
gem5::RangeSize
AddrRange RangeSize(Addr start, Addr size)
Definition: addr_range.hh:661
gem5::HDLcd::red_select
ColorSelectReg red_select
Red color select register.
Definition: hdlcd.hh:255
gem5::DmaReadFifo
Buffered DMA engine helper class.
Definition: dma_device.hh:364
gem5::HDLcd::bypassLineAddress
Addr bypassLineAddress
Definition: hdlcd.hh:366
gem5::HDLcd::h_sync
TimingReg h_sync
Horizontal sync width register.
Definition: hdlcd.hh:248
amba_device.hh
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::HDLcd::H_Data
@ H_Data
Definition: hdlcd.hh:139
gem5::HDLcd::int_mask
uint32_t int_mask
Interrupt mask register.
Definition: hdlcd.hh:236
base_gic.hh
gem5::BasePixelPump::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: pixelpump.cc:126
vncinput.hh
gem5::HDLcd::pxlVSyncBegin
void pxlVSyncBegin()
Definition: hdlcd.cc:531
gem5::statistics::nozero
const FlagsType nozero
Don't print if this is zero.
Definition: info.hh:68
gem5::BasePixelPump::start
void start()
Starting pushing pixels in timing mode.
Definition: pixelpump.cc:159
gem5::BasePixelPump::renderFrame
void renderFrame()
Render an entire frame in non-caching mode.
Definition: pixelpump.cc:255
gem5::HDLcd::v_front_porch
TimingReg v_front_porch
Vertical front porch width register.
Definition: hdlcd.hh:247
gem5::System::bypassCaches
bool bypassCaches() const
Should caches be bypassed?
Definition: system.hh:285
gem5::HDLcd::polarities
PolaritiesReg polarities
Polarities register.
Definition: hdlcd.hh:252
gem5::simout
OutputDirectory simout
Definition: output.cc:62
gem5::HDLcd::Int_Clear
@ Int_Clear
Definition: hdlcd.hh:125
gem5::HDLcd::displayTimings
DisplayTimings displayTimings() const
Definition: hdlcd.cc:437
gem5::HDLcd::V_Back_Porch
@ V_Back_Porch
Definition: hdlcd.hh:134
gem5::HDLcd::conv
PixelConverter conv
Cached pixel converter, set when the converter is enabled.
Definition: hdlcd.hh:382
gem5::DmaReadFifo::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: dma_device.cc:402
gem5::HDLcd::max_outstanding
Bitfield< 11, 8 > max_outstanding
Definition: hdlcd.hh:188
gem5::HDLcd::readReg
uint32_t readReg(Addr offset)
Definition: hdlcd.cc:254
gem5::DmaDevice::dmaRead
void dmaRead(Addr addr, int size, Event *event, uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay=0)
Definition: dma_device.hh:228
gem5::EventManager::schedule
void schedule(Event &event, Tick when)
Definition: eventq.hh:1019
gem5::PixelConverter::toPixel
Pixel toPixel(uint32_t word) const
Get the Pixel representation of a color word.
Definition: pixel.hh:138
std::vector
STL vector class.
Definition: stl.hh:37
gem5::OutputDirectory::create
OutputStream * create(const std::string &name, bool binary=false, bool no_gz=false)
Creates a file in this directory (optionally compressed).
Definition: output.cc:210
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::Packet::makeAtomicResponse
void makeAtomicResponse()
Definition: packet.hh:1043
gem5::HDLcd::fb_line_length
uint32_t fb_line_length
Frame buffer Line length register.
Definition: hdlcd.hh:238
gem5::HDLcd::intStatus
uint32_t intStatus() const
Masked interrupt status register.
Definition: hdlcd.hh:330
gem5::HDLcd::PixelPump::dumpSettings
void dumpSettings()
Definition: hdlcd.cc:678
gem5::HDLcd::DmaEngine::dumpSettings
void dumpSettings()
Definition: hdlcd.cc:651
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::HDLcd::createDmaEngine
void createDmaEngine()
Definition: hdlcd.cc:446
gem5::HDLcd::vnc
VncInput * vnc
Definition: hdlcd.hh:111
gem5::HDLcd::Pixel_Format
@ Pixel_Format
Definition: hdlcd.hh:143
output.hh
gem5::DisplayTimings
Definition: pixelpump.hh:51
gem5::AmbaDmaDevice::pioDelay
Tick pioDelay
Definition: amba_device.hh:105
gem5::HDLcd::lineBuffer
std::vector< uint8_t > lineBuffer
Definition: hdlcd.hh:260
gem5::mask
constexpr uint64_t mask(unsigned nbits)
Generate a 64-bit mask of 'nbits' 1s, right justified.
Definition: bitfield.hh:63
gem5::HDLcd::DmaEngine::startFrame
void startFrame(Addr fb_base)
Definition: hdlcd.cc:633
gem5::HDLcd::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: hdlcd.cc:235
packet.hh
gem5::HDLcd::V_Front_Porch
@ V_Front_Porch
Definition: hdlcd.hh:136
gem5::HDLcd::pixel_format
PixelFormatReg pixel_format
Pixel format register.
Definition: hdlcd.hh:254
gem5::HDLcd::command
CommandReg command
Command register.
Definition: hdlcd.hh:253
gem5::HDLcd::HDLcdStats::underruns
statistics::Scalar underruns
Definition: hdlcd.hh:420
gem5::HDLcd::Fb_Line_Pitch
@ Fb_Line_Pitch
Definition: hdlcd.hh:131
gem5::DmaDevice::dmaPort
DmaPort dmaPort
Definition: dma_device.hh:206
gem5::HDLcd::bus_options
BusOptsReg bus_options
Bus options register.
Definition: hdlcd.hh:242
gem5::HDLcd::Version
@ Version
Definition: hdlcd.hh:123
gem5::OutputStream::stream
std::ostream * stream() const
Get the output underlying output stream.
Definition: output.hh:62
gem5::PixelConverter::length
unsigned length
Bytes per pixel when stored in memory (including padding)
Definition: pixel.hh:184
gem5::HDLcd::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: hdlcd.cc:215
gem5::HDLcd::Red_Select
@ Red_Select
Definition: hdlcd.hh:144
gem5::HDLcd::DmaEngine::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: hdlcd.cc:615
gem5::HDLcd::DmaEngine::onEndOfBlock
void onEndOfBlock() override
End of block callback.
Definition: hdlcd.cc:659
gem5::HDLcd::dmaEngine
std::unique_ptr< DmaEngine > dmaEngine
Definition: hdlcd.hh:414
gem5::HDLcd::h_data
TimingReg h_data
Horizontal data width register.
Definition: hdlcd.hh:250
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::HDLcd::fb_line_count
fb_line_count
Definition: hdlcd.hh:181
gem5::HDLcd::Polarities
@ Polarities
Definition: hdlcd.hh:141
gem5::HDLcd::Fb_Line_Count
@ Fb_Line_Count
Definition: hdlcd.hh:130
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
SERIALIZE_OBJ
#define SERIALIZE_OBJ(obj)
Definition: serialize.hh:648
ADD_STAT
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
Definition: group.hh:75
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::HDLcd::fb_line_pitch
int32_t fb_line_pitch
Frame buffer Line pitch register.
Definition: hdlcd.hh:241
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::PioDevice::sys
System * sys
Definition: io_device.hh:105
gem5::HDLcd::virtRefreshRate
const Tick virtRefreshRate
Definition: hdlcd.hh:117
gem5::ArmInterruptPin::clear
virtual void clear()=0
Clear a signalled interrupt.
gem5::HDLcd::int_rawstat
uint32_t int_rawstat
Interrupt raw status register.
Definition: hdlcd.hh:235
gem5::HDLcd::H_Sync
@ H_Sync
Definition: hdlcd.hh:137
gem5::HDLcd::Int_Mask
@ Int_Mask
Definition: hdlcd.hh:126
gem5::HDLcd::blue_select
ColorSelectReg blue_select
Blue color select register.
Definition: hdlcd.hh:257
gem5::createImgWriter
std::unique_ptr< ImgWriter > createImgWriter(enums::ImageFormat type, const FrameBuffer *fb)
Factory Function which allocates a ImgWriter object and returns a smart pointer to it.
Definition: imgwriter.cc:53
gem5::HDLcd::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: hdlcd.cc:94
gem5::VncInput::setDirty
virtual void setDirty()
The frame buffer uses this call to notify the vnc server that the frame buffer has been updated and a...
Definition: vncinput.cc:93
gem5::BasePixelPump::updateTimings
void updateTimings(const DisplayTimings &timings)
Update frame size using display timing.
Definition: pixelpump.cc:143
gem5::HDLcd::drainResume
void drainResume() override
Resume execution after a successful drain.
Definition: hdlcd.cc:182
gem5::HDLcd::fb_base
uint32_t fb_base
Frame buffer base address register.
Definition: hdlcd.hh:237
gem5::HDLcd::DmaEngine::DmaEngine
DmaEngine(HDLcd &_parent, size_t size, unsigned request_size, unsigned max_pending, size_t line_size, ssize_t line_pitch, unsigned num_lines)
Definition: hdlcd.cc:602
gem5::HDLcd::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: hdlcd.cc:131
compiler.hh
gem5::HDLcd::enableCapture
const bool enableCapture
Definition: hdlcd.hh:115
gem5::HDLcd::Int_RawStat
@ Int_RawStat
Definition: hdlcd.hh:124
gem5::HDLcd::pxlUnderrun
void pxlUnderrun()
Definition: hdlcd.cc:549
gem5::ArmISA::t
Bitfield< 5 > t
Definition: misc_types.hh:70
gem5::HDLcd::Command
@ Command
Definition: hdlcd.hh:142
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
name
const std::string & name()
Definition: trace.cc:49
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
gem5::HDLcd::V_Sync
@ V_Sync
Definition: hdlcd.hh:133
gem5::BasePixelPump::active
bool active() const
Is the pixel pump active and refreshing the display?
Definition: pixelpump.hh:192
packet_access.hh
gem5::Clocked::clockEdge
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Definition: clocked_object.hh:177
gem5::Pixel
Internal gem5 representation of a Pixel.
Definition: pixel.hh:58
gem5::PixelConverter
Configurable RGB pixel converter.
Definition: pixel.hh:91
gem5::HDLcd::virtRefreshEvent
EventFunctionWrapper virtRefreshEvent
Definition: hdlcd.hh:370
gem5::EventManager::deschedule
void deschedule(Event &event)
Definition: eventq.hh:1028
gem5::HDLcd::size
Bitfield< 11, 8 > size
Definition: hdlcd.hh:221
gem5::HDLcd::v_sync
TimingReg v_sync
Vertical sync width register.
Definition: hdlcd.hh:244
gem5::Serializable::currentSection
static const std::string & currentSection()
Gets the fully-qualified name of the active section.
Definition: serialize.cc:130
gem5::HDLcd::H_Front_Porch
@ H_Front_Porch
Definition: hdlcd.hh:140
gem5::HDLcd::writeReg
void writeReg(Addr offset, uint32_t value)
Definition: hdlcd.cc:293
gem5::HDLcd::Bus_Options
@ Bus_Options
Definition: hdlcd.hh:132
gem5::HDLcd::offset
offset
Definition: hdlcd.hh:219
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::AmbaDmaDevice
Definition: amba_device.hh:99
gem5::HDLcd::pxlVSyncEnd
void pxlVSyncEnd()
Definition: hdlcd.cc:538
inform
#define inform(...)
Definition: logging.hh:246
gem5::HDLcd::DmaEngine::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: hdlcd.cc:624
gem5::CheckpointIn::sectionExists
bool sectionExists(const std::string &section)
Definition: serialize.cc:200
gem5::Drainable::drainResume
virtual void drainResume()
Resume execution after a successful drain.
Definition: drain.hh:293
gem5::HDLcd::intClear
void intClear(uint32_t ints)
Convenience function to clear interrupts.
Definition: hdlcd.hh:324
gem5::HDLcd::Blue_Select
@ Blue_Select
Definition: hdlcd.hh:146
gem5::HDLcd::pic
OutputStream * pic
Picture of what the current frame buffer looks like.
Definition: hdlcd.hh:379
gem5::Request
Definition: request.hh:97
gem5::HDLcd::intRaise
void intRaise(uint32_t ints)
Convenience function to raise a new interrupt.
Definition: hdlcd.hh:312
gem5::HDLcd::Int_Status
@ Int_Status
Definition: hdlcd.hh:127
gem5::HDLcd::pixelBufferSize
const Addr pixelBufferSize
Definition: hdlcd.hh:116
gem5::HDLcd::MAX_PIXEL_SIZE
static constexpr size_t MAX_PIXEL_SIZE
Maximum number of bytes per pixel.
Definition: hdlcd.hh:162
gem5::AmbaDmaDevice::interrupt
ArmInterruptPin *const interrupt
Definition: amba_device.hh:106
gem5::HDLcd::pixelConverter
PixelConverter pixelConverter() const
Definition: hdlcd.cc:414
gem5::HDLcd::pxlNext
bool pxlNext(Pixel &p)
Definition: hdlcd.cc:499
gem5::HDLcd::pxlFrameDone
void pxlFrameDone()
Definition: hdlcd.cc:558
gem5::AmbaDmaDevice::pioSize
Addr pioSize
Definition: amba_device.hh:104
gem5::HDLcd::workaroundDmaLineCount
const bool workaroundDmaLineCount
Definition: hdlcd.hh:113
gem5::HDLcd::DmaEngine::onIdle
void onIdle() override
Last response received callback.
Definition: hdlcd.cc:672
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::statistics::Group::stats
std::vector< Info * > stats
Definition: group.hh:221
gem5::Packet::getLE
T getLE() const
Get the data in the packet byte swapped from little endian to host endian.
Definition: packet_access.hh:78
gem5::HDLcd::INT_VSYNC
static constexpr uint32_t INT_VSYNC
Definition: hdlcd.hh:177
gem5::HDLcd::h_front_porch
TimingReg h_front_porch
Horizontal front porch width reg.
Definition: hdlcd.hh:251
gem5::findMsbSet
constexpr int findMsbSet(uint64_t val)
Returns the bit position of the MSB that is set in the input.
Definition: bitfield.hh:263
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::HDLcd::HDLcd
HDLcd(const HDLcdParams &p)
Definition: hdlcd.cc:60
gem5::ArmInterruptPin::raise
virtual void raise()=0
Signal an interrupt.
gem5::HDLcd::enabled
bool enabled() const
Definition: hdlcd.hh:273
trace.hh
gem5::Packet::setLE
void setLE(T v)
Set the value in the data pointer to v as little endian.
Definition: packet_access.hh:108
gem5::HDLcd::pixelPump
PixelPump pixelPump
Definition: hdlcd.hh:384
gem5::statistics::DataWrap::flags
Derived & flags(Flags _flags)
Set the flags and marks this stat to print at the end of simulation.
Definition: statistics.hh:355
gem5::HDLcd::Green_Select
@ Green_Select
Definition: hdlcd.hh:145
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
gem5::HDLcd::setInterrupts
void setInterrupts(uint32_t ints, uint32_t mask)
Assign new interrupt values and update interrupt signals.
Definition: hdlcd.cc:588
gem5::HDLcd::intMask
void intMask(uint32_t mask)
Convenience function to update the interrupt mask.
Definition: hdlcd.hh:303
gem5::HDLcd::workaroundSwapRB
const bool workaroundSwapRB
Definition: hdlcd.hh:112
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::HDLcd
Definition: hdlcd.hh:94
gem5::HDLcd::green_select
ColorSelectReg green_select
Green color select register.
Definition: hdlcd.hh:256
gem5::Serializable::ScopedCheckpointSection
Definition: serialize.hh:172
gem5::HDLcd::v_back_porch
TimingReg v_back_porch
Vertical back porch width register.
Definition: hdlcd.hh:245
gem5::HDLcd::V_Data
@ V_Data
Definition: hdlcd.hh:135
gem5::HDLcd::DmaEngine
Definition: hdlcd.hh:387
gem5::Packet::getSize
unsigned getSize() const
Definition: packet.hh:791
gem5::HDLcd::cmdEnable
void cmdEnable()
Definition: hdlcd.cc:471
gem5::HDLcd::INT_UNDERRUN
static constexpr uint32_t INT_UNDERRUN
Definition: hdlcd.hh:178
gem5::HDLcd::h_back_porch
TimingReg h_back_porch
Horizontal back porch width reg.
Definition: hdlcd.hh:249
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
gem5::HDLcd::burst_len
burst_len
Definition: hdlcd.hh:186
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::HDLcd::H_Back_Porch
@ H_Back_Porch
Definition: hdlcd.hh:138

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