gem5  v22.0.0.2
static_inst.hh
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37 
38 #ifndef __ARCH_X86_INSTS_STATICINST_HH__
39 #define __ARCH_X86_INSTS_STATICINST_HH__
40 
41 #include "arch/x86/pcstate.hh"
42 #include "arch/x86/regs/int.hh"
43 #include "arch/x86/types.hh"
44 #include "base/trace.hh"
45 #include "cpu/static_inst.hh"
46 #include "cpu/thread_context.hh"
47 #include "debug/X86.hh"
48 
49 namespace gem5
50 {
51 
52 namespace X86ISA
53 {
54 
60 struct GpRegIndex
61 {
63  explicit GpRegIndex(RegIndex idx) : index(idx) {}
64 };
65 
66 struct FpRegIndex
67 {
69  explicit FpRegIndex(RegIndex idx) : index(idx) {}
70 };
71 
73 {
75  explicit CtrlRegIndex(RegIndex idx) : index(idx) {}
76 };
77 
78 struct CrRegIndex
79 {
81  explicit CrRegIndex(RegIndex idx) : index(idx) {}
82 };
83 
85 {
87  explicit DbgRegIndex(RegIndex idx) : index(idx) {}
88 };
89 
91 {
93  explicit SegRegIndex(RegIndex idx) : index(idx) {}
94 };
95 
100 class X86StaticInst : public StaticInst
101 {
102  public:
103  static void printMnemonic(std::ostream &os, const char *mnemonic);
104  static void printMnemonic(std::ostream &os, const char *instMnemonic,
105  const char *mnemonic);
106  static void printMem(std::ostream &os, uint8_t segment,
107  uint8_t scale, RegIndex index, RegIndex base,
108  uint64_t disp, uint8_t addressSize, bool rip);
109 
110  static void printSegment(std::ostream &os, int segment);
111 
112  static void printReg(std::ostream &os, RegId reg, int size);
113 
114  protected:
116 
117  public:
119 
120  protected:
121  // Constructor.
122  X86StaticInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
123  StaticInst(mnem, __opClass), machInst(_machInst)
124  {}
125 
126  std::string generateDisassembly(
127  Addr pc, const loader::SymbolTable *symtab) const override;
128 
129  static void divideStep(uint64_t divident, uint64_t divisor,
130  uint64_t &quotient, uint64_t &remainder);
131 
132  static inline uint64_t
133  merge(uint64_t into, RegIndex index, uint64_t val, int size)
134  {
135  X86IntReg reg = into;
136  if (index & IntFoldBit) {
137  reg.H = val;
138  return reg;
139  }
140  switch(size) {
141  case 1:
142  reg.L = val;
143  break;
144  case 2:
145  reg.X = val;
146  break;
147  case 4:
148  //XXX Check if this should be zeroed or sign extended
149  reg = 0;
150  reg.E = val;
151  break;
152  case 8:
153  reg.R = val;
154  break;
155  default:
156  panic("Tried to merge with unrecognized size %d.\n", size);
157  }
158  return reg;
159  }
160 
161  static inline uint64_t
162  pick(uint64_t from, RegIndex index, int size)
163  {
164  X86IntReg reg = from;
165  DPRINTF(X86, "Picking with size %d\n", size);
166  if (index & IntFoldBit)
167  return reg.H;
168  switch(size) {
169  case 1:
170  return reg.L;
171  case 2:
172  return reg.X;
173  case 4:
174  return reg.E;
175  case 8:
176  return reg.R;
177  default:
178  panic("Tried to pick with unrecognized size %d.\n", size);
179  }
180  }
181 
182  static inline int64_t
183  signedPick(uint64_t from, RegIndex index, int size)
184  {
185  X86IntReg reg = from;
186  DPRINTF(X86, "Picking with size %d\n", size);
187  if (index & IntFoldBit)
188  return reg.SH;
189  switch(size) {
190  case 1:
191  return reg.SL;
192  case 2:
193  return reg.SX;
194  case 4:
195  return reg.SE;
196  case 8:
197  return reg.SR;
198  default:
199  panic("Tried to pick with unrecognized size %d.\n", size);
200  }
201  }
202 
203  void
204  advancePC(PCStateBase &pcState) const override
205  {
206  pcState.as<PCState>().advance();
207  }
208 
209  void
210  advancePC(ThreadContext *tc) const override
211  {
212  PCState pc = tc->pcState().as<PCState>();
213  pc.advance();
214  tc->pcState(pc);
215  }
216 
217  std::unique_ptr<PCStateBase>
218  buildRetPC(const PCStateBase &cur_pc,
219  const PCStateBase &call_pc) const override
220  {
221  PCStateBase *ret_pc_ptr = call_pc.clone();
222  ret_pc_ptr->as<PCState>().uEnd();
223  return std::unique_ptr<PCStateBase>{ret_pc_ptr};
224  }
225 };
226 
227 } // namespace X86ISA
228 } // namespace gem5
229 
230 #endif //__ARCH_X86_INSTS_STATICINST_HH__
gem5::X86ISA::FpRegIndex
Definition: static_inst.hh:66
gem5::X86ISA::pc
Bitfield< 19 > pc
Definition: misc.hh:805
gem5::X86ISA::CtrlRegIndex::index
RegIndex index
Definition: static_inst.hh:74
pcstate.hh
gem5::X86ISA::SegRegIndex::SegRegIndex
SegRegIndex(RegIndex idx)
Definition: static_inst.hh:93
gem5::X86ISA::GpRegIndex
Classes for register indices passed to instruction constructors.
Definition: static_inst.hh:60
gem5::X86ISA::X86StaticInst::merge
static uint64_t merge(uint64_t into, RegIndex index, uint64_t val, int size)
Definition: static_inst.hh:133
gem5::X86ISA::X86StaticInst::divideStep
static void divideStep(uint64_t divident, uint64_t divisor, uint64_t &quotient, uint64_t &remainder)
Definition: static_inst.cc:112
gem5::X86ISA::X86StaticInst::buildRetPC
std::unique_ptr< PCStateBase > buildRetPC(const PCStateBase &cur_pc, const PCStateBase &call_pc) const override
Definition: static_inst.hh:218
gem5::X86ISA::CrRegIndex
Definition: static_inst.hh:78
gem5::X86ISA::scale
scale
Definition: types.hh:97
gem5::PCStateBase::as
Target & as()
Definition: pcstate.hh:72
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::X86ISA::X86StaticInst::printMem
static void printMem(std::ostream &os, uint8_t segment, uint8_t scale, RegIndex index, RegIndex base, uint64_t disp, uint8_t addressSize, bool rip)
Definition: static_inst.cc:258
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::X86ISA::X86StaticInst::advancePC
void advancePC(ThreadContext *tc) const override
Definition: static_inst.hh:210
gem5::X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
sc_dt::remainder
return remainder
Definition: scfx_rep.cc:2201
gem5::X86ISA::SegRegIndex::index
RegIndex index
Definition: static_inst.hh:92
gem5::X86ISA::FpRegIndex::index
RegIndex index
Definition: static_inst.hh:68
gem5::StaticInst
Base, ISA-independent static instruction class.
Definition: static_inst.hh:88
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
int.hh
gem5::MipsISA::ExtMachInst
uint64_t ExtMachInst
Definition: types.hh:43
gem5::X86ISA::FpRegIndex::FpRegIndex
FpRegIndex(RegIndex idx)
Definition: static_inst.hh:69
gem5::X86ISA::X86StaticInst::pick
static uint64_t pick(uint64_t from, RegIndex index, int size)
Definition: static_inst.hh:162
static_inst.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::X86StaticInst::printReg
static void printReg(std::ostream &os, RegId reg, int size)
Definition: static_inst.cc:142
gem5::X86ISA::CtrlRegIndex::CtrlRegIndex
CtrlRegIndex(RegIndex idx)
Definition: static_inst.hh:75
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::X86ISA::ExtMachInst
Definition: types.hh:212
gem5::X86ISA::GpRegIndex::index
RegIndex index
Definition: static_inst.hh:62
gem5::X86ISA::X86StaticInst
Base class for all X86 static instructions.
Definition: static_inst.hh:100
gem5::X86ISA::X86StaticInst::X86StaticInst
X86StaticInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: static_inst.hh:122
gem5::X86ISA::X86StaticInst::printSegment
static void printSegment(std::ostream &os, int segment)
Definition: static_inst.cc:63
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:803
gem5::X86ISA::index
Bitfield< 5, 3 > index
Definition: types.hh:98
gem5::X86ISA::X86StaticInst::machInst
ExtMachInst machInst
Definition: static_inst.hh:118
gem5::X86ISA::X86StaticInst::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: static_inst.cc:294
gem5::X86ISA::PCState
Definition: pcstate.hh:50
gem5::X86ISA::GpRegIndex::GpRegIndex
GpRegIndex(RegIndex idx)
Definition: static_inst.hh:63
gem5::X86ISA::CrRegIndex::index
RegIndex index
Definition: static_inst.hh:80
gem5::X86ISA::X86StaticInst::advancePC
void advancePC(PCStateBase &pcState) const override
Definition: static_inst.hh:204
trace.hh
gem5::X86ISA::IntFoldBit
constexpr RegIndex IntFoldBit
Definition: int.hh:149
gem5::X86ISA::CtrlRegIndex
Definition: static_inst.hh:72
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:259
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::X86ISA::SegRegIndex
Definition: static_inst.hh:90
gem5::X86ISA::DbgRegIndex::index
RegIndex index
Definition: static_inst.hh:86
types.hh
thread_context.hh
gem5::X86ISA::CrRegIndex::CrRegIndex
CrRegIndex(RegIndex idx)
Definition: static_inst.hh:81
gem5::X86ISA::DbgRegIndex::DbgRegIndex
DbgRegIndex(RegIndex idx)
Definition: static_inst.hh:87
gem5::X86ISA::X86StaticInst::signedPick
static int64_t signedPick(uint64_t from, RegIndex index, int size)
Definition: static_inst.hh:183
gem5::PCStateBase::clone
virtual PCStateBase * clone() const =0
gem5::X86ISA::DbgRegIndex
Definition: static_inst.hh:84
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::X86ISA::X86StaticInst::printMnemonic
static void printMnemonic(std::ostream &os, const char *mnemonic)
Definition: static_inst.cc:51

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