gem5  v21.1.0.2
static_inst.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2007 The Hewlett-Packard Development Company
3  * All rights reserved.
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Redistribution and use in source and binary forms, with or without
15  * modification, are permitted provided that the following conditions are
16  * met: redistributions of source code must retain the above copyright
17  * notice, this list of conditions and the following disclaimer;
18  * redistributions in binary form must reproduce the above copyright
19  * notice, this list of conditions and the following disclaimer in the
20  * documentation and/or other materials provided with the distribution;
21  * neither the name of the copyright holders nor the names of its
22  * contributors may be used to endorse or promote products derived from
23  * this software without specific prior written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  */
37 
38 #ifndef __ARCH_X86_INSTS_STATICINST_HH__
39 #define __ARCH_X86_INSTS_STATICINST_HH__
40 
41 #include "arch/x86/types.hh"
42 #include "base/trace.hh"
43 #include "cpu/static_inst.hh"
44 #include "debug/X86.hh"
45 
46 namespace gem5
47 {
48 
49 namespace X86ISA
50 {
51 
57 struct GpRegIndex
58 {
60  explicit GpRegIndex(RegIndex idx) : index(idx) {}
61 };
62 
63 struct FpRegIndex
64 {
66  explicit FpRegIndex(RegIndex idx) : index(idx) {}
67 };
68 
70 {
72  explicit CtrlRegIndex(RegIndex idx) : index(idx) {}
73 };
74 
75 struct CrRegIndex
76 {
78  explicit CrRegIndex(RegIndex idx) : index(idx) {}
79 };
80 
82 {
84  explicit DbgRegIndex(RegIndex idx) : index(idx) {}
85 };
86 
88 {
90  explicit SegRegIndex(RegIndex idx) : index(idx) {}
91 };
92 
97 class X86StaticInst : public StaticInst
98 {
99  public:
100  static void printMnemonic(std::ostream &os, const char *mnemonic);
101  static void printMnemonic(std::ostream &os, const char *instMnemonic,
102  const char *mnemonic);
103  static void printMem(std::ostream &os, uint8_t segment,
104  uint8_t scale, RegIndex index, RegIndex base,
105  uint64_t disp, uint8_t addressSize, bool rip);
106 
107  static void printSegment(std::ostream &os, int segment);
108 
109  static void printReg(std::ostream &os, RegId reg, int size);
110 
111  protected:
113 
114  public:
116 
117  protected:
118  // Constructor.
119  X86StaticInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
120  StaticInst(mnem, __opClass), machInst(_machInst)
121  {}
122 
123  std::string generateDisassembly(
124  Addr pc, const loader::SymbolTable *symtab) const override;
125 
126  static void divideStep(uint64_t divident, uint64_t divisor,
127  uint64_t &quotient, uint64_t &remainder);
128 
129  static inline uint64_t
130  merge(uint64_t into, RegIndex index, uint64_t val, int size)
131  {
132  X86IntReg reg = into;
133  if (index & IntFoldBit) {
134  reg.H = val;
135  return reg;
136  }
137  switch(size) {
138  case 1:
139  reg.L = val;
140  break;
141  case 2:
142  reg.X = val;
143  break;
144  case 4:
145  //XXX Check if this should be zeroed or sign extended
146  reg = 0;
147  reg.E = val;
148  break;
149  case 8:
150  reg.R = val;
151  break;
152  default:
153  panic("Tried to merge with unrecognized size %d.\n", size);
154  }
155  return reg;
156  }
157 
158  static inline uint64_t
159  pick(uint64_t from, RegIndex index, int size)
160  {
161  X86IntReg reg = from;
162  DPRINTF(X86, "Picking with size %d\n", size);
163  if (index & IntFoldBit)
164  return reg.H;
165  switch(size) {
166  case 1:
167  return reg.L;
168  case 2:
169  return reg.X;
170  case 4:
171  return reg.E;
172  case 8:
173  return reg.R;
174  default:
175  panic("Tried to pick with unrecognized size %d.\n", size);
176  }
177  }
178 
179  static inline int64_t
180  signedPick(uint64_t from, RegIndex index, int size)
181  {
182  X86IntReg reg = from;
183  DPRINTF(X86, "Picking with size %d\n", size);
184  if (index & IntFoldBit)
185  return reg.SH;
186  switch(size) {
187  case 1:
188  return reg.SL;
189  case 2:
190  return reg.SX;
191  case 4:
192  return reg.SE;
193  case 8:
194  return reg.SR;
195  default:
196  panic("Tried to pick with unrecognized size %d.\n", size);
197  }
198  }
199 
200  void
201  advancePC(PCState &pcState) const override
202  {
203  pcState.advance();
204  }
205 
206  PCState
207  buildRetPC(const PCState &curPC, const PCState &callPC) const override
208  {
209  PCState retPC = callPC;
210  retPC.uEnd();
211  return retPC;
212  }
213 };
214 
215 } // namespace X86ISA
216 } // namespace gem5
217 
218 #endif //__ARCH_X86_INSTS_STATICINST_HH__
gem5::X86ISA::FpRegIndex
Definition: static_inst.hh:63
gem5::X86ISA::pc
Bitfield< 19 > pc
Definition: misc.hh:811
gem5::X86ISA::CtrlRegIndex::index
RegIndex index
Definition: static_inst.hh:71
gem5::X86ISA::SegRegIndex::SegRegIndex
SegRegIndex(RegIndex idx)
Definition: static_inst.hh:90
gem5::X86ISA::GpRegIndex
Classes for register indices passed to instruction constructors.
Definition: static_inst.hh:57
gem5::X86ISA::X86StaticInst::merge
static uint64_t merge(uint64_t into, RegIndex index, uint64_t val, int size)
Definition: static_inst.hh:130
gem5::X86ISA::X86StaticInst::divideStep
static void divideStep(uint64_t divident, uint64_t divisor, uint64_t &quotient, uint64_t &remainder)
Definition: static_inst.cc:112
gem5::X86ISA::CrRegIndex
Definition: static_inst.hh:75
gem5::X86ISA::scale
scale
Definition: types.hh:97
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::X86ISA::X86StaticInst::printMem
static void printMem(std::ostream &os, uint8_t segment, uint8_t scale, RegIndex index, RegIndex base, uint64_t disp, uint8_t addressSize, bool rip)
Definition: static_inst.cc:257
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::X86ISA::PCState::uEnd
void uEnd()
Definition: pcstate.hh:93
gem5::X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
sc_dt::remainder
return remainder
Definition: scfx_rep.cc:2201
gem5::X86ISA::SegRegIndex::index
RegIndex index
Definition: static_inst.hh:89
gem5::X86ISA::FpRegIndex::index
RegIndex index
Definition: static_inst.hh:65
gem5::StaticInst
Base, ISA-independent static instruction class.
Definition: static_inst.hh:88
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::MipsISA::ExtMachInst
uint64_t ExtMachInst
Definition: types.hh:43
gem5::X86ISA::FpRegIndex::FpRegIndex
FpRegIndex(RegIndex idx)
Definition: static_inst.hh:66
gem5::X86ISA::X86StaticInst::pick
static uint64_t pick(uint64_t from, RegIndex index, int size)
Definition: static_inst.hh:159
static_inst.hh
gem5::X86ISA::PCState::advance
void advance()
Definition: pcstate.hh:86
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::X86StaticInst::printReg
static void printReg(std::ostream &os, RegId reg, int size)
Definition: static_inst.cc:142
gem5::X86ISA::CtrlRegIndex::CtrlRegIndex
CtrlRegIndex(RegIndex idx)
Definition: static_inst.hh:72
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::X86ISA::GpRegIndex::index
RegIndex index
Definition: static_inst.hh:59
gem5::X86ISA::X86StaticInst
Base class for all X86 static instructions.
Definition: static_inst.hh:97
gem5::X86ISA::X86StaticInst::X86StaticInst
X86StaticInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: static_inst.hh:119
gem5::X86ISA::X86StaticInst::printSegment
static void printSegment(std::ostream &os, int segment)
Definition: static_inst.cc:63
gem5::X86ISA::X86StaticInst::buildRetPC
PCState buildRetPC(const PCState &curPC, const PCState &callPC) const override
Definition: static_inst.hh:207
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:809
gem5::X86ISA::index
Bitfield< 5, 3 > index
Definition: types.hh:98
gem5::X86ISA::X86StaticInst::machInst
ExtMachInst machInst
Definition: static_inst.hh:115
gem5::X86ISA::X86StaticInst::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: static_inst.cc:293
gem5::X86ISA::PCState
Definition: pcstate.hh:50
gem5::X86ISA::X86StaticInst::advancePC
void advancePC(PCState &pcState) const override
Definition: static_inst.hh:201
gem5::X86ISA::GpRegIndex::GpRegIndex
GpRegIndex(RegIndex idx)
Definition: static_inst.hh:60
gem5::X86ISA::CrRegIndex::index
RegIndex index
Definition: static_inst.hh:77
trace.hh
gem5::X86ISA::CtrlRegIndex
Definition: static_inst.hh:69
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:281
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::X86ISA::SegRegIndex
Definition: static_inst.hh:87
gem5::X86ISA::DbgRegIndex::index
RegIndex index
Definition: static_inst.hh:83
types.hh
gem5::X86ISA::CrRegIndex::CrRegIndex
CrRegIndex(RegIndex idx)
Definition: static_inst.hh:78
gem5::X86ISA::DbgRegIndex::DbgRegIndex
DbgRegIndex(RegIndex idx)
Definition: static_inst.hh:84
gem5::X86ISA::X86StaticInst::signedPick
static int64_t signedPick(uint64_t from, RegIndex index, int size)
Definition: static_inst.hh:180
gem5::X86ISA::DbgRegIndex
Definition: static_inst.hh:81
gem5::X86ISA::IntFoldBit
static const IntRegIndex IntFoldBit
Definition: int.hh:172
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::X86ISA::X86StaticInst::printMnemonic
static void printMnemonic(std::ostream &os, const char *mnemonic)
Definition: static_inst.cc:51

Generated on Tue Sep 21 2021 12:24:35 for gem5 by doxygen 1.8.17