gem5 v24.0.0.0
Loading...
Searching...
No Matches
static_inst.hh
Go to the documentation of this file.
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#ifndef __ARCH_X86_INSTS_STATICINST_HH__
39#define __ARCH_X86_INSTS_STATICINST_HH__
40
41#include "arch/x86/pcstate.hh"
42#include "arch/x86/regs/int.hh"
43#include "arch/x86/types.hh"
44#include "base/trace.hh"
45#include "cpu/static_inst.hh"
46#include "cpu/thread_context.hh"
47#include "debug/X86.hh"
48
49namespace gem5
50{
51
52namespace X86ISA
53{
54
61{
63 explicit GpRegIndex(RegIndex idx) : index(idx) {}
64};
65
67{
69 explicit FpRegIndex(RegIndex idx) : index(idx) {}
70};
71
73{
75 explicit CtrlRegIndex(RegIndex idx) : index(idx) {}
76};
77
79{
81 explicit CrRegIndex(RegIndex idx) : index(idx) {}
82};
83
85{
87 explicit DbgRegIndex(RegIndex idx) : index(idx) {}
88};
89
91{
93 explicit SegRegIndex(RegIndex idx) : index(idx) {}
94};
95
101{
102 public:
103 static void printMnemonic(std::ostream &os, const char *mnemonic);
104 static void printMnemonic(std::ostream &os, const char *instMnemonic,
105 const char *mnemonic);
106 static void printMem(std::ostream &os, uint8_t segment,
107 uint8_t scale, RegIndex index, RegIndex base,
108 uint64_t disp, uint8_t addressSize, bool rip);
109
110 static void printSegment(std::ostream &os, int segment);
111
112 static void printReg(std::ostream &os, RegId reg, int size);
113
114 protected:
116
117 public:
119
120 protected:
121 // Constructor.
122 X86StaticInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
123 StaticInst(mnem, __opClass), machInst(_machInst)
124 {}
125
126 std::string generateDisassembly(
127 Addr pc, const loader::SymbolTable *symtab) const override;
128
129 static void divideStep(uint64_t divident, uint64_t divisor,
130 uint64_t &quotient, uint64_t &remainder);
131
132 static inline uint64_t
133 merge(uint64_t into, RegIndex index, uint64_t val, int size)
134 {
135 X86IntReg reg = into;
136 if (index & IntFoldBit) {
137 reg.H = val;
138 return reg;
139 }
140 switch(size) {
141 case 1:
142 reg.L = val;
143 break;
144 case 2:
145 reg.X = val;
146 break;
147 case 4:
148 //XXX Check if this should be zeroed or sign extended
149 reg = 0;
150 reg.E = val;
151 break;
152 case 8:
153 reg.R = val;
154 break;
155 default:
156 panic("Tried to merge with unrecognized size %d.\n", size);
157 }
158 return reg;
159 }
160
161 static inline uint64_t
162 pick(uint64_t from, RegIndex index, int size)
163 {
164 X86IntReg reg = from;
165 DPRINTF(X86, "Picking with size %d\n", size);
166 if (index & IntFoldBit)
167 return reg.H;
168 switch(size) {
169 case 1:
170 return reg.L;
171 case 2:
172 return reg.X;
173 case 4:
174 return reg.E;
175 case 8:
176 return reg.R;
177 default:
178 panic("Tried to pick with unrecognized size %d.\n", size);
179 }
180 }
181
182 static inline int64_t
183 signedPick(uint64_t from, RegIndex index, int size)
184 {
185 X86IntReg reg = from;
186 DPRINTF(X86, "Picking with size %d\n", size);
187 if (index & IntFoldBit)
188 return reg.SH;
189 switch(size) {
190 case 1:
191 return reg.SL;
192 case 2:
193 return reg.SX;
194 case 4:
195 return reg.SE;
196 case 8:
197 return reg.SR;
198 default:
199 panic("Tried to pick with unrecognized size %d.\n", size);
200 }
201 }
202
203 void
204 advancePC(PCStateBase &pcState) const override
205 {
206 pcState.as<PCState>().advance();
207 }
208
209 void
210 advancePC(ThreadContext *tc) const override
211 {
212 PCState pc = tc->pcState().as<PCState>();
213 pc.advance();
214 tc->pcState(pc);
215 }
216
217 std::unique_ptr<PCStateBase>
218 buildRetPC(const PCStateBase &cur_pc,
219 const PCStateBase &call_pc) const override
220 {
221 PCStateBase *ret_pc_ptr = call_pc.clone();
222 ret_pc_ptr->as<PCState>().uEnd();
223 return std::unique_ptr<PCStateBase>{ret_pc_ptr};
224 }
225};
226
227} // namespace X86ISA
228} // namespace gem5
229
230#endif //__ARCH_X86_INSTS_STATICINST_HH__
#define DPRINTF(x,...)
Definition trace.hh:210
Target & as()
Definition pcstate.hh:73
virtual PCStateBase * clone() const =0
Register ID: describe an architectural register with its class and index.
Definition reg_class.hh:94
Base, ISA-independent static instruction class.
size_t size() const
const char * mnemonic
Base mnemonic (e.g., "add").
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual const PCStateBase & pcState() const =0
void advance() override
Definition pcstate.hh:98
Base class for all X86 static instructions.
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
std::unique_ptr< PCStateBase > buildRetPC(const PCStateBase &cur_pc, const PCStateBase &call_pc) const override
static void printMem(std::ostream &os, uint8_t segment, uint8_t scale, RegIndex index, RegIndex base, uint64_t disp, uint8_t addressSize, bool rip)
static void printSegment(std::ostream &os, int segment)
static void printMnemonic(std::ostream &os, const char *mnemonic)
static void divideStep(uint64_t divident, uint64_t divisor, uint64_t &quotient, uint64_t &remainder)
void advancePC(PCStateBase &pcState) const override
static void printReg(std::ostream &os, RegId reg, int size)
static uint64_t merge(uint64_t into, RegIndex index, uint64_t val, int size)
X86StaticInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
static int64_t signedPick(uint64_t from, RegIndex index, int size)
void advancePC(ThreadContext *tc) const override
static uint64_t pick(uint64_t from, RegIndex index, int size)
#define panic(...)
This implements a cprintf based panic() function.
Definition logging.hh:188
Bitfield< 19 > pc
Definition misc.hh:840
Bitfield< 5, 3 > reg
Definition types.hh:92
Bitfield< 51, 12 > base
Definition pagetable.hh:141
Bitfield< 17 > os
Definition misc.hh:838
Bitfield< 63 > val
Definition misc.hh:804
Bitfield< 5, 3 > index
Definition types.hh:98
constexpr RegIndex IntFoldBit
Definition int.hh:178
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
uint16_t RegIndex
Definition types.hh:176
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
Classes for register indices passed to instruction constructors.

Generated on Tue Jun 18 2024 16:24:02 for gem5 by doxygen 1.11.0