gem5  v21.2.1.1
static_inst.hh
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37 
38 #ifndef __ARCH_X86_INSTS_STATICINST_HH__
39 #define __ARCH_X86_INSTS_STATICINST_HH__
40 
41 #include "arch/x86/pcstate.hh"
42 #include "arch/x86/types.hh"
43 #include "base/trace.hh"
44 #include "cpu/static_inst.hh"
45 #include "cpu/thread_context.hh"
46 #include "debug/X86.hh"
47 
48 namespace gem5
49 {
50 
51 namespace X86ISA
52 {
53 
59 struct GpRegIndex
60 {
62  explicit GpRegIndex(RegIndex idx) : index(idx) {}
63 };
64 
65 struct FpRegIndex
66 {
68  explicit FpRegIndex(RegIndex idx) : index(idx) {}
69 };
70 
72 {
74  explicit CtrlRegIndex(RegIndex idx) : index(idx) {}
75 };
76 
77 struct CrRegIndex
78 {
80  explicit CrRegIndex(RegIndex idx) : index(idx) {}
81 };
82 
84 {
86  explicit DbgRegIndex(RegIndex idx) : index(idx) {}
87 };
88 
90 {
92  explicit SegRegIndex(RegIndex idx) : index(idx) {}
93 };
94 
99 class X86StaticInst : public StaticInst
100 {
101  public:
102  static void printMnemonic(std::ostream &os, const char *mnemonic);
103  static void printMnemonic(std::ostream &os, const char *instMnemonic,
104  const char *mnemonic);
105  static void printMem(std::ostream &os, uint8_t segment,
106  uint8_t scale, RegIndex index, RegIndex base,
107  uint64_t disp, uint8_t addressSize, bool rip);
108 
109  static void printSegment(std::ostream &os, int segment);
110 
111  static void printReg(std::ostream &os, RegId reg, int size);
112 
113  protected:
115 
116  public:
118 
119  protected:
120  // Constructor.
121  X86StaticInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
122  StaticInst(mnem, __opClass), machInst(_machInst)
123  {}
124 
125  std::string generateDisassembly(
126  Addr pc, const loader::SymbolTable *symtab) const override;
127 
128  static void divideStep(uint64_t divident, uint64_t divisor,
129  uint64_t &quotient, uint64_t &remainder);
130 
131  static inline uint64_t
132  merge(uint64_t into, RegIndex index, uint64_t val, int size)
133  {
134  X86IntReg reg = into;
135  if (index & IntFoldBit) {
136  reg.H = val;
137  return reg;
138  }
139  switch(size) {
140  case 1:
141  reg.L = val;
142  break;
143  case 2:
144  reg.X = val;
145  break;
146  case 4:
147  //XXX Check if this should be zeroed or sign extended
148  reg = 0;
149  reg.E = val;
150  break;
151  case 8:
152  reg.R = val;
153  break;
154  default:
155  panic("Tried to merge with unrecognized size %d.\n", size);
156  }
157  return reg;
158  }
159 
160  static inline uint64_t
161  pick(uint64_t from, RegIndex index, int size)
162  {
163  X86IntReg reg = from;
164  DPRINTF(X86, "Picking with size %d\n", size);
165  if (index & IntFoldBit)
166  return reg.H;
167  switch(size) {
168  case 1:
169  return reg.L;
170  case 2:
171  return reg.X;
172  case 4:
173  return reg.E;
174  case 8:
175  return reg.R;
176  default:
177  panic("Tried to pick with unrecognized size %d.\n", size);
178  }
179  }
180 
181  static inline int64_t
182  signedPick(uint64_t from, RegIndex index, int size)
183  {
184  X86IntReg reg = from;
185  DPRINTF(X86, "Picking with size %d\n", size);
186  if (index & IntFoldBit)
187  return reg.SH;
188  switch(size) {
189  case 1:
190  return reg.SL;
191  case 2:
192  return reg.SX;
193  case 4:
194  return reg.SE;
195  case 8:
196  return reg.SR;
197  default:
198  panic("Tried to pick with unrecognized size %d.\n", size);
199  }
200  }
201 
202  void
203  advancePC(PCStateBase &pcState) const override
204  {
205  pcState.as<PCState>().advance();
206  }
207 
208  void
209  advancePC(ThreadContext *tc) const override
210  {
211  PCState pc = tc->pcState().as<PCState>();
212  pc.advance();
213  tc->pcState(pc);
214  }
215 
216  std::unique_ptr<PCStateBase>
217  buildRetPC(const PCStateBase &cur_pc,
218  const PCStateBase &call_pc) const override
219  {
220  PCStateBase *ret_pc_ptr = call_pc.clone();
221  ret_pc_ptr->as<PCState>().uEnd();
222  return std::unique_ptr<PCStateBase>{ret_pc_ptr};
223  }
224 };
225 
226 } // namespace X86ISA
227 } // namespace gem5
228 
229 #endif //__ARCH_X86_INSTS_STATICINST_HH__
gem5::X86ISA::FpRegIndex
Definition: static_inst.hh:65
gem5::X86ISA::pc
Bitfield< 19 > pc
Definition: misc.hh:811
gem5::X86ISA::CtrlRegIndex::index
RegIndex index
Definition: static_inst.hh:73
pcstate.hh
gem5::X86ISA::SegRegIndex::SegRegIndex
SegRegIndex(RegIndex idx)
Definition: static_inst.hh:92
gem5::X86ISA::GpRegIndex
Classes for register indices passed to instruction constructors.
Definition: static_inst.hh:59
gem5::X86ISA::X86StaticInst::merge
static uint64_t merge(uint64_t into, RegIndex index, uint64_t val, int size)
Definition: static_inst.hh:132
gem5::X86ISA::X86StaticInst::divideStep
static void divideStep(uint64_t divident, uint64_t divisor, uint64_t &quotient, uint64_t &remainder)
Definition: static_inst.cc:112
gem5::X86ISA::X86StaticInst::buildRetPC
std::unique_ptr< PCStateBase > buildRetPC(const PCStateBase &cur_pc, const PCStateBase &call_pc) const override
Definition: static_inst.hh:217
gem5::X86ISA::CrRegIndex
Definition: static_inst.hh:77
gem5::X86ISA::scale
scale
Definition: types.hh:97
gem5::PCStateBase::as
Target & as()
Definition: pcstate.hh:72
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::X86ISA::X86StaticInst::printMem
static void printMem(std::ostream &os, uint8_t segment, uint8_t scale, RegIndex index, RegIndex base, uint64_t disp, uint8_t addressSize, bool rip)
Definition: static_inst.cc:257
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::X86ISA::X86StaticInst::advancePC
void advancePC(ThreadContext *tc) const override
Definition: static_inst.hh:209
gem5::X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
sc_dt::remainder
return remainder
Definition: scfx_rep.cc:2201
gem5::X86ISA::SegRegIndex::index
RegIndex index
Definition: static_inst.hh:91
gem5::X86ISA::FpRegIndex::index
RegIndex index
Definition: static_inst.hh:67
gem5::StaticInst
Base, ISA-independent static instruction class.
Definition: static_inst.hh:87
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::MipsISA::ExtMachInst
uint64_t ExtMachInst
Definition: types.hh:43
gem5::X86ISA::FpRegIndex::FpRegIndex
FpRegIndex(RegIndex idx)
Definition: static_inst.hh:68
gem5::X86ISA::X86StaticInst::pick
static uint64_t pick(uint64_t from, RegIndex index, int size)
Definition: static_inst.hh:161
static_inst.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::X86StaticInst::printReg
static void printReg(std::ostream &os, RegId reg, int size)
Definition: static_inst.cc:142
gem5::X86ISA::CtrlRegIndex::CtrlRegIndex
CtrlRegIndex(RegIndex idx)
Definition: static_inst.hh:74
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::X86ISA::GpRegIndex::index
RegIndex index
Definition: static_inst.hh:61
gem5::X86ISA::X86StaticInst
Base class for all X86 static instructions.
Definition: static_inst.hh:99
gem5::X86ISA::X86StaticInst::X86StaticInst
X86StaticInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: static_inst.hh:121
gem5::X86ISA::X86StaticInst::printSegment
static void printSegment(std::ostream &os, int segment)
Definition: static_inst.cc:63
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:809
gem5::X86ISA::index
Bitfield< 5, 3 > index
Definition: types.hh:98
gem5::X86ISA::X86StaticInst::machInst
ExtMachInst machInst
Definition: static_inst.hh:117
gem5::X86ISA::X86StaticInst::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: static_inst.cc:293
gem5::X86ISA::PCState
Definition: pcstate.hh:50
gem5::X86ISA::GpRegIndex::GpRegIndex
GpRegIndex(RegIndex idx)
Definition: static_inst.hh:62
gem5::X86ISA::CrRegIndex::index
RegIndex index
Definition: static_inst.hh:79
gem5::X86ISA::X86StaticInst::advancePC
void advancePC(PCStateBase &pcState) const override
Definition: static_inst.hh:203
trace.hh
gem5::X86ISA::CtrlRegIndex
Definition: static_inst.hh:71
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:280
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::X86ISA::SegRegIndex
Definition: static_inst.hh:89
gem5::X86ISA::DbgRegIndex::index
RegIndex index
Definition: static_inst.hh:85
types.hh
thread_context.hh
gem5::X86ISA::CrRegIndex::CrRegIndex
CrRegIndex(RegIndex idx)
Definition: static_inst.hh:80
gem5::X86ISA::DbgRegIndex::DbgRegIndex
DbgRegIndex(RegIndex idx)
Definition: static_inst.hh:86
gem5::X86ISA::X86StaticInst::signedPick
static int64_t signedPick(uint64_t from, RegIndex index, int size)
Definition: static_inst.hh:182
gem5::PCStateBase::clone
virtual PCStateBase * clone() const =0
gem5::X86ISA::DbgRegIndex
Definition: static_inst.hh:83
gem5::X86ISA::IntFoldBit
static const IntRegIndex IntFoldBit
Definition: int.hh:172
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:113
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::X86ISA::X86StaticInst::printMnemonic
static void printMnemonic(std::ostream &os, const char *mnemonic)
Definition: static_inst.cc:51

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