gem5  v22.1.0.0
isa.hh
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28 
29 #ifndef __ARCH_MIPS_ISA_HH__
30 #define __ARCH_MIPS_ISA_HH__
31 
32 #include <queue>
33 #include <string>
34 #include <vector>
35 
36 #include "arch/generic/isa.hh"
37 #include "arch/mips/pcstate.hh"
38 #include "arch/mips/regs/misc.hh"
39 #include "arch/mips/types.hh"
40 #include "base/types.hh"
41 #include "cpu/reg_class.hh"
42 #include "sim/eventq.hh"
43 #include "sim/sim_object.hh"
44 
45 namespace gem5
46 {
47 
48 class BaseCPU;
49 class Checkpoint;
50 struct MipsISAParams;
51 class ThreadContext;
52 
53 namespace MipsISA
54 {
55  class ISA : public BaseISA
56  {
57  public:
58  // The MIPS name for this file is CP0 or Coprocessor 0
59  typedef ISA CP0;
60 
61  using Params = MipsISAParams;
62 
63  protected:
64  // Number of threads and vpes an individual ISA state can handle
65  uint8_t numThreads;
66  uint8_t numVpes;
67 
68  enum BankType
69  {
73  };
74 
78 
79  public:
80  void clear() override;
81 
82  PCStateBase *
83  newPCState(Addr new_inst_addr=0) const override
84  {
85  return new PCState(new_inst_addr);
86  }
87 
88  public:
89  void configCP();
90 
91  unsigned getVPENum(ThreadID tid) const;
92 
94  //
95  // READ/WRITE CP0 STATE
96  //
97  //
99  //@TODO: MIPS MT's register view automatically connects
100  // Status to TCStatus depending on current thread
103  RegVal
104  readMiscRegNoEffect(RegIndex idx) const override
105  {
106  return readMiscRegNoEffect(idx, 0);
107  }
108 
110  RegVal
111  readMiscReg(RegIndex idx) override
112  {
113  return readMiscReg(idx, 0);
114  }
115 
116  RegVal filterCP0Write(RegIndex idx, int reg_sel, RegVal val);
117  void setRegMask(RegIndex idx, RegVal val, ThreadID tid = 0);
118 
120  void
122  {
123  setMiscRegNoEffect(idx, val, 0);
124  }
125 
126  void setMiscReg(RegIndex idx, RegVal val, ThreadID tid);
127  void
128  setMiscReg(RegIndex idx, RegVal val) override
129  {
130  setMiscReg(idx, val, 0);
131  }
132 
134  //
135  // DECLARE INTERFACE THAT WILL ALLOW A MiscRegFile (Cop0)
136  // TO SCHEDULE EVENTS
137  //
139 
140  // Flag that is set when CP0 state has been written to.
142 
143  // Enumerated List of CP0 Event Types
145  {
146  UpdateCP0
147  };
148 
151 
152  // Schedule a CP0 Update Event
153  void scheduleCP0Update(BaseCPU *cpu, Cycles delay = Cycles(0));
154 
155  // If any changes have been made, then check the state for changes
156  // and if necessary alert the CPU
157  void updateCPU(BaseCPU *cpu);
158 
159  static std::string miscRegNames[misc_reg::NumRegs];
160 
161  public:
162  ISA(const Params &p);
163 
164  bool
165  inUserMode() const override
166  {
169 
170  if (// EXL, ERL or CU0 set, CP0 accessible
171  (Stat & 0x10000006) == 0 &&
172  // DM bit set, CP0 accessible
173  (Dbg & 0x40000000) == 0 &&
174  // KSU = 0, kernel mode is base mode
175  (Stat & 0x00000018) != 0) {
176  // Unable to use Status_CU0, etc directly,
177  // using bitfields & masks.
178  return true;
179  } else {
180  return false;
181  }
182  }
183 
184  void copyRegsFrom(ThreadContext *src) override;
185  };
186 } // namespace MipsISA
187 } // namespace gem5
188 
189 #endif
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:79
void processCP0Event(BaseCPU *cpu, CP0EventType)
Process a CP0 event.
Definition: isa.cc:600
ISA(const Params &p)
Definition: isa.cc:111
RegVal readMiscReg(RegIndex idx) override
Definition: isa.hh:111
RegVal readMiscRegNoEffect(RegIndex idx) const override
Definition: isa.hh:104
void setMiscReg(RegIndex idx, RegVal val, ThreadID tid)
Definition: isa.cc:514
bool inUserMode() const override
Definition: isa.hh:165
void setMiscReg(RegIndex idx, RegVal val) override
Definition: isa.hh:128
std::vector< std::vector< RegVal > > miscRegFile
Definition: isa.hh:75
void updateCPU(BaseCPU *cpu)
Definition: isa.cc:571
void updateCP0ReadView(RegIndex idx, ThreadID tid)
Definition: isa.hh:101
RegVal readMiscRegNoEffect(RegIndex idx, ThreadID tid) const
Definition: isa.cc:461
bool cp0Updated
Definition: isa.hh:141
RegVal readMiscReg(RegIndex idx, ThreadID tid)
Definition: isa.cc:474
void setMiscRegNoEffect(RegIndex idx, RegVal val) override
Definition: isa.hh:121
unsigned getVPENum(ThreadID tid) const
Definition: isa.cc:454
void setRegMask(RegIndex idx, RegVal val, ThreadID tid=0)
Definition: isa.cc:499
void setMiscRegNoEffect(RegIndex idx, RegVal val, ThreadID tid)
Definition: isa.cc:486
PCStateBase * newPCState(Addr new_inst_addr=0) const override
Definition: isa.hh:83
std::vector< BankType > bankType
Definition: isa.hh:77
void scheduleCP0Update(BaseCPU *cpu, Cycles delay=Cycles(0))
Definition: isa.cc:557
RegVal filterCP0Write(RegIndex idx, int reg_sel, RegVal val)
This method doesn't need to adjust the Control Register Offset since it has already been done in the ...
Definition: isa.cc:537
std::vector< std::vector< RegVal > > miscRegFile_WriteMask
Definition: isa.hh:76
void copyRegsFrom(ThreadContext *src) override
Definition: isa.cc:185
static std::string miscRegNames[misc_reg::NumRegs]
Definition: isa.hh:159
void configCP()
Definition: isa.cc:205
uint8_t numThreads
Definition: isa.hh:65
uint8_t numVpes
Definition: isa.hh:66
@ perVirtProcessor
Definition: isa.hh:72
@ perThreadContext
Definition: isa.hh:71
void clear() override
Definition: isa.cc:173
MipsISAParams Params
Definition: isa.hh:61
ThreadContext is the external interface to all thread state for anything outside of the CPU.
STL vector class.
Definition: stl.hh:37
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
Bitfield< 0 > p
Bitfield< 63 > val
Definition: misc.hh:776
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:235
uint16_t RegIndex
Definition: types.hh:176
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
uint64_t RegVal
Definition: types.hh:173

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