gem5  v22.0.0.1
isa.hh
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28 
29 #ifndef __ARCH_MIPS_ISA_HH__
30 #define __ARCH_MIPS_ISA_HH__
31 
32 #include <queue>
33 #include <string>
34 #include <vector>
35 
36 #include "arch/generic/isa.hh"
37 #include "arch/mips/pcstate.hh"
38 #include "arch/mips/regs/misc.hh"
39 #include "arch/mips/types.hh"
40 #include "base/types.hh"
41 #include "cpu/reg_class.hh"
42 #include "sim/eventq.hh"
43 #include "sim/sim_object.hh"
44 
45 namespace gem5
46 {
47 
48 class BaseCPU;
49 class Checkpoint;
50 struct MipsISAParams;
51 class ThreadContext;
52 
53 namespace MipsISA
54 {
55  class ISA : public BaseISA
56  {
57  public:
58  // The MIPS name for this file is CP0 or Coprocessor 0
59  typedef ISA CP0;
60 
61  using Params = MipsISAParams;
62 
63  protected:
64  // Number of threads and vpes an individual ISA state can handle
65  uint8_t numThreads;
66  uint8_t numVpes;
67 
68  enum BankType
69  {
73  };
74 
78 
79  public:
80  void clear();
81 
82  PCStateBase *
83  newPCState(Addr new_inst_addr=0) const override
84  {
85  return new PCState(new_inst_addr);
86  }
87 
88  public:
89  void configCP();
90 
91  unsigned getVPENum(ThreadID tid) const;
92 
94  //
95  // READ/WRITE CP0 STATE
96  //
97  //
99  //@TODO: MIPS MT's register view automatically connects
100  // Status to TCStatus depending on current thread
101  void updateCP0ReadView(int misc_reg, ThreadID tid) { }
102  RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const;
103 
104  //template <class TC>
105  RegVal readMiscReg(int misc_reg, ThreadID tid = 0);
106 
107  RegVal filterCP0Write(int misc_reg, int reg_sel, RegVal val);
108  void setRegMask(int misc_reg, RegVal val, ThreadID tid = 0);
109  void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid=0);
110 
111  //template <class TC>
112  void setMiscReg(int misc_reg, RegVal val, ThreadID tid=0);
113 
115  //
116  // DECLARE INTERFACE THAT WILL ALLOW A MiscRegFile (Cop0)
117  // TO SCHEDULE EVENTS
118  //
120 
121  // Flag that is set when CP0 state has been written to.
123 
124  // Enumerated List of CP0 Event Types
126  {
128  };
129 
131  void processCP0Event(BaseCPU *cpu, CP0EventType);
132 
133  // Schedule a CP0 Update Event
134  void scheduleCP0Update(BaseCPU *cpu, Cycles delay = Cycles(0));
135 
136  // If any changes have been made, then check the state for changes
137  // and if necessary alert the CPU
138  void updateCPU(BaseCPU *cpu);
139 
140  static std::string miscRegNames[MISCREG_NUMREGS];
141 
142  public:
143  ISA(const Params &p);
144 
145  RegId flattenRegId(const RegId& regId) const { return regId; }
146 
147  int flattenIntIndex(int reg) const { return reg; }
148  int flattenFloatIndex(int reg) const { return reg; }
149  int flattenVecIndex(int reg) const { return reg; }
150  int flattenVecElemIndex(int reg) const { return reg; }
151  int flattenVecPredIndex(int reg) const { return reg; }
152  // dummy
153  int flattenCCIndex(int reg) const { return reg; }
154  int flattenMiscIndex(int reg) const { return reg; }
155 
156  bool
157  inUserMode() const override
158  {
161 
162  if (// EXL, ERL or CU0 set, CP0 accessible
163  (Stat & 0x10000006) == 0 &&
164  // DM bit set, CP0 accessible
165  (Dbg & 0x40000000) == 0 &&
166  // KSU = 0, kernel mode is base mode
167  (Stat & 0x00000018) != 0) {
168  // Unable to use Status_CU0, etc directly,
169  // using bitfields & masks.
170  return true;
171  } else {
172  return false;
173  }
174  }
175 
176  void copyRegsFrom(ThreadContext *src) override;
177  };
178 } // namespace MipsISA
179 } // namespace gem5
180 
181 #endif
gem5::MipsISA::ISA::bankType
std::vector< BankType > bankType
Definition: isa.hh:77
misc.hh
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::MipsISA::ISA::flattenVecPredIndex
int flattenVecPredIndex(int reg) const
Definition: isa.hh:151
gem5::MipsISA::ISA::processCP0Event
void processCP0Event(BaseCPU *cpu, CP0EventType)
Process a CP0 event.
Definition: isa.cc:591
gem5::MipsISA::ISA::UpdateCP0
@ UpdateCP0
Definition: isa.hh:127
gem5::MipsISA::ISA::CP0
ISA CP0
Definition: isa.hh:59
gem5::MipsISA::MISCREG_STATUS
@ MISCREG_STATUS
Definition: misc.hh:96
gem5::MipsISA::ISA::scheduleCP0Update
void scheduleCP0Update(BaseCPU *cpu, Cycles delay=Cycles(0))
Definition: isa.cc:548
gem5::MipsISA::ISA::numVpes
uint8_t numVpes
Definition: isa.hh:66
types.hh
gem5::MipsISA::ISA::inUserMode
bool inUserMode() const override
Definition: isa.hh:157
gem5::MipsISA::ISA::flattenIntIndex
int flattenIntIndex(int reg) const
Definition: isa.hh:147
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::MipsISA::ISA::numThreads
uint8_t numThreads
Definition: isa.hh:65
std::vector
STL vector class.
Definition: stl.hh:37
gem5::MipsISA::ISA::ISA
ISA(const Params &p)
Definition: isa.cc:100
gem5::MipsISA::MISCREG_NUMREGS
@ MISCREG_NUMREGS
Definition: misc.hh:194
gem5::MipsISA::ISA::miscRegFile
std::vector< std::vector< RegVal > > miscRegFile
Definition: isa.hh:75
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::MipsISA::ISA::flattenVecElemIndex
int flattenVecElemIndex(int reg) const
Definition: isa.hh:150
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::MipsISA::ISA::setRegMask
void setRegMask(int misc_reg, RegVal val, ThreadID tid=0)
Definition: isa.cc:490
sim_object.hh
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::MipsISA::ISA::filterCP0Write
RegVal filterCP0Write(int misc_reg, int reg_sel, RegVal val)
This method doesn't need to adjust the Control Register Offset since it has already been done in the ...
Definition: isa.cc:528
gem5::MipsISA::ISA::perVirtProcessor
@ perVirtProcessor
Definition: isa.hh:72
gem5::MipsISA::ISA::updateCP0ReadView
void updateCP0ReadView(int misc_reg, ThreadID tid)
Definition: isa.hh:101
gem5::MipsISA::ISA::flattenRegId
RegId flattenRegId(const RegId &regId) const
Definition: isa.hh:145
gem5::MipsISA::ISA::setMiscReg
void setMiscReg(int misc_reg, RegVal val, ThreadID tid=0)
Definition: isa.cc:505
gem5::MipsISA::ISA::copyRegsFrom
void copyRegsFrom(ThreadContext *src) override
Definition: isa.cc:174
gem5::MipsISA::ISA::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid=0) const
Definition: isa.cc:450
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::MipsISA::ISA::newPCState
PCStateBase * newPCState(Addr new_inst_addr=0) const override
Definition: isa.hh:83
gem5::MipsISA::ISA::miscRegNames
static std::string miscRegNames[MISCREG_NUMREGS]
Definition: isa.hh:140
gem5::MipsISA::ISA::CP0EventType
CP0EventType
Definition: isa.hh:125
gem5::MipsISA::ISA::configCP
void configCP()
Definition: isa.cc:194
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::MipsISA::ISA::flattenFloatIndex
int flattenFloatIndex(int reg) const
Definition: isa.hh:148
isa.hh
gem5::MipsISA::ISA::readMiscReg
RegVal readMiscReg(int misc_reg, ThreadID tid=0)
Definition: isa.cc:464
gem5::MipsISA::ISA::flattenMiscIndex
int flattenMiscIndex(int reg) const
Definition: isa.hh:154
types.hh
gem5::MipsISA::ISA::getVPENum
unsigned getVPENum(ThreadID tid) const
Definition: isa.cc:443
gem5::MipsISA::ISA::perThreadContext
@ perThreadContext
Definition: isa.hh:71
reg_class.hh
gem5::MipsISA::ISA::flattenVecIndex
int flattenVecIndex(int reg) const
Definition: isa.hh:149
gem5::MipsISA::ISA::perProcessor
@ perProcessor
Definition: isa.hh:70
gem5::MipsISA::ISA::updateCPU
void updateCPU(BaseCPU *cpu)
Definition: isa.cc:562
gem5::MipsISA::MISCREG_DEBUG
@ MISCREG_DEBUG
Definition: misc.hh:144
gem5::MipsISA::ISA
Definition: isa.hh:55
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::BaseISA
Definition: isa.hh:57
gem5::MipsISA::ISA::flattenCCIndex
int flattenCCIndex(int reg) const
Definition: isa.hh:153
gem5::MipsISA::ISA::cp0Updated
bool cp0Updated
Definition: isa.hh:122
gem5::MipsISA::ISA::clear
void clear()
Definition: isa.cc:162
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::MipsISA::ISA::Params
MipsISAParams Params
Definition: isa.hh:61
pcstate.hh
gem5::MipsISA::ISA::BankType
BankType
Definition: isa.hh:68
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:235
gem5::MipsISA::ISA::miscRegFile_WriteMask
std::vector< std::vector< RegVal > > miscRegFile_WriteMask
Definition: isa.hh:76
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126
gem5::MipsISA::ISA::setMiscRegNoEffect
void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid=0)
Definition: isa.cc:477
eventq.hh

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