gem5  v21.1.0.2
isa.hh
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28 
29 #ifndef __ARCH_MIPS_ISA_HH__
30 #define __ARCH_MIPS_ISA_HH__
31 
32 #include <queue>
33 #include <string>
34 #include <vector>
35 
36 #include "arch/generic/isa.hh"
37 #include "arch/mips/regs/misc.hh"
38 #include "arch/mips/types.hh"
39 #include "base/types.hh"
40 #include "cpu/reg_class.hh"
41 #include "sim/eventq.hh"
42 #include "sim/sim_object.hh"
43 
44 namespace gem5
45 {
46 
47 class BaseCPU;
48 class Checkpoint;
49 struct MipsISAParams;
50 class ThreadContext;
51 
52 namespace MipsISA
53 {
54  class ISA : public BaseISA
55  {
56  public:
57  // The MIPS name for this file is CP0 or Coprocessor 0
58  typedef ISA CP0;
59 
60  using Params = MipsISAParams;
61 
62  protected:
63  // Number of threads and vpes an individual ISA state can handle
64  uint8_t numThreads;
65  uint8_t numVpes;
66 
67  enum BankType
68  {
72  };
73 
77 
78  public:
79  void clear();
80 
81  public:
82  void configCP();
83 
84  unsigned getVPENum(ThreadID tid) const;
85 
87  //
88  // READ/WRITE CP0 STATE
89  //
90  //
92  //@TODO: MIPS MT's register view automatically connects
93  // Status to TCStatus depending on current thread
94  void updateCP0ReadView(int misc_reg, ThreadID tid) { }
95  RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const;
96 
97  //template <class TC>
98  RegVal readMiscReg(int misc_reg, ThreadID tid = 0);
99 
100  RegVal filterCP0Write(int misc_reg, int reg_sel, RegVal val);
101  void setRegMask(int misc_reg, RegVal val, ThreadID tid = 0);
102  void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid=0);
103 
104  //template <class TC>
105  void setMiscReg(int misc_reg, RegVal val, ThreadID tid=0);
106 
108  //
109  // DECLARE INTERFACE THAT WILL ALLOW A MiscRegFile (Cop0)
110  // TO SCHEDULE EVENTS
111  //
113 
114  // Flag that is set when CP0 state has been written to.
116 
117  // Enumerated List of CP0 Event Types
119  {
121  };
122 
125 
126  // Schedule a CP0 Update Event
127  void scheduleCP0Update(BaseCPU *cpu, Cycles delay = Cycles(0));
128 
129  // If any changes have been made, then check the state for changes
130  // and if necessary alert the CPU
131  void updateCPU(BaseCPU *cpu);
132 
133  static std::string miscRegNames[MISCREG_NUMREGS];
134 
135  public:
136  ISA(const Params &p);
137 
138  RegId flattenRegId(const RegId& regId) const { return regId; }
139 
140  int flattenIntIndex(int reg) const { return reg; }
141  int flattenFloatIndex(int reg) const { return reg; }
142  int flattenVecIndex(int reg) const { return reg; }
143  int flattenVecElemIndex(int reg) const { return reg; }
144  int flattenVecPredIndex(int reg) const { return reg; }
145  // dummy
146  int flattenCCIndex(int reg) const { return reg; }
147  int flattenMiscIndex(int reg) const { return reg; }
148 
149  bool
150  inUserMode() const override
151  {
154 
155  if (// EXL, ERL or CU0 set, CP0 accessible
156  (Stat & 0x10000006) == 0 &&
157  // DM bit set, CP0 accessible
158  (Dbg & 0x40000000) == 0 &&
159  // KSU = 0, kernel mode is base mode
160  (Stat & 0x00000018) != 0) {
161  // Unable to use Status_CU0, etc directly,
162  // using bitfields & masks.
163  return true;
164  } else {
165  return false;
166  }
167  }
168 
169  void copyRegsFrom(ThreadContext *src) override;
170  };
171 } // namespace MipsISA
172 } // namespace gem5
173 
174 #endif
gem5::MipsISA::ISA::bankType
std::vector< BankType > bankType
Definition: isa.hh:76
misc.hh
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::MipsISA::ISA::flattenVecPredIndex
int flattenVecPredIndex(int reg) const
Definition: isa.hh:144
gem5::MipsISA::ISA::processCP0Event
void processCP0Event(BaseCPU *cpu, CP0EventType)
Process a CP0 event.
Definition: isa.cc:588
gem5::MipsISA::ISA::UpdateCP0
@ UpdateCP0
Definition: isa.hh:120
gem5::MipsISA::ISA::CP0
ISA CP0
Definition: isa.hh:58
gem5::MipsISA::MISCREG_STATUS
@ MISCREG_STATUS
Definition: misc.hh:96
gem5::MipsISA::ISA::scheduleCP0Update
void scheduleCP0Update(BaseCPU *cpu, Cycles delay=Cycles(0))
Definition: isa.cc:545
gem5::MipsISA::ISA::numVpes
uint8_t numVpes
Definition: isa.hh:65
types.hh
gem5::MipsISA::ISA::inUserMode
bool inUserMode() const override
Definition: isa.hh:150
gem5::MipsISA::ISA::flattenIntIndex
int flattenIntIndex(int reg) const
Definition: isa.hh:140
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::MipsISA::ISA::numThreads
uint8_t numThreads
Definition: isa.hh:64
std::vector
STL vector class.
Definition: stl.hh:37
gem5::MipsISA::ISA::ISA
ISA(const Params &p)
Definition: isa.cc:97
gem5::MipsISA::MISCREG_NUMREGS
@ MISCREG_NUMREGS
Definition: misc.hh:194
gem5::MipsISA::ISA::miscRegFile
std::vector< std::vector< RegVal > > miscRegFile
Definition: isa.hh:74
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::MipsISA::ISA::flattenVecElemIndex
int flattenVecElemIndex(int reg) const
Definition: isa.hh:143
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::MipsISA::ISA::setRegMask
void setRegMask(int misc_reg, RegVal val, ThreadID tid=0)
Definition: isa.cc:487
sim_object.hh
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::MipsISA::ISA::filterCP0Write
RegVal filterCP0Write(int misc_reg, int reg_sel, RegVal val)
This method doesn't need to adjust the Control Register Offset since it has already been done in the ...
Definition: isa.cc:525
gem5::MipsISA::ISA::perVirtProcessor
@ perVirtProcessor
Definition: isa.hh:71
gem5::MipsISA::ISA::updateCP0ReadView
void updateCP0ReadView(int misc_reg, ThreadID tid)
Definition: isa.hh:94
gem5::MipsISA::ISA::flattenRegId
RegId flattenRegId(const RegId &regId) const
Definition: isa.hh:138
gem5::MipsISA::ISA::setMiscReg
void setMiscReg(int misc_reg, RegVal val, ThreadID tid=0)
Definition: isa.cc:502
gem5::BaseCPU
Definition: base.hh:107
gem5::MipsISA::ISA::copyRegsFrom
void copyRegsFrom(ThreadContext *src) override
Definition: isa.cc:171
gem5::MipsISA::ISA::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid=0) const
Definition: isa.cc:447
gem5::MipsISA::ISA::miscRegNames
static std::string miscRegNames[MISCREG_NUMREGS]
Definition: isa.hh:133
gem5::MipsISA::ISA::CP0EventType
CP0EventType
Definition: isa.hh:118
gem5::MipsISA::ISA::configCP
void configCP()
Definition: isa.cc:191
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::MipsISA::ISA::flattenFloatIndex
int flattenFloatIndex(int reg) const
Definition: isa.hh:141
isa.hh
gem5::MipsISA::ISA::readMiscReg
RegVal readMiscReg(int misc_reg, ThreadID tid=0)
Definition: isa.cc:461
gem5::MipsISA::ISA::flattenMiscIndex
int flattenMiscIndex(int reg) const
Definition: isa.hh:147
types.hh
gem5::MipsISA::ISA::getVPENum
unsigned getVPENum(ThreadID tid) const
Definition: isa.cc:440
gem5::MipsISA::ISA::perThreadContext
@ perThreadContext
Definition: isa.hh:70
reg_class.hh
gem5::MipsISA::ISA::flattenVecIndex
int flattenVecIndex(int reg) const
Definition: isa.hh:142
gem5::MipsISA::ISA::perProcessor
@ perProcessor
Definition: isa.hh:69
gem5::MipsISA::ISA::updateCPU
void updateCPU(BaseCPU *cpu)
Definition: isa.cc:559
gem5::MipsISA::MISCREG_DEBUG
@ MISCREG_DEBUG
Definition: misc.hh:144
gem5::MipsISA::ISA
Definition: isa.hh:54
gem5::BaseISA
Definition: isa.hh:54
gem5::MipsISA::ISA::flattenCCIndex
int flattenCCIndex(int reg) const
Definition: isa.hh:146
gem5::MipsISA::ISA::cp0Updated
bool cp0Updated
Definition: isa.hh:115
gem5::MipsISA::ISA::clear
void clear()
Definition: isa.cc:159
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::MipsISA::ISA::Params
MipsISAParams Params
Definition: isa.hh:60
gem5::MipsISA::ISA::BankType
BankType
Definition: isa.hh:67
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::MipsISA::ISA::miscRegFile_WriteMask
std::vector< std::vector< RegVal > > miscRegFile_WriteMask
Definition: isa.hh:75
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88
gem5::MipsISA::ISA::setMiscRegNoEffect
void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid=0)
Definition: isa.cc:474
eventq.hh

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