gem5 v24.0.0.0
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#include <isa.hh>
Public Types | |
enum | CP0EventType { UpdateCP0 } |
typedef ISA | CP0 |
using | Params = MipsISAParams |
Public Types inherited from gem5::BaseISA | |
typedef std::vector< const RegClass * > | RegClasses |
Public Types inherited from gem5::SimObject | |
typedef SimObjectParams | Params |
Public Member Functions | |
void | clear () override |
PCStateBase * | newPCState (Addr new_inst_addr=0) const override |
void | configCP () |
unsigned | getVPENum (ThreadID tid) const |
void | updateCP0ReadView (RegIndex idx, ThreadID tid) |
RegVal | readMiscRegNoEffect (RegIndex idx, ThreadID tid) const |
RegVal | readMiscRegNoEffect (RegIndex idx) const override |
RegVal | readMiscReg (RegIndex idx, ThreadID tid) |
RegVal | readMiscReg (RegIndex idx) override |
RegVal | filterCP0Write (RegIndex idx, int reg_sel, RegVal val) |
This method doesn't need to adjust the Control Register Offset since it has already been done in the calling method (setRegWithEffect) | |
void | setRegMask (RegIndex idx, RegVal val, ThreadID tid=0) |
void | setMiscRegNoEffect (RegIndex idx, RegVal val, ThreadID tid) |
void | setMiscRegNoEffect (RegIndex idx, RegVal val) override |
void | setMiscReg (RegIndex idx, RegVal val, ThreadID tid) |
void | setMiscReg (RegIndex idx, RegVal val) override |
void | processCP0Event (BaseCPU *cpu, CP0EventType) |
Process a CP0 event. | |
void | scheduleCP0Update (BaseCPU *cpu, Cycles delay=Cycles(0)) |
void | updateCPU (BaseCPU *cpu) |
ISA (const Params &p) | |
bool | inUserMode () const override |
void | copyRegsFrom (ThreadContext *src) override |
Public Member Functions inherited from gem5::BaseISA | |
virtual void | takeOverFrom (ThreadContext *new_tc, ThreadContext *old_tc) |
virtual void | setThreadContext (ThreadContext *_tc) |
virtual uint64_t | getExecutingAsid () const |
virtual void | resetThread () |
const RegClasses & | regClasses () const |
const std::string | getIsaName () const |
virtual void | handleLockedRead (const RequestPtr &req) |
virtual void | handleLockedRead (ExecContext *xc, const RequestPtr &req) |
virtual bool | handleLockedWrite (const RequestPtr &req, Addr cacheBlockMask) |
virtual bool | handleLockedWrite (ExecContext *xc, const RequestPtr &req, Addr cacheBlockMask) |
virtual void | handleLockedSnoop (PacketPtr pkt, Addr cacheBlockMask) |
virtual void | handleLockedSnoop (ExecContext *xc, PacketPtr pkt, Addr cacheBlockMask) |
virtual void | handleLockedSnoopHit () |
virtual void | handleLockedSnoopHit (ExecContext *xc) |
virtual void | globalClearExclusive () |
virtual void | globalClearExclusive (ExecContext *xc) |
void | serialize (CheckpointOut &cp) const override |
Serialize an object. | |
virtual int64_t | getVectorLengthInBytes () const |
This function returns the vector length of the Vector Length Agnostic extension of the ISA. | |
Public Member Functions inherited from gem5::SimObject | |
const Params & | params () const |
SimObject (const Params &p) | |
virtual | ~SimObject () |
virtual void | init () |
init() is called after all C++ SimObjects have been created and all ports are connected. | |
virtual void | loadState (CheckpointIn &cp) |
loadState() is called on each SimObject when restoring from a checkpoint. | |
virtual void | initState () |
initState() is called on each SimObject when not restoring from a checkpoint. | |
virtual void | regProbePoints () |
Register probe points for this object. | |
virtual void | regProbeListeners () |
Register probe listeners for this object. | |
ProbeManager * | getProbeManager () |
Get the probe manager for this object. | |
virtual Port & | getPort (const std::string &if_name, PortID idx=InvalidPortID) |
Get a port with a given name and index. | |
virtual void | startup () |
startup() is the final initialization call before simulation. | |
DrainState | drain () override |
Provide a default implementation of the drain interface for objects that don't need draining. | |
virtual void | memWriteback () |
Write back dirty buffers to memory using functional writes. | |
virtual void | memInvalidate () |
Invalidate the contents of memory buffers. | |
void | serialize (CheckpointOut &cp) const override |
Serialize an object. | |
void | unserialize (CheckpointIn &cp) override |
Unserialize an object. | |
Public Member Functions inherited from gem5::EventManager | |
EventQueue * | eventQueue () const |
void | schedule (Event &event, Tick when) |
void | deschedule (Event &event) |
void | reschedule (Event &event, Tick when, bool always=false) |
void | schedule (Event *event, Tick when) |
void | deschedule (Event *event) |
void | reschedule (Event *event, Tick when, bool always=false) |
void | wakeupEventQueue (Tick when=(Tick) -1) |
This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. | |
void | setCurTick (Tick newVal) |
EventManager (EventManager &em) | |
Event manger manages events in the event queue. | |
EventManager (EventManager *em) | |
EventManager (EventQueue *eq) | |
Public Member Functions inherited from gem5::Serializable | |
Serializable () | |
virtual | ~Serializable () |
void | serializeSection (CheckpointOut &cp, const char *name) const |
Serialize an object into a new section. | |
void | serializeSection (CheckpointOut &cp, const std::string &name) const |
void | unserializeSection (CheckpointIn &cp, const char *name) |
Unserialize an a child object. | |
void | unserializeSection (CheckpointIn &cp, const std::string &name) |
Public Member Functions inherited from gem5::Drainable | |
DrainState | drainState () const |
Return the current drain state of an object. | |
virtual void | notifyFork () |
Notify a child process of a fork. | |
Public Member Functions inherited from gem5::statistics::Group | |
Group (Group *parent, const char *name=nullptr) | |
Construct a new statistics group. | |
virtual | ~Group () |
virtual void | regStats () |
Callback to set stat parameters. | |
virtual void | resetStats () |
Callback to reset stats. | |
virtual void | preDumpStats () |
Callback before stats are dumped. | |
void | addStat (statistics::Info *info) |
Register a stat with this group. | |
const std::map< std::string, Group * > & | getStatGroups () const |
Get all child groups associated with this object. | |
const std::vector< Info * > & | getStats () const |
Get all stats associated with this object. | |
void | addStatGroup (const char *name, Group *block) |
Add a stat block as a child of this block. | |
const Info * | resolveStat (std::string name) const |
Resolve a stat by its name within this group. | |
void | mergeStatGroup (Group *block) |
Merge the contents (stats & children) of a block to this block. | |
Group ()=delete | |
Group (const Group &)=delete | |
Group & | operator= (const Group &)=delete |
Public Member Functions inherited from gem5::Named | |
Named (const std::string &name_) | |
virtual | ~Named ()=default |
virtual std::string | name () const |
Public Attributes | |
bool | cp0Updated |
Static Public Attributes | |
static std::string | miscRegNames [misc_reg::NumRegs] |
Protected Types | |
enum | BankType { perProcessor , perThreadContext , perVirtProcessor } |
Protected Attributes | |
uint8_t | numThreads |
uint8_t | numVpes |
std::vector< std::vector< RegVal > > | miscRegFile |
std::vector< std::vector< RegVal > > | miscRegFile_WriteMask |
std::vector< BankType > | bankType |
Protected Attributes inherited from gem5::BaseISA | |
ThreadContext * | tc = nullptr |
RegClasses | _regClasses |
std::string | isaName |
Protected Attributes inherited from gem5::SimObject | |
const SimObjectParams & | _params |
Cached copy of the object parameters. | |
Protected Attributes inherited from gem5::EventManager | |
EventQueue * | eventq |
A pointer to this object's event queue. | |
Additional Inherited Members | |
Static Public Member Functions inherited from gem5::SimObject | |
static void | serializeAll (const std::string &cpt_dir) |
Create a checkpoint by serializing all SimObjects in the system. | |
static SimObject * | find (const char *name) |
Find the SimObject with the given name and return a pointer to it. | |
static void | setSimObjectResolver (SimObjectResolver *resolver) |
There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. | |
static SimObjectResolver * | getSimObjectResolver () |
There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. | |
Static Public Member Functions inherited from gem5::Serializable | |
static const std::string & | currentSection () |
Gets the fully-qualified name of the active section. | |
static void | generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream) |
Generate a checkpoint file so that the serialization can be routed to it. | |
Protected Member Functions inherited from gem5::BaseISA | |
BaseISA (const SimObjectParams &p, const std::string &name) | |
Protected Member Functions inherited from gem5::Drainable | |
Drainable () | |
virtual | ~Drainable () |
virtual void | drainResume () |
Resume execution after a successful drain. | |
void | signalDrainDone () const |
Signal that an object is drained. | |
typedef ISA gem5::MipsISA::ISA::CP0 |
using gem5::MipsISA::ISA::Params = MipsISAParams |
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gem5::MipsISA::ISA::ISA | ( | const Params & | p | ) |
Definition at line 113 of file isa.cc.
References gem5::BaseISA::_regClasses, bankType, gem5::ArmISA::ccRegClass, clear(), gem5::MipsISA::misc_reg::Debug, gem5::MipsISA::misc_reg::Ebase, gem5::X86ISA::floatRegClass, gem5::MipsISA::i, gem5::ArmISA::intRegClass, gem5::MipsISA::misc_reg::Lladdr, gem5::ArmISA::matRegClass, gem5::ArmISA::miscRegClass, miscRegFile, miscRegFile_WriteMask, gem5::MipsISA::misc_reg::NumRegs, numThreads, numVpes, perProcessor, perThreadContext, perVirtProcessor, gem5::MipsISA::misc_reg::SrsConf0, gem5::MipsISA::misc_reg::SrsConf1, gem5::MipsISA::misc_reg::SrsConf2, gem5::MipsISA::misc_reg::SrsConf3, gem5::MipsISA::misc_reg::SrsConf4, gem5::MipsISA::misc_reg::Status, gem5::MipsISA::misc_reg::TcBind, gem5::MipsISA::misc_reg::TcContext, gem5::MipsISA::misc_reg::TcHalt, gem5::MipsISA::misc_reg::TcRestart, gem5::MipsISA::misc_reg::TcSchedule, gem5::MipsISA::misc_reg::TcSchefback, gem5::MipsISA::misc_reg::TcStatus, gem5::ArmISA::vecElemClass, gem5::ArmISA::vecPredRegClass, gem5::ArmISA::vecRegClass, gem5::MipsISA::misc_reg::VpeConf0, gem5::MipsISA::misc_reg::VpeConf1, gem5::MipsISA::misc_reg::VpeControl, gem5::MipsISA::misc_reg::VpeOpt, gem5::MipsISA::misc_reg::VpeSchedule, gem5::MipsISA::misc_reg::VpeSchefback, and gem5::MipsISA::misc_reg::Yqmask.
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overridevirtual |
Reimplemented from gem5::BaseISA.
Definition at line 176 of file isa.cc.
References gem5::MipsISA::i, gem5::MipsISA::k, miscRegFile, miscRegFile_WriteMask, and gem5::MipsISA::misc_reg::NumRegs.
Referenced by ISA().
void gem5::MipsISA::ISA::configCP | ( | ) |
Definition at line 208 of file isa.cc.
References gem5::MipsISA::misc_reg::Badvaddr, gem5::MipsISA::misc_reg::Cause, gem5::MipsISA::misc_reg::Config, gem5::MipsISA::misc_reg::Config1, gem5::MipsISA::misc_reg::Config2, gem5::MipsISA::misc_reg::Config3, gem5::MipsISA::misc_reg::Context, gem5::MipsISA::CoreSpecific::CP0_Config1_C2, gem5::MipsISA::CoreSpecific::CP0_Config1_DA, gem5::MipsISA::CoreSpecific::CP0_Config1_DL, gem5::MipsISA::CoreSpecific::CP0_Config1_DS, gem5::MipsISA::CoreSpecific::CP0_Config1_EP, gem5::MipsISA::CoreSpecific::CP0_Config1_FP, gem5::MipsISA::CoreSpecific::CP0_Config1_IA, gem5::MipsISA::CoreSpecific::CP0_Config1_IL, gem5::MipsISA::CoreSpecific::CP0_Config1_IS, gem5::MipsISA::CoreSpecific::CP0_Config1_M, gem5::MipsISA::CoreSpecific::CP0_Config1_MD, gem5::MipsISA::CoreSpecific::CP0_Config1_MMU, gem5::MipsISA::CoreSpecific::CP0_Config1_PC, gem5::MipsISA::CoreSpecific::CP0_Config1_WR, gem5::MipsISA::CoreSpecific::CP0_Config2_M, gem5::MipsISA::CoreSpecific::CP0_Config2_SA, gem5::MipsISA::CoreSpecific::CP0_Config2_SL, gem5::MipsISA::CoreSpecific::CP0_Config2_SS, gem5::MipsISA::CoreSpecific::CP0_Config2_SU, gem5::MipsISA::CoreSpecific::CP0_Config2_TA, gem5::MipsISA::CoreSpecific::CP0_Config2_TL, gem5::MipsISA::CoreSpecific::CP0_Config2_TS, gem5::MipsISA::CoreSpecific::CP0_Config2_TU, gem5::MipsISA::CoreSpecific::CP0_Config3_DSPP, gem5::MipsISA::CoreSpecific::CP0_Config3_LPA, gem5::MipsISA::CoreSpecific::CP0_Config3_MT, gem5::MipsISA::CoreSpecific::CP0_Config3_SM, gem5::MipsISA::CoreSpecific::CP0_Config3_SP, gem5::MipsISA::CoreSpecific::CP0_Config3_TL, gem5::MipsISA::CoreSpecific::CP0_Config3_VEIC, gem5::MipsISA::CoreSpecific::CP0_Config3_VInt, gem5::MipsISA::CoreSpecific::CP0_Config_AR, gem5::MipsISA::CoreSpecific::CP0_Config_AT, gem5::MipsISA::CoreSpecific::CP0_Config_BE, gem5::MipsISA::CoreSpecific::CP0_Config_MT, gem5::MipsISA::CoreSpecific::CP0_Config_VI, gem5::MipsISA::CoreSpecific::CP0_EBase_CPUNum, gem5::MipsISA::CoreSpecific::CP0_IntCtl_IPPCI, gem5::MipsISA::CoreSpecific::CP0_IntCtl_IPTI, gem5::MipsISA::CoreSpecific::CP0_PerfCtr_M, gem5::MipsISA::CoreSpecific::CP0_PerfCtr_W, gem5::MipsISA::CoreSpecific::CP0_PRId_CompanyID, gem5::MipsISA::CoreSpecific::CP0_PRId_CompanyOptions, gem5::MipsISA::CoreSpecific::CP0_PRId_ProcessorID, gem5::MipsISA::CoreSpecific::CP0_PRId_Revision, gem5::MipsISA::CoreSpecific::CP0_SrsCtl_HSS, gem5::MipsISA::CoreSpecific::CP0_WatchHi_M, gem5::MipsISA::misc_reg::Cp0Random, DPRINTF, gem5::MipsISA::misc_reg::Ebase, gem5::MipsISA::misc_reg::Entrylo0, gem5::MipsISA::misc_reg::Entrylo1, gem5::MipsISA::misc_reg::Index, gem5::MipsISA::misc_reg::Intctl, gem5::MipsISA::misc_reg::Lladdr, gem5::MipsISA::mask, gem5::MipsISA::misc_reg::MvpConf0, numThreads, numVpes, gem5::MipsISA::misc_reg::Pagegrain, gem5::MipsISA::misc_reg::Pagemask, panic, gem5::MipsISA::misc_reg::Perfcnt0, gem5::MipsISA::misc_reg::Prid, gem5::MipsISA::procId, readMiscRegNoEffect(), gem5::replaceBits(), setMiscRegNoEffect(), setRegMask(), gem5::MipsISA::misc_reg::Srsctl, gem5::MipsISA::misc_reg::Status, gem5::ArmISA::status, gem5::MipsISA::misc_reg::TcBind, gem5::MipsISA::misc_reg::TcHalt, gem5::MipsISA::misc_reg::TcStatus, gem5::MipsISA::misc_reg::VpeConf0, and gem5::MipsISA::misc_reg::Watchhi0.
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overridevirtual |
Implements gem5::BaseISA.
Definition at line 188 of file isa.cc.
References gem5::X86ISA::floatRegClass, gem5::ThreadContext::getReg(), gem5::MipsISA::i, gem5::ArmISA::intRegClass, gem5::MipsISA::misc_reg::NumRegs, gem5::ThreadContext::pcState(), gem5::ThreadContext::readMiscRegNoEffect(), gem5::ThreadContext::setMiscRegNoEffect(), gem5::ThreadContext::setReg(), and gem5::BaseISA::tc.
This method doesn't need to adjust the Control Register Offset since it has already been done in the calling method (setRegWithEffect)
Definition at line 540 of file isa.cc.
References DPRINTF, miscRegFile, miscRegFile_WriteMask, and gem5::X86ISA::val.
Referenced by setMiscReg().
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inline |
Definition at line 457 of file isa.cc.
References miscRegFile, and gem5::MipsISA::misc_reg::TcBind.
Referenced by readMiscReg(), readMiscRegNoEffect(), setMiscReg(), setMiscRegNoEffect(), and setRegMask().
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inlineoverridevirtual |
Implements gem5::BaseISA.
Definition at line 165 of file isa.hh.
References gem5::MipsISA::misc_reg::Debug, readMiscRegNoEffect(), and gem5::MipsISA::misc_reg::Status.
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inlineoverridevirtual |
Implements gem5::BaseISA.
void gem5::MipsISA::ISA::processCP0Event | ( | BaseCPU * | cpu, |
CP0EventType | cp0EventType ) |
Process a CP0 event.
Definition at line 603 of file isa.cc.
References UpdateCP0, and updateCPU().
Referenced by scheduleCP0Update().
Definition at line 477 of file isa.cc.
References bankType, DPRINTF, getVPENum(), miscRegFile, miscRegNames, and perThreadContext.
Referenced by readMiscReg().
Definition at line 464 of file isa.cc.
References bankType, DPRINTF, getVPENum(), miscRegFile, miscRegNames, and perThreadContext.
Referenced by configCP(), inUserMode(), readMiscRegNoEffect(), and updateCPU().
Definition at line 560 of file isa.cc.
References gem5::Clocked::clockEdge(), cp0Updated, gem5::EventBase::CPU_Tick_Pri, processCP0Event(), gem5::EventManager::schedule(), and UpdateCP0.
Referenced by setMiscReg().
Implements gem5::BaseISA.
Definition at line 128 of file isa.hh.
References setMiscReg(), and gem5::X86ISA::val.
Definition at line 517 of file isa.cc.
References bankType, DPRINTF, filterCP0Write(), gem5::ThreadContext::getCpuPtr(), getVPENum(), miscRegFile, miscRegNames, perThreadContext, scheduleCP0Update(), gem5::BaseISA::tc, and gem5::X86ISA::val.
Referenced by setMiscReg().
Implements gem5::BaseISA.
Definition at line 121 of file isa.hh.
References setMiscRegNoEffect(), and gem5::X86ISA::val.
Definition at line 489 of file isa.cc.
References bankType, DPRINTF, getVPENum(), miscRegFile, miscRegNames, perThreadContext, and gem5::X86ISA::val.
Referenced by configCP(), and setMiscRegNoEffect().
Definition at line 502 of file isa.cc.
References bankType, DPRINTF, getVPENum(), miscRegFile_WriteMask, miscRegNames, perThreadContext, and gem5::X86ISA::val.
Referenced by configCP().
void gem5::MipsISA::ISA::updateCPU | ( | BaseCPU * | cpu | ) |
Definition at line 574 of file isa.cc.
References cp0Updated, gem5::BaseCPU::getContext(), gem5::MipsISA::haltThread(), gem5::MipsISA::misc_reg::MvpConf0, readMiscRegNoEffect(), gem5::MipsISA::restoreThread(), gem5::MipsISA::misc_reg::TcHalt, and gem5::MipsISA::misc_reg::TcStatus.
Referenced by processCP0Event().
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protected |
Definition at line 77 of file isa.hh.
Referenced by ISA(), readMiscReg(), readMiscRegNoEffect(), setMiscReg(), setMiscRegNoEffect(), and setRegMask().
bool gem5::MipsISA::ISA::cp0Updated |
Definition at line 141 of file isa.hh.
Referenced by scheduleCP0Update(), and updateCPU().
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protected |
Definition at line 75 of file isa.hh.
Referenced by clear(), filterCP0Write(), getVPENum(), ISA(), readMiscReg(), readMiscRegNoEffect(), setMiscReg(), and setMiscRegNoEffect().
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protected |
Definition at line 76 of file isa.hh.
Referenced by clear(), filterCP0Write(), ISA(), and setRegMask().
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static |
Definition at line 159 of file isa.hh.
Referenced by readMiscReg(), readMiscRegNoEffect(), setMiscReg(), setMiscRegNoEffect(), and setRegMask().
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protected |
Definition at line 65 of file isa.hh.
Referenced by configCP(), and ISA().
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protected |
Definition at line 66 of file isa.hh.
Referenced by configCP(), and ISA().