gem5  v21.1.0.2
Public Types | Public Member Functions | Public Attributes | Static Public Attributes | Protected Types | Protected Attributes | List of all members
gem5::MipsISA::ISA Class Reference

#include <isa.hh>

Inheritance diagram for gem5::MipsISA::ISA:
gem5::BaseISA gem5::SimObject gem5::EventManager gem5::Serializable gem5::Drainable gem5::statistics::Group gem5::Named

Public Types

enum  CP0EventType { UpdateCP0 }
 
typedef ISA CP0
 
using Params = MipsISAParams
 
- Public Types inherited from gem5::BaseISA
typedef std::vector< RegClassInfoRegClasses
 
- Public Types inherited from gem5::SimObject
typedef SimObjectParams Params
 

Public Member Functions

void clear ()
 
void configCP ()
 
unsigned getVPENum (ThreadID tid) const
 
void updateCP0ReadView (int misc_reg, ThreadID tid)
 
RegVal readMiscRegNoEffect (int misc_reg, ThreadID tid=0) const
 
RegVal readMiscReg (int misc_reg, ThreadID tid=0)
 
RegVal filterCP0Write (int misc_reg, int reg_sel, RegVal val)
 This method doesn't need to adjust the Control Register Offset since it has already been done in the calling method (setRegWithEffect) More...
 
void setRegMask (int misc_reg, RegVal val, ThreadID tid=0)
 
void setMiscRegNoEffect (int misc_reg, RegVal val, ThreadID tid=0)
 
void setMiscReg (int misc_reg, RegVal val, ThreadID tid=0)
 
void processCP0Event (BaseCPU *cpu, CP0EventType)
 Process a CP0 event. More...
 
void scheduleCP0Update (BaseCPU *cpu, Cycles delay=Cycles(0))
 
void updateCPU (BaseCPU *cpu)
 
 ISA (const Params &p)
 
RegId flattenRegId (const RegId &regId) const
 
int flattenIntIndex (int reg) const
 
int flattenFloatIndex (int reg) const
 
int flattenVecIndex (int reg) const
 
int flattenVecElemIndex (int reg) const
 
int flattenVecPredIndex (int reg) const
 
int flattenCCIndex (int reg) const
 
int flattenMiscIndex (int reg) const
 
bool inUserMode () const override
 
void copyRegsFrom (ThreadContext *src) override
 
- Public Member Functions inherited from gem5::BaseISA
virtual void takeOverFrom (ThreadContext *new_tc, ThreadContext *old_tc)
 
virtual void setThreadContext (ThreadContext *_tc)
 
virtual uint64_t getExecutingAsid () const
 
virtual enums::VecRegRenameMode initVecRegRenameMode () const
 
virtual enums::VecRegRenameMode vecRegRenameMode (ThreadContext *_tc) const
 
const RegClassesregClasses () const
 
- Public Member Functions inherited from gem5::SimObject
const Paramsparams () const
 
 SimObject (const Params &p)
 
virtual ~SimObject ()
 
virtual void init ()
 init() is called after all C++ SimObjects have been created and all ports are connected. More...
 
virtual void loadState (CheckpointIn &cp)
 loadState() is called on each SimObject when restoring from a checkpoint. More...
 
virtual void initState ()
 initState() is called on each SimObject when not restoring from a checkpoint. More...
 
virtual void regProbePoints ()
 Register probe points for this object. More...
 
virtual void regProbeListeners ()
 Register probe listeners for this object. More...
 
ProbeManagergetProbeManager ()
 Get the probe manager for this object. More...
 
virtual PortgetPort (const std::string &if_name, PortID idx=InvalidPortID)
 Get a port with a given name and index. More...
 
virtual void startup ()
 startup() is the final initialization call before simulation. More...
 
DrainState drain () override
 Provide a default implementation of the drain interface for objects that don't need draining. More...
 
virtual void memWriteback ()
 Write back dirty buffers to memory using functional writes. More...
 
virtual void memInvalidate ()
 Invalidate the contents of memory buffers. More...
 
void serialize (CheckpointOut &cp) const override
 Serialize an object. More...
 
void unserialize (CheckpointIn &cp) override
 Unserialize an object. More...
 
- Public Member Functions inherited from gem5::EventManager
EventQueueeventQueue () const
 
void schedule (Event &event, Tick when)
 
void deschedule (Event &event)
 
void reschedule (Event &event, Tick when, bool always=false)
 
void schedule (Event *event, Tick when)
 
void deschedule (Event *event)
 
void reschedule (Event *event, Tick when, bool always=false)
 
void wakeupEventQueue (Tick when=(Tick) -1)
 This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More...
 
void setCurTick (Tick newVal)
 
 EventManager (EventManager &em)
 Event manger manages events in the event queue. More...
 
 EventManager (EventManager *em)
 
 EventManager (EventQueue *eq)
 
- Public Member Functions inherited from gem5::Serializable
 Serializable ()
 
virtual ~Serializable ()
 
void serializeSection (CheckpointOut &cp, const char *name) const
 Serialize an object into a new section. More...
 
void serializeSection (CheckpointOut &cp, const std::string &name) const
 
void unserializeSection (CheckpointIn &cp, const char *name)
 Unserialize an a child object. More...
 
void unserializeSection (CheckpointIn &cp, const std::string &name)
 
- Public Member Functions inherited from gem5::Drainable
DrainState drainState () const
 Return the current drain state of an object. More...
 
virtual void notifyFork ()
 Notify a child process of a fork. More...
 
- Public Member Functions inherited from gem5::statistics::Group
 Group (Group *parent, const char *name=nullptr)
 Construct a new statistics group. More...
 
virtual ~Group ()
 
virtual void regStats ()
 Callback to set stat parameters. More...
 
virtual void resetStats ()
 Callback to reset stats. More...
 
virtual void preDumpStats ()
 Callback before stats are dumped. More...
 
void addStat (statistics::Info *info)
 Register a stat with this group. More...
 
const std::map< std::string, Group * > & getStatGroups () const
 Get all child groups associated with this object. More...
 
const std::vector< Info * > & getStats () const
 Get all stats associated with this object. More...
 
void addStatGroup (const char *name, Group *block)
 Add a stat block as a child of this block. More...
 
const InforesolveStat (std::string name) const
 Resolve a stat by its name within this group. More...
 
void mergeStatGroup (Group *block)
 Merge the contents (stats & children) of a block to this block. More...
 
 Group ()=delete
 
 Group (const Group &)=delete
 
Groupoperator= (const Group &)=delete
 
- Public Member Functions inherited from gem5::Named
 Named (const std::string &name_)
 
virtual ~Named ()=default
 
virtual std::string name () const
 

Public Attributes

bool cp0Updated
 

Static Public Attributes

static std::string miscRegNames [MISCREG_NUMREGS]
 

Protected Types

enum  BankType { perProcessor, perThreadContext, perVirtProcessor }
 

Protected Attributes

uint8_t numThreads
 
uint8_t numVpes
 
std::vector< std::vector< RegVal > > miscRegFile
 
std::vector< std::vector< RegVal > > miscRegFile_WriteMask
 
std::vector< BankTypebankType
 
- Protected Attributes inherited from gem5::BaseISA
ThreadContexttc = nullptr
 
RegClasses _regClasses
 
- Protected Attributes inherited from gem5::SimObject
const SimObjectParams & _params
 Cached copy of the object parameters. More...
 
- Protected Attributes inherited from gem5::EventManager
EventQueueeventq
 A pointer to this object's event queue. More...
 

Additional Inherited Members

- Static Public Member Functions inherited from gem5::SimObject
static void serializeAll (const std::string &cpt_dir)
 Create a checkpoint by serializing all SimObjects in the system. More...
 
static SimObjectfind (const char *name)
 Find the SimObject with the given name and return a pointer to it. More...
 
static void setSimObjectResolver (SimObjectResolver *resolver)
 There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...
 
static SimObjectResolvergetSimObjectResolver ()
 There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...
 
- Static Public Member Functions inherited from gem5::Serializable
static const std::string & currentSection ()
 Gets the fully-qualified name of the active section. More...
 
static void generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
 Generate a checkpoint file so that the serialization can be routed to it. More...
 
- Protected Member Functions inherited from gem5::BaseISA
 SimObject (const Params &p)
 
- Protected Member Functions inherited from gem5::Drainable
 Drainable ()
 
virtual ~Drainable ()
 
virtual void drainResume ()
 Resume execution after a successful drain. More...
 
void signalDrainDone () const
 Signal that an object is drained. More...
 

Detailed Description

Definition at line 54 of file isa.hh.

Member Typedef Documentation

◆ CP0

Definition at line 58 of file isa.hh.

◆ Params

using gem5::MipsISA::ISA::Params = MipsISAParams

Definition at line 60 of file isa.hh.

Member Enumeration Documentation

◆ BankType

Enumerator
perProcessor 
perThreadContext 
perVirtProcessor 

Definition at line 67 of file isa.hh.

◆ CP0EventType

Enumerator
UpdateCP0 

Definition at line 118 of file isa.hh.

Constructor & Destructor Documentation

◆ ISA()

gem5::MipsISA::ISA::ISA ( const Params p)

Member Function Documentation

◆ clear()

void gem5::MipsISA::ISA::clear ( )

◆ configCP()

void gem5::MipsISA::ISA::configCP ( )

Definition at line 191 of file isa.cc.

References gem5::MipsISA::CoreSpecific::CP0_Config1_C2, gem5::MipsISA::CoreSpecific::CP0_Config1_DA, gem5::MipsISA::CoreSpecific::CP0_Config1_DL, gem5::MipsISA::CoreSpecific::CP0_Config1_DS, gem5::MipsISA::CoreSpecific::CP0_Config1_EP, gem5::MipsISA::CoreSpecific::CP0_Config1_FP, gem5::MipsISA::CoreSpecific::CP0_Config1_IA, gem5::MipsISA::CoreSpecific::CP0_Config1_IL, gem5::MipsISA::CoreSpecific::CP0_Config1_IS, gem5::MipsISA::CoreSpecific::CP0_Config1_M, gem5::MipsISA::CoreSpecific::CP0_Config1_MD, gem5::MipsISA::CoreSpecific::CP0_Config1_MMU, gem5::MipsISA::CoreSpecific::CP0_Config1_PC, gem5::MipsISA::CoreSpecific::CP0_Config1_WR, gem5::MipsISA::CoreSpecific::CP0_Config2_M, gem5::MipsISA::CoreSpecific::CP0_Config2_SA, gem5::MipsISA::CoreSpecific::CP0_Config2_SL, gem5::MipsISA::CoreSpecific::CP0_Config2_SS, gem5::MipsISA::CoreSpecific::CP0_Config2_SU, gem5::MipsISA::CoreSpecific::CP0_Config2_TA, gem5::MipsISA::CoreSpecific::CP0_Config2_TL, gem5::MipsISA::CoreSpecific::CP0_Config2_TS, gem5::MipsISA::CoreSpecific::CP0_Config2_TU, gem5::MipsISA::CoreSpecific::CP0_Config3_DSPP, gem5::MipsISA::CoreSpecific::CP0_Config3_LPA, gem5::MipsISA::CoreSpecific::CP0_Config3_MT, gem5::MipsISA::CoreSpecific::CP0_Config3_SM, gem5::MipsISA::CoreSpecific::CP0_Config3_SP, gem5::MipsISA::CoreSpecific::CP0_Config3_TL, gem5::MipsISA::CoreSpecific::CP0_Config3_VEIC, gem5::MipsISA::CoreSpecific::CP0_Config3_VInt, gem5::MipsISA::CoreSpecific::CP0_Config_AR, gem5::MipsISA::CoreSpecific::CP0_Config_AT, gem5::MipsISA::CoreSpecific::CP0_Config_BE, gem5::MipsISA::CoreSpecific::CP0_Config_MT, gem5::MipsISA::CoreSpecific::CP0_Config_VI, gem5::MipsISA::CoreSpecific::CP0_EBase_CPUNum, gem5::MipsISA::CoreSpecific::CP0_IntCtl_IPPCI, gem5::MipsISA::CoreSpecific::CP0_IntCtl_IPTI, gem5::MipsISA::CoreSpecific::CP0_PerfCtr_M, gem5::MipsISA::CoreSpecific::CP0_PerfCtr_W, gem5::MipsISA::CoreSpecific::CP0_PRId_CompanyID, gem5::MipsISA::CoreSpecific::CP0_PRId_CompanyOptions, gem5::MipsISA::CoreSpecific::CP0_PRId_ProcessorID, gem5::MipsISA::CoreSpecific::CP0_PRId_Revision, gem5::MipsISA::CoreSpecific::CP0_SrsCtl_HSS, gem5::MipsISA::CoreSpecific::CP0_WatchHi_M, DPRINTF, gem5::MipsISA::mask, gem5::MipsISA::MISCREG_BADVADDR, gem5::MipsISA::MISCREG_CAUSE, gem5::MipsISA::MISCREG_CONFIG, gem5::MipsISA::MISCREG_CONFIG1, gem5::MipsISA::MISCREG_CONFIG2, gem5::MipsISA::MISCREG_CONFIG3, gem5::MipsISA::MISCREG_CONTEXT, gem5::MipsISA::MISCREG_CP0_RANDOM, gem5::MipsISA::MISCREG_EBASE, gem5::MipsISA::MISCREG_ENTRYLO0, gem5::MipsISA::MISCREG_ENTRYLO1, gem5::MipsISA::MISCREG_INDEX, gem5::MipsISA::MISCREG_INTCTL, gem5::MipsISA::MISCREG_LLADDR, gem5::MipsISA::MISCREG_MVP_CONF0, gem5::MipsISA::MISCREG_PAGEGRAIN, gem5::MipsISA::MISCREG_PAGEMASK, gem5::MipsISA::MISCREG_PERFCNT0, gem5::MipsISA::MISCREG_PRID, gem5::MipsISA::MISCREG_SRSCTL, gem5::MipsISA::MISCREG_STATUS, gem5::MipsISA::MISCREG_TC_BIND, gem5::MipsISA::MISCREG_TC_HALT, gem5::MipsISA::MISCREG_TC_STATUS, gem5::MipsISA::MISCREG_VPE_CONF0, gem5::MipsISA::MISCREG_WATCHHI0, numThreads, numVpes, panic, gem5::MipsISA::procId, readMiscRegNoEffect(), gem5::replaceBits(), setMiscRegNoEffect(), setRegMask(), and gem5::ArmISA::status.

◆ copyRegsFrom()

void gem5::MipsISA::ISA::copyRegsFrom ( ThreadContext src)
overridevirtual

◆ filterCP0Write()

RegVal gem5::MipsISA::ISA::filterCP0Write ( int  misc_reg,
int  reg_sel,
RegVal  val 
)

This method doesn't need to adjust the Control Register Offset since it has already been done in the calling method (setRegWithEffect)

Definition at line 525 of file isa.cc.

References DPRINTF, miscRegFile, miscRegFile_WriteMask, and gem5::X86ISA::val.

Referenced by setMiscReg().

◆ flattenCCIndex()

int gem5::MipsISA::ISA::flattenCCIndex ( int  reg) const
inline

Definition at line 146 of file isa.hh.

References gem5::X86ISA::reg.

◆ flattenFloatIndex()

int gem5::MipsISA::ISA::flattenFloatIndex ( int  reg) const
inline

Definition at line 141 of file isa.hh.

References gem5::X86ISA::reg.

◆ flattenIntIndex()

int gem5::MipsISA::ISA::flattenIntIndex ( int  reg) const
inline

Definition at line 140 of file isa.hh.

References gem5::X86ISA::reg.

◆ flattenMiscIndex()

int gem5::MipsISA::ISA::flattenMiscIndex ( int  reg) const
inline

Definition at line 147 of file isa.hh.

References gem5::X86ISA::reg.

◆ flattenRegId()

RegId gem5::MipsISA::ISA::flattenRegId ( const RegId regId) const
inline

Definition at line 138 of file isa.hh.

◆ flattenVecElemIndex()

int gem5::MipsISA::ISA::flattenVecElemIndex ( int  reg) const
inline

Definition at line 143 of file isa.hh.

References gem5::X86ISA::reg.

◆ flattenVecIndex()

int gem5::MipsISA::ISA::flattenVecIndex ( int  reg) const
inline

Definition at line 142 of file isa.hh.

References gem5::X86ISA::reg.

◆ flattenVecPredIndex()

int gem5::MipsISA::ISA::flattenVecPredIndex ( int  reg) const
inline

Definition at line 144 of file isa.hh.

References gem5::X86ISA::reg.

◆ getVPENum()

unsigned gem5::MipsISA::ISA::getVPENum ( ThreadID  tid) const
inline

◆ inUserMode()

bool gem5::MipsISA::ISA::inUserMode ( ) const
inlineoverridevirtual

◆ processCP0Event()

void gem5::MipsISA::ISA::processCP0Event ( BaseCPU cpu,
CP0EventType  cp0EventType 
)

Process a CP0 event.

Definition at line 588 of file isa.cc.

References UpdateCP0, and updateCPU().

Referenced by scheduleCP0Update().

◆ readMiscReg()

RegVal gem5::MipsISA::ISA::readMiscReg ( int  misc_reg,
ThreadID  tid = 0 
)

Definition at line 461 of file isa.cc.

References bankType, DPRINTF, getVPENum(), miscRegFile, miscRegNames, and perThreadContext.

◆ readMiscRegNoEffect()

RegVal gem5::MipsISA::ISA::readMiscRegNoEffect ( int  misc_reg,
ThreadID  tid = 0 
) const

Definition at line 447 of file isa.cc.

References bankType, DPRINTF, getVPENum(), miscRegFile, miscRegNames, and perThreadContext.

Referenced by configCP(), inUserMode(), and updateCPU().

◆ scheduleCP0Update()

void gem5::MipsISA::ISA::scheduleCP0Update ( BaseCPU cpu,
Cycles  delay = Cycles(0) 
)

◆ setMiscReg()

void gem5::MipsISA::ISA::setMiscReg ( int  misc_reg,
RegVal  val,
ThreadID  tid = 0 
)

◆ setMiscRegNoEffect()

void gem5::MipsISA::ISA::setMiscRegNoEffect ( int  misc_reg,
RegVal  val,
ThreadID  tid = 0 
)

Definition at line 474 of file isa.cc.

References bankType, DPRINTF, getVPENum(), miscRegFile, miscRegNames, perThreadContext, and gem5::X86ISA::val.

Referenced by configCP().

◆ setRegMask()

void gem5::MipsISA::ISA::setRegMask ( int  misc_reg,
RegVal  val,
ThreadID  tid = 0 
)

Definition at line 487 of file isa.cc.

References bankType, DPRINTF, getVPENum(), miscRegFile_WriteMask, miscRegNames, perThreadContext, and gem5::X86ISA::val.

Referenced by configCP().

◆ updateCP0ReadView()

void gem5::MipsISA::ISA::updateCP0ReadView ( int  misc_reg,
ThreadID  tid 
)
inline

Definition at line 94 of file isa.hh.

◆ updateCPU()

void gem5::MipsISA::ISA::updateCPU ( BaseCPU cpu)

Member Data Documentation

◆ bankType

std::vector<BankType> gem5::MipsISA::ISA::bankType
protected

Definition at line 76 of file isa.hh.

Referenced by ISA(), readMiscReg(), readMiscRegNoEffect(), setMiscReg(), setMiscRegNoEffect(), and setRegMask().

◆ cp0Updated

bool gem5::MipsISA::ISA::cp0Updated

Definition at line 115 of file isa.hh.

Referenced by scheduleCP0Update(), and updateCPU().

◆ miscRegFile

std::vector<std::vector<RegVal> > gem5::MipsISA::ISA::miscRegFile
protected

◆ miscRegFile_WriteMask

std::vector<std::vector<RegVal> > gem5::MipsISA::ISA::miscRegFile_WriteMask
protected

Definition at line 75 of file isa.hh.

Referenced by clear(), filterCP0Write(), ISA(), and setRegMask().

◆ miscRegNames

std::string gem5::MipsISA::ISA::miscRegNames
static

Definition at line 133 of file isa.hh.

Referenced by readMiscReg(), readMiscRegNoEffect(), setMiscReg(), setMiscRegNoEffect(), and setRegMask().

◆ numThreads

uint8_t gem5::MipsISA::ISA::numThreads
protected

Definition at line 64 of file isa.hh.

Referenced by configCP(), and ISA().

◆ numVpes

uint8_t gem5::MipsISA::ISA::numVpes
protected

Definition at line 65 of file isa.hh.

Referenced by configCP(), and ISA().


The documentation for this class was generated from the following files:

Generated on Tue Sep 21 2021 12:31:39 for gem5 by doxygen 1.8.17