gem5  v21.1.0.2
isa.cc
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28 
29 #include "arch/mips/isa.hh"
30 
31 #include "arch/mips/mt.hh"
34 #include "arch/mips/regs/float.hh"
35 #include "arch/mips/regs/int.hh"
36 #include "arch/mips/regs/misc.hh"
37 #include "base/bitfield.hh"
38 #include "cpu/base.hh"
39 #include "cpu/reg_class.hh"
40 #include "cpu/thread_context.hh"
41 #include "debug/MipsPRA.hh"
42 #include "params/MipsISA.hh"
43 
44 namespace gem5
45 {
46 
47 namespace MipsISA
48 {
49 
50 std::string
52 {
53  "Index", "MVPControl", "MVPConf0", "MVPConf1", "", "", "", "",
54  "Random", "VPEControl", "VPEConf0", "VPEConf1",
55  "YQMask", "VPESchedule", "VPEScheFBack", "VPEOpt",
56  "EntryLo0", "TCStatus", "TCBind", "TCRestart",
57  "TCHalt", "TCContext", "TCSchedule", "TCScheFBack",
58  "EntryLo1", "", "", "", "", "", "", "",
59  "Context", "ContextConfig", "", "", "", "", "", "",
60  "PageMask", "PageGrain", "", "", "", "", "", "",
61  "Wired", "SRSConf0", "SRCConf1", "SRSConf2",
62  "SRSConf3", "SRSConf4", "", "",
63  "HWREna", "", "", "", "", "", "", "",
64  "BadVAddr", "", "", "", "", "", "", "",
65  "Count", "", "", "", "", "", "", "",
66  "EntryHi", "", "", "", "", "", "", "",
67  "Compare", "", "", "", "", "", "", "",
68  "Status", "IntCtl", "SRSCtl", "SRSMap", "", "", "", "",
69  "Cause", "", "", "", "", "", "", "",
70  "EPC", "", "", "", "", "", "", "",
71  "PRId", "EBase", "", "", "", "", "", "",
72  "Config", "Config1", "Config2", "Config3", "", "", "", "",
73  "LLAddr", "", "", "", "", "", "", "",
74  "WatchLo0", "WatchLo1", "WatchLo2", "WatchLo3",
75  "WatchLo4", "WatchLo5", "WatchLo6", "WatchLo7",
76  "WatchHi0", "WatchHi1", "WatchHi2", "WatchHi3",
77  "WatchHi4", "WatchHi5", "WatchHi6", "WatchHi7",
78  "XCContext64", "", "", "", "", "", "", "",
79  "", "", "", "", "", "", "", "",
80  "", "", "", "", "", "", "", "",
81  "Debug", "TraceControl1", "TraceControl2", "UserTraceData",
82  "TraceBPC", "", "", "",
83  "DEPC", "", "", "", "", "", "", "",
84  "PerfCnt0", "PerfCnt1", "PerfCnt2", "PerfCnt3",
85  "PerfCnt4", "PerfCnt5", "PerfCnt6", "PerfCnt7",
86  "ErrCtl", "", "", "", "", "", "", "",
87  "CacheErr0", "CacheErr1", "CacheErr2", "CacheErr3", "", "", "", "",
88  "TagLo0", "DataLo1", "TagLo2", "DataLo3",
89  "TagLo4", "DataLo5", "TagLo6", "DataLo7",
90  "TagHi0", "DataHi1", "TagHi2", "DataHi3",
91  "TagHi4", "DataHi5", "TagHi6", "DataHi7",
92  "ErrorEPC", "", "", "", "", "", "", "",
93  "DESAVE", "", "", "", "", "", "", "",
94  "LLFlag"
95 };
96 
97 ISA::ISA(const Params &p) : BaseISA(p), numThreads(p.num_threads),
98  numVpes(p.num_vpes)
99 {
100  _regClasses.emplace_back(NumIntRegs, 0);
101  _regClasses.emplace_back(NumFloatRegs);
102  _regClasses.emplace_back(1); // Not applicable to MIPS.
103  _regClasses.emplace_back(2); // Not applicable to MIPS.
104  _regClasses.emplace_back(1); // Not applicable to MIPS.
105  _regClasses.emplace_back(0); // Not applicable to MIPS.
106  _regClasses.emplace_back(MISCREG_NUMREGS);
107 
109  bankType.resize(MISCREG_NUMREGS);
110 
111  for (int i = 0; i < MISCREG_NUMREGS; i++) {
112  miscRegFile[i].resize(1);
114  }
115 
117 
118  for (int i = 0; i < MISCREG_NUMREGS; i++) {
119  miscRegFile_WriteMask[i].push_back(0);
120  }
121 
122  // Initialize all Per-VPE regs
123  uint32_t per_vpe_regs[] = { MISCREG_VPE_CONTROL,
131  };
132  uint32_t num_vpe_regs = sizeof(per_vpe_regs) / 4;
133  for (int i = 0; i < num_vpe_regs; i++) {
134  if (numVpes > 1) {
135  miscRegFile[per_vpe_regs[i]].resize(numVpes);
136  }
137  bankType[per_vpe_regs[i]] = perVirtProcessor;
138  }
139 
140  // Initialize all Per-TC regs
141  uint32_t per_tc_regs[] = { MISCREG_STATUS,
147  };
148  uint32_t num_tc_regs = sizeof(per_tc_regs) / 4;
149 
150  for (int i = 0; i < num_tc_regs; i++) {
151  miscRegFile[per_tc_regs[i]].resize(numThreads);
152  bankType[per_tc_regs[i]] = perThreadContext;
153  }
154 
155  clear();
156 }
157 
158 void
160 {
161  for (int i = 0; i < MISCREG_NUMREGS; i++) {
162  for (int j = 0; j < miscRegFile[i].size(); j++)
163  miscRegFile[i][j] = 0;
164 
165  for (int k = 0; k < miscRegFile_WriteMask[i].size(); k++)
166  miscRegFile_WriteMask[i][k] = (long unsigned int)(-1);
167  }
168 }
169 
170 void
172 {
173  // First loop through the integer registers.
174  for (int i = 0; i < NumIntRegs; i++)
175  tc->setIntRegFlat(i, src->readIntRegFlat(i));
176 
177  // Then loop through the floating point registers.
178  for (int i = 0; i < NumFloatRegs; i++)
180 
181  // Copy misc. registers
182  for (int i = 0; i < MISCREG_NUMREGS; i++)
184 
185  // Copy over the PC State
186  tc->pcState(src->pcState());
187 }
188 
189 
190 void
192 {
193  DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n",
195 
196  CoreSpecific cp;
197  panic("CP state must be set before the following code is used");
198 
199  // Do Default CP0 initialization HERE
200 
201  // Do Initialization for MT cores here (eventually use
202  // core_name parameter to toggle this initialization)
203  // ===================================================
204  DPRINTF(MipsPRA, "Initializing CP0 State.... ");
205 
208  procId.coId = cp.CP0_PRId_CompanyID;
209  procId.procId = cp.CP0_PRId_ProcessorID;
210  procId.rev = cp.CP0_PRId_Revision;
212 
213  // Now, create Write Mask for ProcID register
214  RegVal procIDMask = 0; // Read-Only register
215  replaceBits(procIDMask, 32, 0, 0);
216  setRegMask(MISCREG_PRID, procIDMask);
217 
218  // Config
219  ConfigReg cfg = readMiscRegNoEffect(MISCREG_CONFIG);
220  cfg.be = cp.CP0_Config_BE;
221  cfg.at = cp.CP0_Config_AT;
222  cfg.ar = cp.CP0_Config_AR;
223  cfg.mt = cp.CP0_Config_MT;
224  cfg.vi = cp.CP0_Config_VI;
225  cfg.m = 1;
227  // Now, create Write Mask for Config register
228  RegVal cfg_Mask = 0x7FFF0007;
229  replaceBits(cfg_Mask, 32, 0, 0);
230  setRegMask(MISCREG_CONFIG, cfg_Mask);
231 
232  // Config1
233  Config1Reg cfg1 = readMiscRegNoEffect(MISCREG_CONFIG1);
234  cfg1.mmuSize = cp.CP0_Config1_MMU;
235  cfg1.is = cp.CP0_Config1_IS;
236  cfg1.il = cp.CP0_Config1_IL;
237  cfg1.ia = cp.CP0_Config1_IA;
238  cfg1.ds = cp.CP0_Config1_DS;
239  cfg1.dl = cp.CP0_Config1_DL;
240  cfg1.da = cp.CP0_Config1_DA;
241  cfg1.fp = cp.CP0_Config1_FP;
242  cfg1.ep = cp.CP0_Config1_EP;
243  cfg1.wr = cp.CP0_Config1_WR;
244  cfg1.md = cp.CP0_Config1_MD;
245  cfg1.c2 = cp.CP0_Config1_C2;
246  cfg1.pc = cp.CP0_Config1_PC;
247  cfg1.m = cp.CP0_Config1_M;
249  // Now, create Write Mask for Config register
250  RegVal cfg1_Mask = 0; // Read Only Register
251  replaceBits(cfg1_Mask, 32,0 , 0);
252  setRegMask(MISCREG_CONFIG1, cfg1_Mask);
253 
254  // Config2
255  Config2Reg cfg2 = readMiscRegNoEffect(MISCREG_CONFIG2);
256  cfg2.tu = cp.CP0_Config2_TU;
257  cfg2.ts = cp.CP0_Config2_TS;
258  cfg2.tl = cp.CP0_Config2_TL;
259  cfg2.ta = cp.CP0_Config2_TA;
260  cfg2.su = cp.CP0_Config2_SU;
261  cfg2.ss = cp.CP0_Config2_SS;
262  cfg2.sl = cp.CP0_Config2_SL;
263  cfg2.sa = cp.CP0_Config2_SA;
264  cfg2.m = cp.CP0_Config2_M;
266  // Now, create Write Mask for Config register
267  RegVal cfg2_Mask = 0x7000F000; // Read Only Register
268  replaceBits(cfg2_Mask, 32, 0, 0);
269  setRegMask(MISCREG_CONFIG2, cfg2_Mask);
270 
271  // Config3
272  Config3Reg cfg3 = readMiscRegNoEffect(MISCREG_CONFIG3);
273  cfg3.dspp = cp.CP0_Config3_DSPP;
274  cfg3.lpa = cp.CP0_Config3_LPA;
275  cfg3.veic = cp.CP0_Config3_VEIC;
276  cfg3.vint = cp.CP0_Config3_VInt;
277  cfg3.sp = cp.CP0_Config3_SP;
278  cfg3.mt = cp.CP0_Config3_MT;
279  cfg3.sm = cp.CP0_Config3_SM;
280  cfg3.tl = cp.CP0_Config3_TL;
282  // Now, create Write Mask for Config register
283  RegVal cfg3_Mask = 0; // Read Only Register
284  replaceBits(cfg3_Mask, 32,0 , 0);
285  setRegMask(MISCREG_CONFIG3, cfg3_Mask);
286 
287  // EBase - CPUNum
288  EBaseReg eBase = readMiscRegNoEffect(MISCREG_EBASE);
289  eBase.cpuNum = cp.CP0_EBase_CPUNum;
290  replaceBits(eBase, 31, 31, 1);
292  // Now, create Write Mask for Config register
293  RegVal EB_Mask = 0x3FFFF000;// Except Exception Base, the
294  // entire register is read only
295  replaceBits(EB_Mask, 32, 0, 0);
296  setRegMask(MISCREG_EBASE, EB_Mask);
297 
298  // SRS Control - HSS (Highest Shadow Set)
299  SRSCtlReg scsCtl = readMiscRegNoEffect(MISCREG_SRSCTL);
300  scsCtl.hss = cp.CP0_SrsCtl_HSS;
302  // Now, create Write Mask for the SRS Ctl register
303  RegVal SC_Mask = 0x0000F3C0;
304  replaceBits(SC_Mask, 32, 0, 0);
305  setRegMask(MISCREG_SRSCTL, SC_Mask);
306 
307  // IntCtl - IPTI, IPPCI
308  IntCtlReg intCtl = readMiscRegNoEffect(MISCREG_INTCTL);
309  intCtl.ipti = cp.CP0_IntCtl_IPTI;
310  intCtl.ippci = cp.CP0_IntCtl_IPPCI;
312  // Now, create Write Mask for the IntCtl register
313  RegVal IC_Mask = 0x000003E0;
314  replaceBits(IC_Mask, 32, 0, 0);
315  setRegMask(MISCREG_INTCTL, IC_Mask);
316 
317  // Watch Hi - M - FIXME (More than 1 Watch register)
318  WatchHiReg watchHi = readMiscRegNoEffect(MISCREG_WATCHHI0);
319  watchHi.m = cp.CP0_WatchHi_M;
321  // Now, create Write Mask for the IntCtl register
322  RegVal wh_Mask = 0x7FFF0FFF;
323  replaceBits(wh_Mask, 32, 0, 0);
324  setRegMask(MISCREG_WATCHHI0, wh_Mask);
325 
326  // Perf Ctr - M - FIXME (More than 1 PerfCnt Pair)
327  PerfCntCtlReg perfCntCtl = readMiscRegNoEffect(MISCREG_PERFCNT0);
328  perfCntCtl.m = cp.CP0_PerfCtr_M;
329  perfCntCtl.w = cp.CP0_PerfCtr_W;
331  // Now, create Write Mask for the IntCtl register
332  RegVal pc_Mask = 0x00007FF;
333  replaceBits(pc_Mask, 32, 0, 0);
334  setRegMask(MISCREG_PERFCNT0, pc_Mask);
335 
336  // Random
338  // Now, create Write Mask for the IntCtl register
339  RegVal random_Mask = 0;
340  replaceBits(random_Mask, 32, 0, 0);
341  setRegMask(MISCREG_CP0_RANDOM, random_Mask);
342 
343  // PageGrain
344  PageGrainReg pageGrain = readMiscRegNoEffect(MISCREG_PAGEGRAIN);
345  pageGrain.esp = cp.CP0_Config3_SP;
347  // Now, create Write Mask for the IntCtl register
348  RegVal pg_Mask = 0x10000000;
349  replaceBits(pg_Mask, 32, 0, 0);
350  setRegMask(MISCREG_PAGEGRAIN, pg_Mask);
351 
352  // Status
354  // Only CU0 and IE are modified on a reset - everything else needs
355  // to be controlled on a per CPU model basis
356 
357  // Enable CP0 on reset
358  // status.cu0 = 1;
359 
360  // Enable ERL bit on a reset
361  status.erl = 1;
362  // Enable BEV bit on a reset
363  status.bev = 1;
364 
366  // Now, create Write Mask for the Status register
367  RegVal stat_Mask = 0xFF78FF17;
368  replaceBits(stat_Mask, 32, 0, 0);
369  setRegMask(MISCREG_STATUS, stat_Mask);
370 
371 
372  // MVPConf0
373  MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0);
374  mvpConf0.tca = 1;
375  mvpConf0.pvpe = numVpes - 1;
376  mvpConf0.ptc = numThreads - 1;
378 
379  // VPEConf0
380  VPEConf0Reg vpeConf0 = readMiscRegNoEffect(MISCREG_VPE_CONF0);
381  vpeConf0.mvp = 1;
383 
384  // TCBind
385  for (ThreadID tid = 0; tid < numThreads; tid++) {
386  TCBindReg tcBind = readMiscRegNoEffect(MISCREG_TC_BIND, tid);
387  tcBind.curTC = tid;
388  setMiscRegNoEffect(MISCREG_TC_BIND, tcBind, tid);
389  }
390  // TCHalt
391  TCHaltReg tcHalt = readMiscRegNoEffect(MISCREG_TC_HALT);
392  tcHalt.h = 0;
394 
395  // TCStatus
396  // Set TCStatus Activated to 1 for the initial thread that is running
397  TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS);
398  tcStatus.a = 1;
400 
401  // Set Dynamically Allocatable bit to 1 for all other threads
402  for (ThreadID tid = 1; tid < numThreads; tid++) {
403  tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid);
404  tcStatus.da = 1;
405  setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus, tid);
406  }
407 
408 
409  RegVal mask = 0x7FFFFFFF;
410 
411  // Now, create Write Mask for the Index register
412  replaceBits(mask, 32, 0, 0);
414 
415  mask = 0x3FFFFFFF;
416  replaceBits(mask, 32, 0, 0);
419 
420  mask = 0xFF800000;
421  replaceBits(mask, 32, 0, 0);
423 
424  mask = 0x1FFFF800;
425  replaceBits(mask, 32, 0, 0);
427 
428  mask = 0x0;
429  replaceBits(mask, 32, 0, 0);
432 
433  mask = 0x08C00300;
434  replaceBits(mask, 32, 0, 0);
436 
437 }
438 
439 inline unsigned
441 {
442  TCBindReg tcBind = miscRegFile[MISCREG_TC_BIND][tid];
443  return tcBind.curVPE;
444 }
445 
446 RegVal
447 ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
448 {
449  unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
450  ? tid : getVPENum(tid);
451  DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) (%lx).\n",
452  misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
453  miscRegFile[misc_reg][reg_sel]);
454  return miscRegFile[misc_reg][reg_sel];
455 }
456 
457 //@TODO: MIPS MT's register view automatically connects
458 // Status to TCStatus depending on current thread
459 //template <class TC>
460 RegVal
461 ISA::readMiscReg(int misc_reg, ThreadID tid)
462 {
463  unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
464  ? tid : getVPENum(tid);
465  DPRINTF(MipsPRA,
466  "Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n",
467  misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
468  miscRegFile[misc_reg][reg_sel]);
469 
470  return miscRegFile[misc_reg][reg_sel];
471 }
472 
473 void
475 {
476  unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
477  ? tid : getVPENum(tid);
478  DPRINTF(MipsPRA,
479  "[tid:%i] Setting (direct set) CP0 Register:%u "
480  "Select:%u (%s) to %#x.\n",
481  tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
482 
483  miscRegFile[misc_reg][reg_sel] = val;
484 }
485 
486 void
487 ISA::setRegMask(int misc_reg, RegVal val, ThreadID tid)
488 {
489  unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
490  ? tid : getVPENum(tid);
491  DPRINTF(MipsPRA,
492  "[tid:%i] Setting CP0 Register: %u Select: %u (%s) to %#x\n",
493  tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
494  miscRegFile_WriteMask[misc_reg][reg_sel] = val;
495 }
496 
497 // PROGRAMMER'S NOTES:
498 // (1) Some CP0 Registers have fields that cannot
499 // be overwritten. Make sure to handle those particular registers
500 // with care!
501 void
502 ISA::setMiscReg(int misc_reg, RegVal val, ThreadID tid)
503 {
504  int reg_sel = (bankType[misc_reg] == perThreadContext)
505  ? tid : getVPENum(tid);
506 
507  DPRINTF(MipsPRA,
508  "[tid:%i] Setting CP0 Register:%u "
509  "Select:%u (%s) to %#x, with effect.\n",
510  tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
511 
512  RegVal cp0_val = filterCP0Write(misc_reg, reg_sel, val);
513 
514  miscRegFile[misc_reg][reg_sel] = cp0_val;
515 
517 }
518 
524 RegVal
525 ISA::filterCP0Write(int misc_reg, int reg_sel, RegVal val)
526 {
527  RegVal retVal = val;
528 
529  // Mask off read-only regions
530  retVal &= miscRegFile_WriteMask[misc_reg][reg_sel];
531  RegVal curVal = miscRegFile[misc_reg][reg_sel];
532  // Mask off current alue with inverse mask (clear writeable bits)
533  curVal &= (~miscRegFile_WriteMask[misc_reg][reg_sel]);
534  retVal |= curVal; // Combine the two
535  DPRINTF(MipsPRA,
536  "filterCP0Write: Mask: %lx, Inverse Mask: %lx, write Val: %x, "
537  "current val: %lx, written val: %x\n",
538  miscRegFile_WriteMask[misc_reg][reg_sel],
539  ~miscRegFile_WriteMask[misc_reg][reg_sel],
540  val, miscRegFile[misc_reg][reg_sel], retVal);
541  return retVal;
542 }
543 
544 void
546 {
547  if (!cp0Updated) {
548  cp0Updated = true;
549 
550  //schedule UPDATE
551  auto cp0_event = new EventFunctionWrapper(
552  [this, cpu]{ processCP0Event(cpu, UpdateCP0); },
553  "Coprocessor-0 event", true, Event::CPU_Tick_Pri);
554  cpu->schedule(cp0_event, cpu->clockEdge(delay));
555  }
556 }
557 
558 void
560 {
562  //
563  // EVALUATE CP0 STATE FOR MIPS MT
564  //
566  MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0);
567  ThreadID num_threads = mvpConf0.ptc + 1;
568 
569  for (ThreadID tid = 0; tid < num_threads; tid++) {
570  TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid);
571  TCHaltReg tcHalt = readMiscRegNoEffect(MISCREG_TC_HALT, tid);
572 
573  //@todo: add vpe/mt check here thru mvpcontrol & vpecontrol regs
574  if (tcHalt.h == 1 || tcStatus.a == 0) {
575  haltThread(cpu->getContext(tid));
576  } else if (tcHalt.h == 0 && tcStatus.a == 1) {
577  restoreThread(cpu->getContext(tid));
578  }
579  }
580 
581  num_threads = mvpConf0.ptc + 1;
582 
583  // Toggle update flag after we finished updating
584  cp0Updated = false;
585 }
586 
587 void
589 {
590  switch (cp0EventType)
591  {
592  case UpdateCP0:
593  updateCPU(cpu);
594  break;
595  }
596 }
597 
598 } // namespace MipsISA
599 } // namespace gem5
gem5::MipsISA::MISCREG_ENTRYLO0
@ MISCREG_ENTRYLO0
Definition: misc.hh:62
gem5::MipsISA::procId
Bitfield< 15, 8 > procId
Definition: pra_constants.hh:206
gem5::MipsISA::ISA::bankType
std::vector< BankType > bankType
Definition: isa.hh:76
misc.hh
gem5::MipsISA::mask
mask
Definition: pra_constants.hh:73
gem5::MipsISA::CoreSpecific::CP0_Config1_DS
unsigned CP0_Config1_DS
Definition: types.hh:125
isa.hh
gem5::BaseISA::tc
ThreadContext * tc
Definition: isa.hh:62
gem5::MipsISA::CoreSpecific::CP0_Config2_TA
unsigned CP0_Config2_TA
Definition: types.hh:139
gem5::MipsISA::MISCREG_CONFIG3
@ MISCREG_CONFIG3
Definition: misc.hh:111
gem5::MipsISA::restoreThread
void restoreThread(TC *tc)
Definition: mt.hh:154
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::MipsISA::MISCREG_PRID
@ MISCREG_PRID
Definition: misc.hh:105
gem5::MipsISA::CoreSpecific::CP0_Config3_SM
bool CP0_Config3_SM
Definition: types.hh:151
gem5::MipsISA::ISA::processCP0Event
void processCP0Event(BaseCPU *cpu, CP0EventType)
Process a CP0 event.
Definition: isa.cc:588
gem5::MipsISA::ISA::UpdateCP0
@ UpdateCP0
Definition: isa.hh:120
gem5::MipsISA::CoreSpecific::CP0_Config_VI
unsigned CP0_Config_VI
Definition: types.hh:119
gem5::MipsISA::MISCREG_SRS_CONF1
@ MISCREG_SRS_CONF1
Definition: misc.hh:81
gem5::MipsISA::CoreSpecific::CP0_Config3_LPA
bool CP0_Config3_LPA
Definition: types.hh:146
gem5::MipsISA::MISCREG_STATUS
@ MISCREG_STATUS
Definition: misc.hh:96
gem5::MipsISA::ISA::scheduleCP0Update
void scheduleCP0Update(BaseCPU *cpu, Cycles delay=Cycles(0))
Definition: isa.cc:545
gem5::MipsISA::ISA::numVpes
uint8_t numVpes
Definition: isa.hh:65
gem5::MipsISA::CoreSpecific::CP0_Config1_IA
unsigned CP0_Config1_IA
Definition: types.hh:124
gem5::MipsISA::MISCREG_EBASE
@ MISCREG_EBASE
Definition: misc.hh:106
gem5::MipsISA::CoreSpecific::CP0_Config3_SP
bool CP0_Config3_SP
Definition: types.hh:149
pra_constants.hh
gem5::MipsISA::MISCREG_YQMASK
@ MISCREG_YQMASK
Definition: misc.hh:57
gem5::replaceBits
constexpr void replaceBits(T &val, unsigned first, unsigned last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
Definition: bitfield.hh:197
gem5::MipsISA::MISCREG_TC_BIND
@ MISCREG_TC_BIND
Definition: misc.hh:64
gem5::MipsISA::MISCREG_CONFIG2
@ MISCREG_CONFIG2
Definition: misc.hh:110
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::MipsISA::MISCREG_VPE_CONF1
@ MISCREG_VPE_CONF1
Definition: misc.hh:56
gem5::MipsISA::MISCREG_WATCHHI0
@ MISCREG_WATCHHI0
Definition: misc.hh:129
gem5::MipsISA::NumFloatRegs
const int NumFloatRegs
Definition: float.hh:45
gem5::MipsISA::CoreSpecific::CP0_IntCtl_IPPCI
unsigned CP0_IntCtl_IPPCI
Definition: types.hh:107
gem5::MipsISA::CoreSpecific::CP0_Config2_SA
unsigned CP0_Config2_SA
Definition: types.hh:143
gem5::EventManager::schedule
void schedule(Event &event, Tick when)
Definition: eventq.hh:1019
gem5::MipsISA::ISA::numThreads
uint8_t numThreads
Definition: isa.hh:64
gem5::MipsISA::CoreSpecific::CP0_IntCtl_IPTI
unsigned CP0_IntCtl_IPTI
Definition: types.hh:106
gem5::ThreadContext::readIntRegFlat
virtual RegVal readIntRegFlat(RegIndex idx) const =0
Flat register interfaces.
gem5::MipsISA::CoreSpecific::CP0_Config3_TL
bool CP0_Config3_TL
Definition: types.hh:152
gem5::MipsISA::MISCREG_SRSCTL
@ MISCREG_SRSCTL
Definition: misc.hh:98
gem5::MipsISA::ISA::ISA
ISA(const Params &p)
Definition: isa.cc:97
gem5::MipsISA::MISCREG_NUMREGS
@ MISCREG_NUMREGS
Definition: misc.hh:194
gem5::MipsISA::MISCREG_SRS_CONF2
@ MISCREG_SRS_CONF2
Definition: misc.hh:82
gem5::MipsISA::CoreSpecific::CP0_Config1_MD
bool CP0_Config1_MD
Definition: types.hh:129
gem5::MipsISA::MISCREG_CP0_RANDOM
@ MISCREG_CP0_RANDOM
Definition: misc.hh:53
gem5::MipsISA::ISA::miscRegFile
std::vector< std::vector< RegVal > > miscRegFile
Definition: isa.hh:74
gem5::MipsISA::MISCREG_INTCTL
@ MISCREG_INTCTL
Definition: misc.hh:97
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::MipsISA::CoreSpecific::CP0_Config1_M
unsigned CP0_Config1_M
Definition: types.hh:120
gem5::MipsISA::CoreSpecific::CP0_Config1_DA
unsigned CP0_Config1_DA
Definition: types.hh:127
gem5::MipsISA::MISCREG_INDEX
@ MISCREG_INDEX
Definition: misc.hh:48
gem5::MipsISA::MISCREG_TC_CONTEXT
@ MISCREG_TC_CONTEXT
Definition: misc.hh:67
gem5::MipsISA::CoreSpecific::CP0_SrsCtl_HSS
unsigned CP0_SrsCtl_HSS
Definition: types.hh:108
gem5::ArmISA::j
Bitfield< 24 > j
Definition: misc_types.hh:57
gem5::MipsISA::MISCREG_SRS_CONF4
@ MISCREG_SRS_CONF4
Definition: misc.hh:84
gem5::BaseISA::_regClasses
RegClasses _regClasses
Definition: isa.hh:64
gem5::MipsISA::CoreSpecific::CP0_Config2_SU
unsigned CP0_Config2_SU
Definition: types.hh:140
gem5::MipsISA::CoreSpecific::CP0_Config1_DL
unsigned CP0_Config1_DL
Definition: types.hh:126
gem5::MipsISA::i
Bitfield< 2 > i
Definition: pra_constants.hh:279
gem5::MipsISA::CoreSpecific::CP0_Config1_C2
bool CP0_Config1_C2
Definition: types.hh:128
gem5::MipsISA::MISCREG_VPE_SCHEFBACK
@ MISCREG_VPE_SCHEFBACK
Definition: misc.hh:59
bitfield.hh
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::MipsISA::ISA::setRegMask
void setRegMask(int misc_reg, RegVal val, ThreadID tid=0)
Definition: isa.cc:487
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::MipsISA::CoreSpecific::CP0_PerfCtr_M
bool CP0_PerfCtr_M
Definition: types.hh:155
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::MipsISA::MISCREG_TC_STATUS
@ MISCREG_TC_STATUS
Definition: misc.hh:63
gem5::MipsISA::CoreSpecific::CP0_WatchHi_M
bool CP0_WatchHi_M
Definition: types.hh:154
gem5::ThreadContext::setIntRegFlat
virtual void setIntRegFlat(RegIndex idx, RegVal val)=0
gem5::MipsISA::MISCREG_TC_HALT
@ MISCREG_TC_HALT
Definition: misc.hh:66
gem5::MipsISA::MISCREG_BADVADDR
@ MISCREG_BADVADDR
Definition: misc.hh:88
gem5::MipsISA::CoreSpecific::CP0_Config2_TU
unsigned CP0_Config2_TU
Definition: types.hh:136
gem5::MipsISA::ISA::filterCP0Write
RegVal filterCP0Write(int misc_reg, int reg_sel, RegVal val)
This method doesn't need to adjust the Control Register Offset since it has already been done in the ...
Definition: isa.cc:525
gem5::ThreadContext::setFloatRegFlat
virtual void setFloatRegFlat(RegIndex idx, RegVal val)=0
gem5::MipsISA::MISCREG_CONFIG
@ MISCREG_CONFIG
Definition: misc.hh:108
gem5::MipsISA::MISCREG_CONFIG1
@ MISCREG_CONFIG1
Definition: misc.hh:109
gem5::MipsISA::NumIntRegs
const int NumIntRegs
Definition: int.hh:44
gem5::MipsISA::ISA::perVirtProcessor
@ perVirtProcessor
Definition: isa.hh:71
gem5::MipsISA::CoreSpecific::CP0_Config3_VInt
bool CP0_Config3_VInt
Definition: types.hh:148
gem5::MipsISA::CoreSpecific::CP0_Config3_VEIC
bool CP0_Config3_VEIC
Definition: types.hh:147
gem5::MipsISA::ISA::setMiscReg
void setMiscReg(int misc_reg, RegVal val, ThreadID tid=0)
Definition: isa.cc:502
gem5::BaseCPU
Definition: base.hh:107
gem5::MipsISA::CoreSpecific::CP0_Config3_DSPP
bool CP0_Config3_DSPP
Definition: types.hh:145
gem5::MipsISA::MISCREG_TC_SCHEDULE
@ MISCREG_TC_SCHEDULE
Definition: misc.hh:68
gem5::MipsISA::ISA::copyRegsFrom
void copyRegsFrom(ThreadContext *src) override
Definition: isa.cc:171
gem5::ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::MipsISA::CoreSpecific::CP0_Config1_MMU
unsigned CP0_Config1_MMU
Definition: types.hh:121
gem5::MipsISA::ISA::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid=0) const
Definition: isa.cc:447
gem5::BaseCPU::getContext
virtual ThreadContext * getContext(int tn)
Given a thread num get tho thread context for it.
Definition: base.hh:290
gem5::MipsISA::CoreSpecific::CP0_Config2_M
bool CP0_Config2_M
Definition: types.hh:135
gem5::MipsISA::CoreSpecific::CP0_Config1_IS
unsigned CP0_Config1_IS
Definition: types.hh:122
gem5::MipsISA::CoreSpecific::CP0_Config1_WR
bool CP0_Config1_WR
Definition: types.hh:131
gem5::Clocked::clockEdge
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Definition: clocked_object.hh:177
gem5::MipsISA::ISA::miscRegNames
static std::string miscRegNames[MISCREG_NUMREGS]
Definition: isa.hh:133
gem5::MipsISA::ISA::CP0EventType
CP0EventType
Definition: isa.hh:118
float.hh
gem5::MipsISA::MISCREG_PAGEMASK
@ MISCREG_PAGEMASK
Definition: misc.hh:76
gem5::MipsISA::ISA::configCP
void configCP()
Definition: isa.cc:191
gem5::MipsISA::haltThread
void haltThread(TC *tc)
Definition: mt.hh:135
gem5::MipsISA::MISCREG_VPE_CONTROL
@ MISCREG_VPE_CONTROL
Definition: misc.hh:54
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::MipsISA::CoreSpecific::CP0_PRId_ProcessorID
unsigned CP0_PRId_ProcessorID
Definition: types.hh:111
gem5::MipsISA::MISCREG_VPE_SCHEDULE
@ MISCREG_VPE_SCHEDULE
Definition: misc.hh:58
gem5::MipsISA::CoreSpecific
Definition: types.hh:79
gem5::MipsISA::CoreSpecific::CP0_PRId_Revision
unsigned CP0_PRId_Revision
Definition: types.hh:112
gem5::MipsISA::CoreSpecific::CP0_PRId_CompanyOptions
unsigned CP0_PRId_CompanyOptions
Definition: types.hh:109
gem5::MipsISA::MISCREG_MVP_CONF0
@ MISCREG_MVP_CONF0
Definition: misc.hh:50
gem5::MipsISA::MISCREG_VPE_CONF0
@ MISCREG_VPE_CONF0
Definition: misc.hh:55
gem5::MipsISA::ISA::readMiscReg
RegVal readMiscReg(int misc_reg, ThreadID tid=0)
Definition: isa.cc:461
gem5::MipsISA::CoreSpecific::CP0_Config1_IL
unsigned CP0_Config1_IL
Definition: types.hh:123
base.hh
int.hh
gem5::MipsISA::ISA::getVPENum
unsigned getVPENum(ThreadID tid) const
Definition: isa.cc:440
gem5::MipsISA::ISA::perThreadContext
@ perThreadContext
Definition: isa.hh:70
gem5::MipsISA::CoreSpecific::CP0_Config1_PC
bool CP0_Config1_PC
Definition: types.hh:130
gem5::MipsISA::CoreSpecific::CP0_Config_AT
unsigned CP0_Config_AT
Definition: types.hh:116
reg_class.hh
gem5::MipsISA::CoreSpecific::CP0_Config3_MT
bool CP0_Config3_MT
Definition: types.hh:150
gem5::MipsISA::CoreSpecific::CP0_Config_MT
unsigned CP0_Config_MT
Definition: types.hh:118
gem5::MipsISA::CoreSpecific::CP0_EBase_CPUNum
unsigned CP0_EBase_CPUNum
Definition: types.hh:113
gem5::MipsISA::MISCREG_TC_SCHEFBACK
@ MISCREG_TC_SCHEFBACK
Definition: misc.hh:69
gem5::MipsISA::ISA::perProcessor
@ perProcessor
Definition: isa.hh:69
gem5::MipsISA::ISA::updateCPU
void updateCPU(BaseCPU *cpu)
Definition: isa.cc:559
gem5::MipsISA::CoreSpecific::CP0_Config_AR
unsigned CP0_Config_AR
Definition: types.hh:117
gem5::MipsISA::k
Bitfield< 23 > k
Definition: dt_constants.hh:81
gem5::MipsISA::MISCREG_TC_RESTART
@ MISCREG_TC_RESTART
Definition: misc.hh:65
gem5::ThreadContext::getCpuPtr
virtual BaseCPU * getCpuPtr()=0
gem5::MipsISA::MISCREG_DEBUG
@ MISCREG_DEBUG
Definition: misc.hh:144
gem5::MipsISA::MISCREG_LLADDR
@ MISCREG_LLADDR
Definition: misc.hh:118
gem5::MipsISA::CoreSpecific::CP0_Config1_FP
bool CP0_Config1_FP
Definition: types.hh:134
gem5::MipsISA::CoreSpecific::CP0_Config_BE
unsigned CP0_Config_BE
Definition: types.hh:115
gem5::MipsISA::CoreSpecific::CP0_Config2_TS
unsigned CP0_Config2_TS
Definition: types.hh:137
gem5::BaseISA
Definition: isa.hh:54
gem5::EventBase::CPU_Tick_Pri
static const Priority CPU_Tick_Pri
CPU ticks must come after other associated CPU events (such as writebacks).
Definition: eventq.hh:204
gem5::MipsISA::MISCREG_ENTRYLO1
@ MISCREG_ENTRYLO1
Definition: misc.hh:71
gem5::MipsISA::CoreSpecific::CP0_PerfCtr_W
bool CP0_PerfCtr_W
Definition: types.hh:156
gem5::ThreadContext::readFloatRegFlat
virtual RegVal readFloatRegFlat(RegIndex idx) const =0
gem5::MipsISA::ISA::cp0Updated
bool cp0Updated
Definition: isa.hh:115
gem5::MipsISA::ISA::clear
void clear()
Definition: isa.cc:159
gem5::MipsISA::MISCREG_SRS_CONF3
@ MISCREG_SRS_CONF3
Definition: misc.hh:83
gem5::MipsISA::MISCREG_CAUSE
@ MISCREG_CAUSE
Definition: misc.hh:101
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::MipsISA::ISA::Params
MipsISAParams Params
Definition: isa.hh:60
mt_constants.hh
gem5::MipsISA::CoreSpecific::CP0_Config2_SS
unsigned CP0_Config2_SS
Definition: types.hh:141
gem5::MipsISA::MISCREG_PAGEGRAIN
@ MISCREG_PAGEGRAIN
Definition: misc.hh:77
mt.hh
gem5::MipsISA::CoreSpecific::CP0_PRId_CompanyID
unsigned CP0_PRId_CompanyID
Definition: types.hh:110
gem5::MipsISA::MISCREG_CONTEXT
@ MISCREG_CONTEXT
Definition: misc.hh:73
gem5::MipsISA::CoreSpecific::CP0_Config2_TL
unsigned CP0_Config2_TL
Definition: types.hh:138
thread_context.hh
gem5::MipsISA::MISCREG_VPE_OPT
@ MISCREG_VPE_OPT
Definition: misc.hh:60
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::MipsISA::MISCREG_SRS_CONF0
@ MISCREG_SRS_CONF0
Definition: misc.hh:80
gem5::MipsISA::ISA::miscRegFile_WriteMask
std::vector< std::vector< RegVal > > miscRegFile_WriteMask
Definition: isa.hh:75
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::MipsISA::CoreSpecific::CP0_Config1_EP
bool CP0_Config1_EP
Definition: types.hh:133
gem5::ArmISA::status
Bitfield< 5, 0 > status
Definition: misc_types.hh:422
gem5::ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
gem5::MipsISA::CoreSpecific::CP0_Config2_SL
unsigned CP0_Config2_SL
Definition: types.hh:142
gem5::MipsISA::MISCREG_PERFCNT0
@ MISCREG_PERFCNT0
Definition: misc.hh:152
gem5::MipsISA::ISA::setMiscRegNoEffect
void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid=0)
Definition: isa.cc:474

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