gem5  v22.0.0.1
isa.cc
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28 
29 #include "arch/mips/isa.hh"
30 
31 #include "arch/mips/mt.hh"
34 #include "arch/mips/regs/float.hh"
35 #include "arch/mips/regs/int.hh"
36 #include "arch/mips/regs/misc.hh"
37 #include "base/bitfield.hh"
38 #include "cpu/base.hh"
39 #include "cpu/reg_class.hh"
40 #include "cpu/thread_context.hh"
41 #include "debug/FloatRegs.hh"
42 #include "debug/IntRegs.hh"
43 #include "debug/MipsPRA.hh"
44 #include "debug/MiscRegs.hh"
45 #include "params/MipsISA.hh"
46 
47 namespace gem5
48 {
49 
50 namespace MipsISA
51 {
52 
53 std::string
55 {
56  "Index", "MVPControl", "MVPConf0", "MVPConf1", "", "", "", "",
57  "Random", "VPEControl", "VPEConf0", "VPEConf1",
58  "YQMask", "VPESchedule", "VPEScheFBack", "VPEOpt",
59  "EntryLo0", "TCStatus", "TCBind", "TCRestart",
60  "TCHalt", "TCContext", "TCSchedule", "TCScheFBack",
61  "EntryLo1", "", "", "", "", "", "", "",
62  "Context", "ContextConfig", "", "", "", "", "", "",
63  "PageMask", "PageGrain", "", "", "", "", "", "",
64  "Wired", "SRSConf0", "SRCConf1", "SRSConf2",
65  "SRSConf3", "SRSConf4", "", "",
66  "HWREna", "", "", "", "", "", "", "",
67  "BadVAddr", "", "", "", "", "", "", "",
68  "Count", "", "", "", "", "", "", "",
69  "EntryHi", "", "", "", "", "", "", "",
70  "Compare", "", "", "", "", "", "", "",
71  "Status", "IntCtl", "SRSCtl", "SRSMap", "", "", "", "",
72  "Cause", "", "", "", "", "", "", "",
73  "EPC", "", "", "", "", "", "", "",
74  "PRId", "EBase", "", "", "", "", "", "",
75  "Config", "Config1", "Config2", "Config3", "", "", "", "",
76  "LLAddr", "", "", "", "", "", "", "",
77  "WatchLo0", "WatchLo1", "WatchLo2", "WatchLo3",
78  "WatchLo4", "WatchLo5", "WatchLo6", "WatchLo7",
79  "WatchHi0", "WatchHi1", "WatchHi2", "WatchHi3",
80  "WatchHi4", "WatchHi5", "WatchHi6", "WatchHi7",
81  "XCContext64", "", "", "", "", "", "", "",
82  "", "", "", "", "", "", "", "",
83  "", "", "", "", "", "", "", "",
84  "Debug", "TraceControl1", "TraceControl2", "UserTraceData",
85  "TraceBPC", "", "", "",
86  "DEPC", "", "", "", "", "", "", "",
87  "PerfCnt0", "PerfCnt1", "PerfCnt2", "PerfCnt3",
88  "PerfCnt4", "PerfCnt5", "PerfCnt6", "PerfCnt7",
89  "ErrCtl", "", "", "", "", "", "", "",
90  "CacheErr0", "CacheErr1", "CacheErr2", "CacheErr3", "", "", "", "",
91  "TagLo0", "DataLo1", "TagLo2", "DataLo3",
92  "TagLo4", "DataLo5", "TagLo6", "DataLo7",
93  "TagHi0", "DataHi1", "TagHi2", "DataHi3",
94  "TagHi4", "DataHi5", "TagHi6", "DataHi7",
95  "ErrorEPC", "", "", "", "", "", "", "",
96  "DESAVE", "", "", "", "", "", "", "",
97  "LLFlag"
98 };
99 
100 ISA::ISA(const Params &p) : BaseISA(p), numThreads(p.num_threads),
101  numVpes(p.num_vpes)
102 {
103  _regClasses.emplace_back(NumIntRegs, debug::IntRegs);
104  _regClasses.emplace_back(NumFloatRegs, debug::FloatRegs);
105  _regClasses.emplace_back(1, debug::IntRegs); // Not applicable to MIPS.
106  _regClasses.emplace_back(2, debug::IntRegs); // Not applicable to MIPS.
107  _regClasses.emplace_back(1, debug::IntRegs); // Not applicable to MIPS.
108  _regClasses.emplace_back(0, debug::IntRegs); // Not applicable to MIPS.
109  _regClasses.emplace_back(MISCREG_NUMREGS, debug::MiscRegs);
110 
112  bankType.resize(MISCREG_NUMREGS);
113 
114  for (int i = 0; i < MISCREG_NUMREGS; i++) {
115  miscRegFile[i].resize(1);
117  }
118 
120 
121  for (int i = 0; i < MISCREG_NUMREGS; i++) {
122  miscRegFile_WriteMask[i].push_back(0);
123  }
124 
125  // Initialize all Per-VPE regs
126  uint32_t per_vpe_regs[] = { MISCREG_VPE_CONTROL,
134  };
135  uint32_t num_vpe_regs = sizeof(per_vpe_regs) / 4;
136  for (int i = 0; i < num_vpe_regs; i++) {
137  if (numVpes > 1) {
138  miscRegFile[per_vpe_regs[i]].resize(numVpes);
139  }
140  bankType[per_vpe_regs[i]] = perVirtProcessor;
141  }
142 
143  // Initialize all Per-TC regs
144  uint32_t per_tc_regs[] = { MISCREG_STATUS,
150  };
151  uint32_t num_tc_regs = sizeof(per_tc_regs) / 4;
152 
153  for (int i = 0; i < num_tc_regs; i++) {
154  miscRegFile[per_tc_regs[i]].resize(numThreads);
155  bankType[per_tc_regs[i]] = perThreadContext;
156  }
157 
158  clear();
159 }
160 
161 void
163 {
164  for (int i = 0; i < MISCREG_NUMREGS; i++) {
165  for (int j = 0; j < miscRegFile[i].size(); j++)
166  miscRegFile[i][j] = 0;
167 
168  for (int k = 0; k < miscRegFile_WriteMask[i].size(); k++)
169  miscRegFile_WriteMask[i][k] = (long unsigned int)(-1);
170  }
171 }
172 
173 void
175 {
176  // First loop through the integer registers.
177  for (int i = 0; i < NumIntRegs; i++)
178  tc->setIntRegFlat(i, src->readIntRegFlat(i));
179 
180  // Then loop through the floating point registers.
181  for (int i = 0; i < NumFloatRegs; i++)
183 
184  // Copy misc. registers
185  for (int i = 0; i < MISCREG_NUMREGS; i++)
187 
188  // Copy over the PC State
189  tc->pcState(src->pcState());
190 }
191 
192 
193 void
195 {
196  DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n",
198 
199  CoreSpecific cp;
200  panic("CP state must be set before the following code is used");
201 
202  // Do Default CP0 initialization HERE
203 
204  // Do Initialization for MT cores here (eventually use
205  // core_name parameter to toggle this initialization)
206  // ===================================================
207  DPRINTF(MipsPRA, "Initializing CP0 State.... ");
208 
211  procId.coId = cp.CP0_PRId_CompanyID;
212  procId.procId = cp.CP0_PRId_ProcessorID;
213  procId.rev = cp.CP0_PRId_Revision;
215 
216  // Now, create Write Mask for ProcID register
217  RegVal procIDMask = 0; // Read-Only register
218  replaceBits(procIDMask, 32, 0, 0);
219  setRegMask(MISCREG_PRID, procIDMask);
220 
221  // Config
222  ConfigReg cfg = readMiscRegNoEffect(MISCREG_CONFIG);
223  cfg.be = cp.CP0_Config_BE;
224  cfg.at = cp.CP0_Config_AT;
225  cfg.ar = cp.CP0_Config_AR;
226  cfg.mt = cp.CP0_Config_MT;
227  cfg.vi = cp.CP0_Config_VI;
228  cfg.m = 1;
230  // Now, create Write Mask for Config register
231  RegVal cfg_Mask = 0x7FFF0007;
232  replaceBits(cfg_Mask, 32, 0, 0);
233  setRegMask(MISCREG_CONFIG, cfg_Mask);
234 
235  // Config1
236  Config1Reg cfg1 = readMiscRegNoEffect(MISCREG_CONFIG1);
237  cfg1.mmuSize = cp.CP0_Config1_MMU;
238  cfg1.is = cp.CP0_Config1_IS;
239  cfg1.il = cp.CP0_Config1_IL;
240  cfg1.ia = cp.CP0_Config1_IA;
241  cfg1.ds = cp.CP0_Config1_DS;
242  cfg1.dl = cp.CP0_Config1_DL;
243  cfg1.da = cp.CP0_Config1_DA;
244  cfg1.fp = cp.CP0_Config1_FP;
245  cfg1.ep = cp.CP0_Config1_EP;
246  cfg1.wr = cp.CP0_Config1_WR;
247  cfg1.md = cp.CP0_Config1_MD;
248  cfg1.c2 = cp.CP0_Config1_C2;
249  cfg1.pc = cp.CP0_Config1_PC;
250  cfg1.m = cp.CP0_Config1_M;
252  // Now, create Write Mask for Config register
253  RegVal cfg1_Mask = 0; // Read Only Register
254  replaceBits(cfg1_Mask, 32,0 , 0);
255  setRegMask(MISCREG_CONFIG1, cfg1_Mask);
256 
257  // Config2
258  Config2Reg cfg2 = readMiscRegNoEffect(MISCREG_CONFIG2);
259  cfg2.tu = cp.CP0_Config2_TU;
260  cfg2.ts = cp.CP0_Config2_TS;
261  cfg2.tl = cp.CP0_Config2_TL;
262  cfg2.ta = cp.CP0_Config2_TA;
263  cfg2.su = cp.CP0_Config2_SU;
264  cfg2.ss = cp.CP0_Config2_SS;
265  cfg2.sl = cp.CP0_Config2_SL;
266  cfg2.sa = cp.CP0_Config2_SA;
267  cfg2.m = cp.CP0_Config2_M;
269  // Now, create Write Mask for Config register
270  RegVal cfg2_Mask = 0x7000F000; // Read Only Register
271  replaceBits(cfg2_Mask, 32, 0, 0);
272  setRegMask(MISCREG_CONFIG2, cfg2_Mask);
273 
274  // Config3
275  Config3Reg cfg3 = readMiscRegNoEffect(MISCREG_CONFIG3);
276  cfg3.dspp = cp.CP0_Config3_DSPP;
277  cfg3.lpa = cp.CP0_Config3_LPA;
278  cfg3.veic = cp.CP0_Config3_VEIC;
279  cfg3.vint = cp.CP0_Config3_VInt;
280  cfg3.sp = cp.CP0_Config3_SP;
281  cfg3.mt = cp.CP0_Config3_MT;
282  cfg3.sm = cp.CP0_Config3_SM;
283  cfg3.tl = cp.CP0_Config3_TL;
285  // Now, create Write Mask for Config register
286  RegVal cfg3_Mask = 0; // Read Only Register
287  replaceBits(cfg3_Mask, 32,0 , 0);
288  setRegMask(MISCREG_CONFIG3, cfg3_Mask);
289 
290  // EBase - CPUNum
291  EBaseReg eBase = readMiscRegNoEffect(MISCREG_EBASE);
292  eBase.cpuNum = cp.CP0_EBase_CPUNum;
293  replaceBits(eBase, 31, 31, 1);
295  // Now, create Write Mask for Config register
296  RegVal EB_Mask = 0x3FFFF000;// Except Exception Base, the
297  // entire register is read only
298  replaceBits(EB_Mask, 32, 0, 0);
299  setRegMask(MISCREG_EBASE, EB_Mask);
300 
301  // SRS Control - HSS (Highest Shadow Set)
302  SRSCtlReg scsCtl = readMiscRegNoEffect(MISCREG_SRSCTL);
303  scsCtl.hss = cp.CP0_SrsCtl_HSS;
305  // Now, create Write Mask for the SRS Ctl register
306  RegVal SC_Mask = 0x0000F3C0;
307  replaceBits(SC_Mask, 32, 0, 0);
308  setRegMask(MISCREG_SRSCTL, SC_Mask);
309 
310  // IntCtl - IPTI, IPPCI
311  IntCtlReg intCtl = readMiscRegNoEffect(MISCREG_INTCTL);
312  intCtl.ipti = cp.CP0_IntCtl_IPTI;
313  intCtl.ippci = cp.CP0_IntCtl_IPPCI;
315  // Now, create Write Mask for the IntCtl register
316  RegVal IC_Mask = 0x000003E0;
317  replaceBits(IC_Mask, 32, 0, 0);
318  setRegMask(MISCREG_INTCTL, IC_Mask);
319 
320  // Watch Hi - M - FIXME (More than 1 Watch register)
321  WatchHiReg watchHi = readMiscRegNoEffect(MISCREG_WATCHHI0);
322  watchHi.m = cp.CP0_WatchHi_M;
324  // Now, create Write Mask for the IntCtl register
325  RegVal wh_Mask = 0x7FFF0FFF;
326  replaceBits(wh_Mask, 32, 0, 0);
327  setRegMask(MISCREG_WATCHHI0, wh_Mask);
328 
329  // Perf Ctr - M - FIXME (More than 1 PerfCnt Pair)
330  PerfCntCtlReg perfCntCtl = readMiscRegNoEffect(MISCREG_PERFCNT0);
331  perfCntCtl.m = cp.CP0_PerfCtr_M;
332  perfCntCtl.w = cp.CP0_PerfCtr_W;
334  // Now, create Write Mask for the IntCtl register
335  RegVal pc_Mask = 0x00007FF;
336  replaceBits(pc_Mask, 32, 0, 0);
337  setRegMask(MISCREG_PERFCNT0, pc_Mask);
338 
339  // Random
341  // Now, create Write Mask for the IntCtl register
342  RegVal random_Mask = 0;
343  replaceBits(random_Mask, 32, 0, 0);
344  setRegMask(MISCREG_CP0_RANDOM, random_Mask);
345 
346  // PageGrain
347  PageGrainReg pageGrain = readMiscRegNoEffect(MISCREG_PAGEGRAIN);
348  pageGrain.esp = cp.CP0_Config3_SP;
350  // Now, create Write Mask for the IntCtl register
351  RegVal pg_Mask = 0x10000000;
352  replaceBits(pg_Mask, 32, 0, 0);
353  setRegMask(MISCREG_PAGEGRAIN, pg_Mask);
354 
355  // Status
357  // Only CU0 and IE are modified on a reset - everything else needs
358  // to be controlled on a per CPU model basis
359 
360  // Enable CP0 on reset
361  // status.cu0 = 1;
362 
363  // Enable ERL bit on a reset
364  status.erl = 1;
365  // Enable BEV bit on a reset
366  status.bev = 1;
367 
369  // Now, create Write Mask for the Status register
370  RegVal stat_Mask = 0xFF78FF17;
371  replaceBits(stat_Mask, 32, 0, 0);
372  setRegMask(MISCREG_STATUS, stat_Mask);
373 
374 
375  // MVPConf0
376  MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0);
377  mvpConf0.tca = 1;
378  mvpConf0.pvpe = numVpes - 1;
379  mvpConf0.ptc = numThreads - 1;
381 
382  // VPEConf0
383  VPEConf0Reg vpeConf0 = readMiscRegNoEffect(MISCREG_VPE_CONF0);
384  vpeConf0.mvp = 1;
386 
387  // TCBind
388  for (ThreadID tid = 0; tid < numThreads; tid++) {
389  TCBindReg tcBind = readMiscRegNoEffect(MISCREG_TC_BIND, tid);
390  tcBind.curTC = tid;
391  setMiscRegNoEffect(MISCREG_TC_BIND, tcBind, tid);
392  }
393  // TCHalt
394  TCHaltReg tcHalt = readMiscRegNoEffect(MISCREG_TC_HALT);
395  tcHalt.h = 0;
397 
398  // TCStatus
399  // Set TCStatus Activated to 1 for the initial thread that is running
400  TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS);
401  tcStatus.a = 1;
403 
404  // Set Dynamically Allocatable bit to 1 for all other threads
405  for (ThreadID tid = 1; tid < numThreads; tid++) {
406  tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid);
407  tcStatus.da = 1;
408  setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus, tid);
409  }
410 
411 
412  RegVal mask = 0x7FFFFFFF;
413 
414  // Now, create Write Mask for the Index register
415  replaceBits(mask, 32, 0, 0);
417 
418  mask = 0x3FFFFFFF;
419  replaceBits(mask, 32, 0, 0);
422 
423  mask = 0xFF800000;
424  replaceBits(mask, 32, 0, 0);
426 
427  mask = 0x1FFFF800;
428  replaceBits(mask, 32, 0, 0);
430 
431  mask = 0x0;
432  replaceBits(mask, 32, 0, 0);
435 
436  mask = 0x08C00300;
437  replaceBits(mask, 32, 0, 0);
439 
440 }
441 
442 inline unsigned
444 {
445  TCBindReg tcBind = miscRegFile[MISCREG_TC_BIND][tid];
446  return tcBind.curVPE;
447 }
448 
449 RegVal
450 ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
451 {
452  unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
453  ? tid : getVPENum(tid);
454  DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) (%lx).\n",
455  misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
456  miscRegFile[misc_reg][reg_sel]);
457  return miscRegFile[misc_reg][reg_sel];
458 }
459 
460 //@TODO: MIPS MT's register view automatically connects
461 // Status to TCStatus depending on current thread
462 //template <class TC>
463 RegVal
464 ISA::readMiscReg(int misc_reg, ThreadID tid)
465 {
466  unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
467  ? tid : getVPENum(tid);
468  DPRINTF(MipsPRA,
469  "Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n",
470  misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
471  miscRegFile[misc_reg][reg_sel]);
472 
473  return miscRegFile[misc_reg][reg_sel];
474 }
475 
476 void
478 {
479  unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
480  ? tid : getVPENum(tid);
481  DPRINTF(MipsPRA,
482  "[tid:%i] Setting (direct set) CP0 Register:%u "
483  "Select:%u (%s) to %#x.\n",
484  tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
485 
486  miscRegFile[misc_reg][reg_sel] = val;
487 }
488 
489 void
490 ISA::setRegMask(int misc_reg, RegVal val, ThreadID tid)
491 {
492  unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
493  ? tid : getVPENum(tid);
494  DPRINTF(MipsPRA,
495  "[tid:%i] Setting CP0 Register: %u Select: %u (%s) to %#x\n",
496  tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
497  miscRegFile_WriteMask[misc_reg][reg_sel] = val;
498 }
499 
500 // PROGRAMMER'S NOTES:
501 // (1) Some CP0 Registers have fields that cannot
502 // be overwritten. Make sure to handle those particular registers
503 // with care!
504 void
505 ISA::setMiscReg(int misc_reg, RegVal val, ThreadID tid)
506 {
507  int reg_sel = (bankType[misc_reg] == perThreadContext)
508  ? tid : getVPENum(tid);
509 
510  DPRINTF(MipsPRA,
511  "[tid:%i] Setting CP0 Register:%u "
512  "Select:%u (%s) to %#x, with effect.\n",
513  tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
514 
515  RegVal cp0_val = filterCP0Write(misc_reg, reg_sel, val);
516 
517  miscRegFile[misc_reg][reg_sel] = cp0_val;
518 
520 }
521 
527 RegVal
528 ISA::filterCP0Write(int misc_reg, int reg_sel, RegVal val)
529 {
530  RegVal retVal = val;
531 
532  // Mask off read-only regions
533  retVal &= miscRegFile_WriteMask[misc_reg][reg_sel];
534  RegVal curVal = miscRegFile[misc_reg][reg_sel];
535  // Mask off current alue with inverse mask (clear writeable bits)
536  curVal &= (~miscRegFile_WriteMask[misc_reg][reg_sel]);
537  retVal |= curVal; // Combine the two
538  DPRINTF(MipsPRA,
539  "filterCP0Write: Mask: %lx, Inverse Mask: %lx, write Val: %x, "
540  "current val: %lx, written val: %x\n",
541  miscRegFile_WriteMask[misc_reg][reg_sel],
542  ~miscRegFile_WriteMask[misc_reg][reg_sel],
543  val, miscRegFile[misc_reg][reg_sel], retVal);
544  return retVal;
545 }
546 
547 void
548 ISA::scheduleCP0Update(BaseCPU *cpu, Cycles delay)
549 {
550  if (!cp0Updated) {
551  cp0Updated = true;
552 
553  //schedule UPDATE
554  auto cp0_event = new EventFunctionWrapper(
555  [this, cpu]{ processCP0Event(cpu, UpdateCP0); },
556  "Coprocessor-0 event", true, Event::CPU_Tick_Pri);
557  cpu->schedule(cp0_event, cpu->clockEdge(delay));
558  }
559 }
560 
561 void
562 ISA::updateCPU(BaseCPU *cpu)
563 {
565  //
566  // EVALUATE CP0 STATE FOR MIPS MT
567  //
569  MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0);
570  ThreadID num_threads = mvpConf0.ptc + 1;
571 
572  for (ThreadID tid = 0; tid < num_threads; tid++) {
573  TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid);
574  TCHaltReg tcHalt = readMiscRegNoEffect(MISCREG_TC_HALT, tid);
575 
576  //@todo: add vpe/mt check here thru mvpcontrol & vpecontrol regs
577  if (tcHalt.h == 1 || tcStatus.a == 0) {
578  haltThread(cpu->getContext(tid));
579  } else if (tcHalt.h == 0 && tcStatus.a == 1) {
580  restoreThread(cpu->getContext(tid));
581  }
582  }
583 
584  num_threads = mvpConf0.ptc + 1;
585 
586  // Toggle update flag after we finished updating
587  cp0Updated = false;
588 }
589 
590 void
591 ISA::processCP0Event(BaseCPU *cpu, CP0EventType cp0EventType)
592 {
593  switch (cp0EventType)
594  {
595  case UpdateCP0:
596  updateCPU(cpu);
597  break;
598  }
599 }
600 
601 } // namespace MipsISA
602 } // namespace gem5
gem5::MipsISA::MISCREG_ENTRYLO0
@ MISCREG_ENTRYLO0
Definition: misc.hh:62
gem5::MipsISA::procId
Bitfield< 15, 8 > procId
Definition: pra_constants.hh:206
gem5::MipsISA::ISA::bankType
std::vector< BankType > bankType
Definition: isa.hh:77
gem5::ThreadContext::setIntRegFlat
void setIntRegFlat(RegIndex idx, RegVal val)
Definition: thread_context.hh:331
misc.hh
gem5::MipsISA::mask
mask
Definition: pra_constants.hh:73
gem5::MipsISA::CoreSpecific::CP0_Config1_DS
unsigned CP0_Config1_DS
Definition: types.hh:125
isa.hh
gem5::BaseISA::tc
ThreadContext * tc
Definition: isa.hh:65
gem5::MipsISA::CoreSpecific::CP0_Config2_TA
unsigned CP0_Config2_TA
Definition: types.hh:139
gem5::MipsISA::MISCREG_CONFIG3
@ MISCREG_CONFIG3
Definition: misc.hh:111
gem5::MipsISA::restoreThread
void restoreThread(TC *tc)
Definition: mt.hh:155
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::MipsISA::MISCREG_PRID
@ MISCREG_PRID
Definition: misc.hh:105
gem5::MipsISA::CoreSpecific::CP0_Config3_SM
bool CP0_Config3_SM
Definition: types.hh:151
gem5::MipsISA::ISA::processCP0Event
void processCP0Event(BaseCPU *cpu, CP0EventType)
Process a CP0 event.
Definition: isa.cc:591
gem5::MipsISA::ISA::UpdateCP0
@ UpdateCP0
Definition: isa.hh:127
gem5::MipsISA::CoreSpecific::CP0_Config_VI
unsigned CP0_Config_VI
Definition: types.hh:119
gem5::MipsISA::MISCREG_SRS_CONF1
@ MISCREG_SRS_CONF1
Definition: misc.hh:81
gem5::MipsISA::CoreSpecific::CP0_Config3_LPA
bool CP0_Config3_LPA
Definition: types.hh:146
gem5::MipsISA::MISCREG_STATUS
@ MISCREG_STATUS
Definition: misc.hh:96
gem5::MipsISA::ISA::scheduleCP0Update
void scheduleCP0Update(BaseCPU *cpu, Cycles delay=Cycles(0))
Definition: isa.cc:548
gem5::MipsISA::ISA::numVpes
uint8_t numVpes
Definition: isa.hh:66
gem5::MipsISA::CoreSpecific::CP0_Config1_IA
unsigned CP0_Config1_IA
Definition: types.hh:124
gem5::ThreadContext::readIntRegFlat
RegVal readIntRegFlat(RegIndex idx) const
Definition: thread_context.hh:326
gem5::MipsISA::MISCREG_EBASE
@ MISCREG_EBASE
Definition: misc.hh:106
gem5::MipsISA::CoreSpecific::CP0_Config3_SP
bool CP0_Config3_SP
Definition: types.hh:149
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
pra_constants.hh
gem5::MipsISA::MISCREG_YQMASK
@ MISCREG_YQMASK
Definition: misc.hh:57
gem5::replaceBits
constexpr void replaceBits(T &val, unsigned first, unsigned last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
Definition: bitfield.hh:197
gem5::MipsISA::MISCREG_TC_BIND
@ MISCREG_TC_BIND
Definition: misc.hh:64
gem5::MipsISA::MISCREG_CONFIG2
@ MISCREG_CONFIG2
Definition: misc.hh:110
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::MipsISA::MISCREG_VPE_CONF1
@ MISCREG_VPE_CONF1
Definition: misc.hh:56
gem5::MipsISA::MISCREG_WATCHHI0
@ MISCREG_WATCHHI0
Definition: misc.hh:129
gem5::MipsISA::NumFloatRegs
const int NumFloatRegs
Definition: float.hh:45
gem5::MipsISA::CoreSpecific::CP0_IntCtl_IPPCI
unsigned CP0_IntCtl_IPPCI
Definition: types.hh:107
gem5::MipsISA::CoreSpecific::CP0_Config2_SA
unsigned CP0_Config2_SA
Definition: types.hh:143
gem5::MipsISA::ISA::numThreads
uint8_t numThreads
Definition: isa.hh:65
gem5::MipsISA::CoreSpecific::CP0_IntCtl_IPTI
unsigned CP0_IntCtl_IPTI
Definition: types.hh:106
gem5::MipsISA::CoreSpecific::CP0_Config3_TL
bool CP0_Config3_TL
Definition: types.hh:152
gem5::MipsISA::MISCREG_SRSCTL
@ MISCREG_SRSCTL
Definition: misc.hh:98
gem5::MipsISA::ISA::ISA
ISA(const Params &p)
Definition: isa.cc:100
gem5::MipsISA::MISCREG_NUMREGS
@ MISCREG_NUMREGS
Definition: misc.hh:194
gem5::MipsISA::MISCREG_SRS_CONF2
@ MISCREG_SRS_CONF2
Definition: misc.hh:82
gem5::MipsISA::CoreSpecific::CP0_Config1_MD
bool CP0_Config1_MD
Definition: types.hh:129
gem5::MipsISA::MISCREG_CP0_RANDOM
@ MISCREG_CP0_RANDOM
Definition: misc.hh:53
gem5::MipsISA::ISA::miscRegFile
std::vector< std::vector< RegVal > > miscRegFile
Definition: isa.hh:75
gem5::MipsISA::MISCREG_INTCTL
@ MISCREG_INTCTL
Definition: misc.hh:97
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::MipsISA::CoreSpecific::CP0_Config1_M
unsigned CP0_Config1_M
Definition: types.hh:120
gem5::MipsISA::CoreSpecific::CP0_Config1_DA
unsigned CP0_Config1_DA
Definition: types.hh:127
gem5::MipsISA::MISCREG_INDEX
@ MISCREG_INDEX
Definition: misc.hh:48
gem5::MipsISA::MISCREG_TC_CONTEXT
@ MISCREG_TC_CONTEXT
Definition: misc.hh:67
gem5::MipsISA::CoreSpecific::CP0_SrsCtl_HSS
unsigned CP0_SrsCtl_HSS
Definition: types.hh:108
gem5::ArmISA::j
Bitfield< 24 > j
Definition: misc_types.hh:57
gem5::MipsISA::MISCREG_SRS_CONF4
@ MISCREG_SRS_CONF4
Definition: misc.hh:84
gem5::BaseISA::_regClasses
RegClasses _regClasses
Definition: isa.hh:67
gem5::MipsISA::CoreSpecific::CP0_Config2_SU
unsigned CP0_Config2_SU
Definition: types.hh:140
gem5::MipsISA::CoreSpecific::CP0_Config1_DL
unsigned CP0_Config1_DL
Definition: types.hh:126
gem5::MipsISA::i
Bitfield< 2 > i
Definition: pra_constants.hh:279
gem5::MipsISA::CoreSpecific::CP0_Config1_C2
bool CP0_Config1_C2
Definition: types.hh:128
gem5::MipsISA::MISCREG_VPE_SCHEFBACK
@ MISCREG_VPE_SCHEFBACK
Definition: misc.hh:59
bitfield.hh
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::MipsISA::ISA::setRegMask
void setRegMask(int misc_reg, RegVal val, ThreadID tid=0)
Definition: isa.cc:490
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::MipsISA::CoreSpecific::CP0_PerfCtr_M
bool CP0_PerfCtr_M
Definition: types.hh:155
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::MipsISA::MISCREG_TC_STATUS
@ MISCREG_TC_STATUS
Definition: misc.hh:63
gem5::MipsISA::CoreSpecific::CP0_WatchHi_M
bool CP0_WatchHi_M
Definition: types.hh:154
gem5::MipsISA::MISCREG_TC_HALT
@ MISCREG_TC_HALT
Definition: misc.hh:66
gem5::MipsISA::MISCREG_BADVADDR
@ MISCREG_BADVADDR
Definition: misc.hh:88
gem5::MipsISA::CoreSpecific::CP0_Config2_TU
unsigned CP0_Config2_TU
Definition: types.hh:136
gem5::MipsISA::ISA::filterCP0Write
RegVal filterCP0Write(int misc_reg, int reg_sel, RegVal val)
This method doesn't need to adjust the Control Register Offset since it has already been done in the ...
Definition: isa.cc:528
gem5::MipsISA::MISCREG_CONFIG
@ MISCREG_CONFIG
Definition: misc.hh:108
gem5::MipsISA::MISCREG_CONFIG1
@ MISCREG_CONFIG1
Definition: misc.hh:109
gem5::MipsISA::NumIntRegs
const int NumIntRegs
Definition: int.hh:44
gem5::MipsISA::ISA::perVirtProcessor
@ perVirtProcessor
Definition: isa.hh:72
gem5::MipsISA::CoreSpecific::CP0_Config3_VInt
bool CP0_Config3_VInt
Definition: types.hh:148
gem5::MipsISA::CoreSpecific::CP0_Config3_VEIC
bool CP0_Config3_VEIC
Definition: types.hh:147
gem5::MipsISA::ISA::setMiscReg
void setMiscReg(int misc_reg, RegVal val, ThreadID tid=0)
Definition: isa.cc:505
gem5::MipsISA::CoreSpecific::CP0_Config3_DSPP
bool CP0_Config3_DSPP
Definition: types.hh:145
gem5::MipsISA::MISCREG_TC_SCHEDULE
@ MISCREG_TC_SCHEDULE
Definition: misc.hh:68
gem5::MipsISA::ISA::copyRegsFrom
void copyRegsFrom(ThreadContext *src) override
Definition: isa.cc:174
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::MipsISA::CoreSpecific::CP0_Config1_MMU
unsigned CP0_Config1_MMU
Definition: types.hh:121
gem5::MipsISA::ISA::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid=0) const
Definition: isa.cc:450
gem5::MipsISA::CoreSpecific::CP0_Config2_M
bool CP0_Config2_M
Definition: types.hh:135
gem5::ThreadContext::readFloatRegFlat
RegVal readFloatRegFlat(RegIndex idx) const
Definition: thread_context.hh:337
gem5::MipsISA::CoreSpecific::CP0_Config1_IS
unsigned CP0_Config1_IS
Definition: types.hh:122
gem5::MipsISA::CoreSpecific::CP0_Config1_WR
bool CP0_Config1_WR
Definition: types.hh:131
gem5::MipsISA::ISA::miscRegNames
static std::string miscRegNames[MISCREG_NUMREGS]
Definition: isa.hh:140
gem5::MipsISA::ISA::CP0EventType
CP0EventType
Definition: isa.hh:125
float.hh
gem5::MipsISA::MISCREG_PAGEMASK
@ MISCREG_PAGEMASK
Definition: misc.hh:76
gem5::MipsISA::ISA::configCP
void configCP()
Definition: isa.cc:194
gem5::MipsISA::haltThread
void haltThread(TC *tc)
Definition: mt.hh:136
gem5::MipsISA::MISCREG_VPE_CONTROL
@ MISCREG_VPE_CONTROL
Definition: misc.hh:54
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::MipsISA::CoreSpecific::CP0_PRId_ProcessorID
unsigned CP0_PRId_ProcessorID
Definition: types.hh:111
gem5::MipsISA::MISCREG_VPE_SCHEDULE
@ MISCREG_VPE_SCHEDULE
Definition: misc.hh:58
gem5::MipsISA::CoreSpecific
Definition: types.hh:79
gem5::MipsISA::CoreSpecific::CP0_PRId_Revision
unsigned CP0_PRId_Revision
Definition: types.hh:112
gem5::MipsISA::CoreSpecific::CP0_PRId_CompanyOptions
unsigned CP0_PRId_CompanyOptions
Definition: types.hh:109
gem5::MipsISA::MISCREG_MVP_CONF0
@ MISCREG_MVP_CONF0
Definition: misc.hh:50
gem5::MipsISA::MISCREG_VPE_CONF0
@ MISCREG_VPE_CONF0
Definition: misc.hh:55
gem5::MipsISA::ISA::readMiscReg
RegVal readMiscReg(int misc_reg, ThreadID tid=0)
Definition: isa.cc:464
gem5::MipsISA::CoreSpecific::CP0_Config1_IL
unsigned CP0_Config1_IL
Definition: types.hh:123
base.hh
int.hh
gem5::MipsISA::ISA::getVPENum
unsigned getVPENum(ThreadID tid) const
Definition: isa.cc:443
gem5::MipsISA::ISA::perThreadContext
@ perThreadContext
Definition: isa.hh:71
gem5::MipsISA::CoreSpecific::CP0_Config1_PC
bool CP0_Config1_PC
Definition: types.hh:130
gem5::MipsISA::CoreSpecific::CP0_Config_AT
unsigned CP0_Config_AT
Definition: types.hh:116
reg_class.hh
gem5::MipsISA::CoreSpecific::CP0_Config3_MT
bool CP0_Config3_MT
Definition: types.hh:150
gem5::MipsISA::CoreSpecific::CP0_Config_MT
unsigned CP0_Config_MT
Definition: types.hh:118
gem5::MipsISA::CoreSpecific::CP0_EBase_CPUNum
unsigned CP0_EBase_CPUNum
Definition: types.hh:113
gem5::MipsISA::MISCREG_TC_SCHEFBACK
@ MISCREG_TC_SCHEFBACK
Definition: misc.hh:69
gem5::MipsISA::ISA::perProcessor
@ perProcessor
Definition: isa.hh:70
gem5::MipsISA::ISA::updateCPU
void updateCPU(BaseCPU *cpu)
Definition: isa.cc:562
gem5::MipsISA::CoreSpecific::CP0_Config_AR
unsigned CP0_Config_AR
Definition: types.hh:117
gem5::MipsISA::k
Bitfield< 23 > k
Definition: dt_constants.hh:81
gem5::MipsISA::MISCREG_TC_RESTART
@ MISCREG_TC_RESTART
Definition: misc.hh:65
gem5::ThreadContext::getCpuPtr
virtual BaseCPU * getCpuPtr()=0
gem5::MipsISA::MISCREG_DEBUG
@ MISCREG_DEBUG
Definition: misc.hh:144
gem5::MipsISA::MISCREG_LLADDR
@ MISCREG_LLADDR
Definition: misc.hh:118
gem5::MipsISA::CoreSpecific::CP0_Config1_FP
bool CP0_Config1_FP
Definition: types.hh:134
gem5::MipsISA::CoreSpecific::CP0_Config_BE
unsigned CP0_Config_BE
Definition: types.hh:115
gem5::MipsISA::CoreSpecific::CP0_Config2_TS
unsigned CP0_Config2_TS
Definition: types.hh:137
gem5::BaseISA
Definition: isa.hh:57
gem5::EventBase::CPU_Tick_Pri
static const Priority CPU_Tick_Pri
CPU ticks must come after other associated CPU events (such as writebacks).
Definition: eventq.hh:204
gem5::MipsISA::MISCREG_ENTRYLO1
@ MISCREG_ENTRYLO1
Definition: misc.hh:71
gem5::MipsISA::CoreSpecific::CP0_PerfCtr_W
bool CP0_PerfCtr_W
Definition: types.hh:156
gem5::MipsISA::ISA::cp0Updated
bool cp0Updated
Definition: isa.hh:122
gem5::MipsISA::ISA::clear
void clear()
Definition: isa.cc:162
gem5::MipsISA::MISCREG_SRS_CONF3
@ MISCREG_SRS_CONF3
Definition: misc.hh:83
gem5::MipsISA::MISCREG_CAUSE
@ MISCREG_CAUSE
Definition: misc.hh:101
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::MipsISA::ISA::Params
MipsISAParams Params
Definition: isa.hh:61
mt_constants.hh
gem5::MipsISA::CoreSpecific::CP0_Config2_SS
unsigned CP0_Config2_SS
Definition: types.hh:141
gem5::MipsISA::MISCREG_PAGEGRAIN
@ MISCREG_PAGEGRAIN
Definition: misc.hh:77
mt.hh
gem5::MipsISA::CoreSpecific::CP0_PRId_CompanyID
unsigned CP0_PRId_CompanyID
Definition: types.hh:110
gem5::MipsISA::MISCREG_CONTEXT
@ MISCREG_CONTEXT
Definition: misc.hh:73
gem5::MipsISA::CoreSpecific::CP0_Config2_TL
unsigned CP0_Config2_TL
Definition: types.hh:138
thread_context.hh
gem5::MipsISA::MISCREG_VPE_OPT
@ MISCREG_VPE_OPT
Definition: misc.hh:60
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:235
gem5::MipsISA::MISCREG_SRS_CONF0
@ MISCREG_SRS_CONF0
Definition: misc.hh:80
gem5::MipsISA::ISA::miscRegFile_WriteMask
std::vector< std::vector< RegVal > > miscRegFile_WriteMask
Definition: isa.hh:76
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::MipsISA::CoreSpecific::CP0_Config1_EP
bool CP0_Config1_EP
Definition: types.hh:133
gem5::ArmISA::status
Bitfield< 5, 0 > status
Definition: misc_types.hh:423
gem5::ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
gem5::MipsISA::CoreSpecific::CP0_Config2_SL
unsigned CP0_Config2_SL
Definition: types.hh:142
gem5::MipsISA::MISCREG_PERFCNT0
@ MISCREG_PERFCNT0
Definition: misc.hh:152
gem5::MipsISA::ISA::setMiscRegNoEffect
void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid=0)
Definition: isa.cc:477
gem5::ThreadContext::setFloatRegFlat
void setFloatRegFlat(RegIndex idx, RegVal val)
Definition: thread_context.hh:342

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