gem5  v22.1.0.0
isa.cc
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28 
29 #include "arch/mips/isa.hh"
30 
31 #include "arch/mips/mt.hh"
34 #include "arch/mips/regs/float.hh"
35 #include "arch/mips/regs/int.hh"
36 #include "arch/mips/regs/misc.hh"
37 #include "base/bitfield.hh"
38 #include "cpu/base.hh"
39 #include "cpu/reg_class.hh"
40 #include "cpu/thread_context.hh"
41 #include "debug/MipsPRA.hh"
42 #include "params/MipsISA.hh"
43 
44 namespace gem5
45 {
46 
47 namespace MipsISA
48 {
49 
50 std::string
52 {
53  "Index", "MVPControl", "MVPConf0", "MVPConf1", "", "", "", "",
54  "Random", "VPEControl", "VPEConf0", "VPEConf1",
55  "YQMask", "VPESchedule", "VPEScheFBack", "VPEOpt",
56  "EntryLo0", "TCStatus", "TCBind", "TCRestart",
57  "TCHalt", "TCContext", "TCSchedule", "TCScheFBack",
58  "EntryLo1", "", "", "", "", "", "", "",
59  "Context", "ContextConfig", "", "", "", "", "", "",
60  "PageMask", "PageGrain", "", "", "", "", "", "",
61  "Wired", "SRSConf0", "SRCConf1", "SRSConf2",
62  "SRSConf3", "SRSConf4", "", "",
63  "HWREna", "", "", "", "", "", "", "",
64  "BadVAddr", "", "", "", "", "", "", "",
65  "Count", "", "", "", "", "", "", "",
66  "EntryHi", "", "", "", "", "", "", "",
67  "Compare", "", "", "", "", "", "", "",
68  "Status", "IntCtl", "SRSCtl", "SRSMap", "", "", "", "",
69  "Cause", "", "", "", "", "", "", "",
70  "EPC", "", "", "", "", "", "", "",
71  "PRId", "EBase", "", "", "", "", "", "",
72  "Config", "Config1", "Config2", "Config3", "", "", "", "",
73  "LLAddr", "", "", "", "", "", "", "",
74  "WatchLo0", "WatchLo1", "WatchLo2", "WatchLo3",
75  "WatchLo4", "WatchLo5", "WatchLo6", "WatchLo7",
76  "WatchHi0", "WatchHi1", "WatchHi2", "WatchHi3",
77  "WatchHi4", "WatchHi5", "WatchHi6", "WatchHi7",
78  "XCContext64", "", "", "", "", "", "", "",
79  "", "", "", "", "", "", "", "",
80  "", "", "", "", "", "", "", "",
81  "Debug", "TraceControl1", "TraceControl2", "UserTraceData",
82  "TraceBPC", "", "", "",
83  "DEPC", "", "", "", "", "", "", "",
84  "PerfCnt0", "PerfCnt1", "PerfCnt2", "PerfCnt3",
85  "PerfCnt4", "PerfCnt5", "PerfCnt6", "PerfCnt7",
86  "ErrCtl", "", "", "", "", "", "", "",
87  "CacheErr0", "CacheErr1", "CacheErr2", "CacheErr3", "", "", "", "",
88  "TagLo0", "DataLo1", "TagLo2", "DataLo3",
89  "TagLo4", "DataLo5", "TagLo6", "DataLo7",
90  "TagHi0", "DataHi1", "TagHi2", "DataHi3",
91  "TagHi4", "DataHi5", "TagHi6", "DataHi7",
92  "ErrorEPC", "", "", "", "", "", "", "",
93  "DESAVE", "", "", "", "", "", "", "",
94  "LLFlag"
95 };
96 
97 namespace
98 {
99 
100 /* Not applicable to MIPS. */
101 constexpr RegClass vecRegClass(VecRegClass, VecRegClassName, 1,
102  debug::IntRegs);
103 constexpr RegClass vecElemClass(VecElemClass, VecElemClassName, 2,
104  debug::IntRegs);
106  debug::IntRegs);
107 constexpr RegClass ccRegClass(CCRegClass, CCRegClassName, 0, debug::IntRegs);
108 
109 } // anonymous namespace
110 
111 ISA::ISA(const Params &p) : BaseISA(p), numThreads(p.num_threads),
112  numVpes(p.num_vpes)
113 {
114  _regClasses.push_back(&intRegClass);
115  _regClasses.push_back(&floatRegClass);
116  _regClasses.push_back(&vecRegClass);
117  _regClasses.push_back(&vecElemClass);
118  _regClasses.push_back(&vecPredRegClass);
119  _regClasses.push_back(&ccRegClass);
120  _regClasses.push_back(&miscRegClass);
121 
123  bankType.resize(misc_reg::NumRegs);
124 
125  for (int i = 0; i < misc_reg::NumRegs; i++) {
126  miscRegFile[i].resize(1);
128  }
129 
131 
132  for (int i = 0; i < misc_reg::NumRegs; i++) {
133  miscRegFile_WriteMask[i].push_back(0);
134  }
135 
136  // Initialize all Per-VPE regs
137  uint32_t per_vpe_regs[] = { misc_reg::VpeControl,
145  };
146  uint32_t num_vpe_regs = sizeof(per_vpe_regs) / 4;
147  for (int i = 0; i < num_vpe_regs; i++) {
148  if (numVpes > 1) {
149  miscRegFile[per_vpe_regs[i]].resize(numVpes);
150  }
151  bankType[per_vpe_regs[i]] = perVirtProcessor;
152  }
153 
154  // Initialize all Per-TC regs
155  uint32_t per_tc_regs[] = { misc_reg::Status,
161  };
162  uint32_t num_tc_regs = sizeof(per_tc_regs) / 4;
163 
164  for (int i = 0; i < num_tc_regs; i++) {
165  miscRegFile[per_tc_regs[i]].resize(numThreads);
166  bankType[per_tc_regs[i]] = perThreadContext;
167  }
168 
169  clear();
170 }
171 
172 void
174 {
175  for (int i = 0; i < misc_reg::NumRegs; i++) {
176  for (int j = 0; j < miscRegFile[i].size(); j++)
177  miscRegFile[i][j] = 0;
178 
179  for (int k = 0; k < miscRegFile_WriteMask[i].size(); k++)
180  miscRegFile_WriteMask[i][k] = (long unsigned int)(-1);
181  }
182 }
183 
184 void
186 {
187  // First loop through the integer registers.
188  for (auto &id: intRegClass)
189  tc->setReg(id, src->getReg(id));
190 
191  // Then loop through the floating point registers.
192  for (auto &id: floatRegClass)
193  tc->setReg(id, src->getReg(id));
194 
195  // Copy misc. registers
196  for (int i = 0; i < misc_reg::NumRegs; i++)
198 
199  // Copy over the PC State
200  tc->pcState(src->pcState());
201 }
202 
203 
204 void
206 {
207  DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n",
209 
210  CoreSpecific cp;
211  panic("CP state must be set before the following code is used");
212 
213  // Do Default CP0 initialization HERE
214 
215  // Do Initialization for MT cores here (eventually use
216  // core_name parameter to toggle this initialization)
217  // ===================================================
218  DPRINTF(MipsPRA, "Initializing CP0 State.... ");
219 
222  procId.coId = cp.CP0_PRId_CompanyID;
223  procId.procId = cp.CP0_PRId_ProcessorID;
224  procId.rev = cp.CP0_PRId_Revision;
226 
227  // Now, create Write Mask for ProcID register
228  RegVal procIDMask = 0; // Read-Only register
229  replaceBits(procIDMask, 32, 0, 0);
230  setRegMask(misc_reg::Prid, procIDMask);
231 
232  // Config
233  ConfigReg cfg = readMiscRegNoEffect(misc_reg::Config);
234  cfg.be = cp.CP0_Config_BE;
235  cfg.at = cp.CP0_Config_AT;
236  cfg.ar = cp.CP0_Config_AR;
237  cfg.mt = cp.CP0_Config_MT;
238  cfg.vi = cp.CP0_Config_VI;
239  cfg.m = 1;
241  // Now, create Write Mask for Config register
242  RegVal cfg_Mask = 0x7FFF0007;
243  replaceBits(cfg_Mask, 32, 0, 0);
244  setRegMask(misc_reg::Config, cfg_Mask);
245 
246  // Config1
247  Config1Reg cfg1 = readMiscRegNoEffect(misc_reg::Config1);
248  cfg1.mmuSize = cp.CP0_Config1_MMU;
249  cfg1.is = cp.CP0_Config1_IS;
250  cfg1.il = cp.CP0_Config1_IL;
251  cfg1.ia = cp.CP0_Config1_IA;
252  cfg1.ds = cp.CP0_Config1_DS;
253  cfg1.dl = cp.CP0_Config1_DL;
254  cfg1.da = cp.CP0_Config1_DA;
255  cfg1.fp = cp.CP0_Config1_FP;
256  cfg1.ep = cp.CP0_Config1_EP;
257  cfg1.wr = cp.CP0_Config1_WR;
258  cfg1.md = cp.CP0_Config1_MD;
259  cfg1.c2 = cp.CP0_Config1_C2;
260  cfg1.pc = cp.CP0_Config1_PC;
261  cfg1.m = cp.CP0_Config1_M;
263  // Now, create Write Mask for Config register
264  RegVal cfg1_Mask = 0; // Read Only Register
265  replaceBits(cfg1_Mask, 32,0 , 0);
266  setRegMask(misc_reg::Config1, cfg1_Mask);
267 
268  // Config2
269  Config2Reg cfg2 = readMiscRegNoEffect(misc_reg::Config2);
270  cfg2.tu = cp.CP0_Config2_TU;
271  cfg2.ts = cp.CP0_Config2_TS;
272  cfg2.tl = cp.CP0_Config2_TL;
273  cfg2.ta = cp.CP0_Config2_TA;
274  cfg2.su = cp.CP0_Config2_SU;
275  cfg2.ss = cp.CP0_Config2_SS;
276  cfg2.sl = cp.CP0_Config2_SL;
277  cfg2.sa = cp.CP0_Config2_SA;
278  cfg2.m = cp.CP0_Config2_M;
280  // Now, create Write Mask for Config register
281  RegVal cfg2_Mask = 0x7000F000; // Read Only Register
282  replaceBits(cfg2_Mask, 32, 0, 0);
283  setRegMask(misc_reg::Config2, cfg2_Mask);
284 
285  // Config3
286  Config3Reg cfg3 = readMiscRegNoEffect(misc_reg::Config3);
287  cfg3.dspp = cp.CP0_Config3_DSPP;
288  cfg3.lpa = cp.CP0_Config3_LPA;
289  cfg3.veic = cp.CP0_Config3_VEIC;
290  cfg3.vint = cp.CP0_Config3_VInt;
291  cfg3.sp = cp.CP0_Config3_SP;
292  cfg3.mt = cp.CP0_Config3_MT;
293  cfg3.sm = cp.CP0_Config3_SM;
294  cfg3.tl = cp.CP0_Config3_TL;
296  // Now, create Write Mask for Config register
297  RegVal cfg3_Mask = 0; // Read Only Register
298  replaceBits(cfg3_Mask, 32,0 , 0);
299  setRegMask(misc_reg::Config3, cfg3_Mask);
300 
301  // EBase - CPUNum
302  EBaseReg eBase = readMiscRegNoEffect(misc_reg::Ebase);
303  eBase.cpuNum = cp.CP0_EBase_CPUNum;
304  replaceBits(eBase, 31, 31, 1);
306  // Now, create Write Mask for Config register
307  RegVal EB_Mask = 0x3FFFF000;// Except Exception Base, the
308  // entire register is read only
309  replaceBits(EB_Mask, 32, 0, 0);
310  setRegMask(misc_reg::Ebase, EB_Mask);
311 
312  // SRS Control - HSS (Highest Shadow Set)
313  SRSCtlReg scsCtl = readMiscRegNoEffect(misc_reg::Srsctl);
314  scsCtl.hss = cp.CP0_SrsCtl_HSS;
316  // Now, create Write Mask for the SRS Ctl register
317  RegVal SC_Mask = 0x0000F3C0;
318  replaceBits(SC_Mask, 32, 0, 0);
319  setRegMask(misc_reg::Srsctl, SC_Mask);
320 
321  // IntCtl - IPTI, IPPCI
322  IntCtlReg intCtl = readMiscRegNoEffect(misc_reg::Intctl);
323  intCtl.ipti = cp.CP0_IntCtl_IPTI;
324  intCtl.ippci = cp.CP0_IntCtl_IPPCI;
326  // Now, create Write Mask for the IntCtl register
327  RegVal IC_Mask = 0x000003E0;
328  replaceBits(IC_Mask, 32, 0, 0);
329  setRegMask(misc_reg::Intctl, IC_Mask);
330 
331  // Watch Hi - M - FIXME (More than 1 Watch register)
332  WatchHiReg watchHi = readMiscRegNoEffect(misc_reg::Watchhi0);
333  watchHi.m = cp.CP0_WatchHi_M;
335  // Now, create Write Mask for the IntCtl register
336  RegVal wh_Mask = 0x7FFF0FFF;
337  replaceBits(wh_Mask, 32, 0, 0);
338  setRegMask(misc_reg::Watchhi0, wh_Mask);
339 
340  // Perf Ctr - M - FIXME (More than 1 PerfCnt Pair)
341  PerfCntCtlReg perfCntCtl = readMiscRegNoEffect(misc_reg::Perfcnt0);
342  perfCntCtl.m = cp.CP0_PerfCtr_M;
343  perfCntCtl.w = cp.CP0_PerfCtr_W;
345  // Now, create Write Mask for the IntCtl register
346  RegVal pc_Mask = 0x00007FF;
347  replaceBits(pc_Mask, 32, 0, 0);
348  setRegMask(misc_reg::Perfcnt0, pc_Mask);
349 
350  // Random
352  // Now, create Write Mask for the IntCtl register
353  RegVal random_Mask = 0;
354  replaceBits(random_Mask, 32, 0, 0);
355  setRegMask(misc_reg::Cp0Random, random_Mask);
356 
357  // PageGrain
358  PageGrainReg pageGrain = readMiscRegNoEffect(misc_reg::Pagegrain);
359  pageGrain.esp = cp.CP0_Config3_SP;
361  // Now, create Write Mask for the IntCtl register
362  RegVal pg_Mask = 0x10000000;
363  replaceBits(pg_Mask, 32, 0, 0);
365 
366  // Status
368  // Only CU0 and IE are modified on a reset - everything else needs
369  // to be controlled on a per CPU model basis
370 
371  // Enable CP0 on reset
372  // status.cu0 = 1;
373 
374  // Enable ERL bit on a reset
375  status.erl = 1;
376  // Enable BEV bit on a reset
377  status.bev = 1;
378 
380  // Now, create Write Mask for the Status register
381  RegVal stat_Mask = 0xFF78FF17;
382  replaceBits(stat_Mask, 32, 0, 0);
383  setRegMask(misc_reg::Status, stat_Mask);
384 
385 
386  // MVPConf0
387  MVPConf0Reg mvpConf0 = readMiscRegNoEffect(misc_reg::MvpConf0);
388  mvpConf0.tca = 1;
389  mvpConf0.pvpe = numVpes - 1;
390  mvpConf0.ptc = numThreads - 1;
392 
393  // VPEConf0
394  VPEConf0Reg vpeConf0 = readMiscRegNoEffect(misc_reg::VpeConf0);
395  vpeConf0.mvp = 1;
397 
398  // TCBind
399  for (ThreadID tid = 0; tid < numThreads; tid++) {
400  TCBindReg tcBind = readMiscRegNoEffect(misc_reg::TcBind, tid);
401  tcBind.curTC = tid;
402  setMiscRegNoEffect(misc_reg::TcBind, tcBind, tid);
403  }
404  // TCHalt
405  TCHaltReg tcHalt = readMiscRegNoEffect(misc_reg::TcHalt);
406  tcHalt.h = 0;
408 
409  // TCStatus
410  // Set TCStatus Activated to 1 for the initial thread that is running
411  TCStatusReg tcStatus = readMiscRegNoEffect(misc_reg::TcStatus);
412  tcStatus.a = 1;
414 
415  // Set Dynamically Allocatable bit to 1 for all other threads
416  for (ThreadID tid = 1; tid < numThreads; tid++) {
417  tcStatus = readMiscRegNoEffect(misc_reg::TcStatus, tid);
418  tcStatus.da = 1;
419  setMiscRegNoEffect(misc_reg::TcStatus, tcStatus, tid);
420  }
421 
422 
423  RegVal mask = 0x7FFFFFFF;
424 
425  // Now, create Write Mask for the Index register
426  replaceBits(mask, 32, 0, 0);
428 
429  mask = 0x3FFFFFFF;
430  replaceBits(mask, 32, 0, 0);
433 
434  mask = 0xFF800000;
435  replaceBits(mask, 32, 0, 0);
437 
438  mask = 0x1FFFF800;
439  replaceBits(mask, 32, 0, 0);
441 
442  mask = 0x0;
443  replaceBits(mask, 32, 0, 0);
446 
447  mask = 0x08C00300;
448  replaceBits(mask, 32, 0, 0);
450 
451 }
452 
453 inline unsigned
455 {
456  TCBindReg tcBind = miscRegFile[misc_reg::TcBind][tid];
457  return tcBind.curVPE;
458 }
459 
460 RegVal
462 {
463  unsigned reg_sel = (bankType[idx] == perThreadContext)
464  ? tid : getVPENum(tid);
465  DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) (%lx).\n",
466  idx / 8, idx % 8, miscRegNames[idx], miscRegFile[idx][reg_sel]);
467  return miscRegFile[idx][reg_sel];
468 }
469 
470 //@TODO: MIPS MT's register view automatically connects
471 // Status to TCStatus depending on current thread
472 //template <class TC>
473 RegVal
475 {
476  unsigned reg_sel = (bankType[idx] == perThreadContext)
477  ? tid : getVPENum(tid);
478  DPRINTF(MipsPRA,
479  "Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n",
480  idx / 8, idx % 8, miscRegNames[idx], miscRegFile[idx][reg_sel]);
481 
482  return miscRegFile[idx][reg_sel];
483 }
484 
485 void
487 {
488  unsigned reg_sel = (bankType[idx] == perThreadContext)
489  ? tid : getVPENum(tid);
490  DPRINTF(MipsPRA,
491  "[tid:%i] Setting (direct set) CP0 Register:%u "
492  "Select:%u (%s) to %#x.\n",
493  tid, idx / 8, idx % 8, miscRegNames[idx], val);
494 
495  miscRegFile[idx][reg_sel] = val;
496 }
497 
498 void
500 {
501  unsigned reg_sel = (bankType[idx] == perThreadContext)
502  ? tid : getVPENum(tid);
503  DPRINTF(MipsPRA,
504  "[tid:%i] Setting CP0 Register: %u Select: %u (%s) to %#x\n",
505  tid, idx / 8, idx % 8, miscRegNames[idx], val);
506  miscRegFile_WriteMask[idx][reg_sel] = val;
507 }
508 
509 // PROGRAMMER'S NOTES:
510 // (1) Some CP0 Registers have fields that cannot
511 // be overwritten. Make sure to handle those particular registers
512 // with care!
513 void
515 {
516  int reg_sel = (bankType[idx] == perThreadContext)
517  ? tid : getVPENum(tid);
518 
519  DPRINTF(MipsPRA,
520  "[tid:%i] Setting CP0 Register:%u "
521  "Select:%u (%s) to %#x, with effect.\n",
522  tid, idx / 8, idx % 8, miscRegNames[idx], val);
523 
524  RegVal cp0_val = filterCP0Write(idx, reg_sel, val);
525 
526  miscRegFile[idx][reg_sel] = cp0_val;
527 
529 }
530 
536 RegVal
538 {
539  RegVal retVal = val;
540 
541  // Mask off read-only regions
542  retVal &= miscRegFile_WriteMask[idx][reg_sel];
543  RegVal curVal = miscRegFile[idx][reg_sel];
544  // Mask off current alue with inverse mask (clear writeable bits)
545  curVal &= (~miscRegFile_WriteMask[idx][reg_sel]);
546  retVal |= curVal; // Combine the two
547  DPRINTF(MipsPRA,
548  "filterCP0Write: Mask: %lx, Inverse Mask: %lx, write Val: %x, "
549  "current val: %lx, written val: %x\n",
550  miscRegFile_WriteMask[idx][reg_sel],
551  ~miscRegFile_WriteMask[idx][reg_sel],
552  val, miscRegFile[idx][reg_sel], retVal);
553  return retVal;
554 }
555 
556 void
558 {
559  if (!cp0Updated) {
560  cp0Updated = true;
561 
562  //schedule UPDATE
563  auto cp0_event = new EventFunctionWrapper(
564  [this, cpu]{ processCP0Event(cpu, UpdateCP0); },
565  "Coprocessor-0 event", true, Event::CPU_Tick_Pri);
566  cpu->schedule(cp0_event, cpu->clockEdge(delay));
567  }
568 }
569 
570 void
572 {
574  //
575  // EVALUATE CP0 STATE FOR MIPS MT
576  //
578  MVPConf0Reg mvpConf0 = readMiscRegNoEffect(misc_reg::MvpConf0);
579  ThreadID num_threads = mvpConf0.ptc + 1;
580 
581  for (ThreadID tid = 0; tid < num_threads; tid++) {
582  TCStatusReg tcStatus = readMiscRegNoEffect(misc_reg::TcStatus, tid);
583  TCHaltReg tcHalt = readMiscRegNoEffect(misc_reg::TcHalt, tid);
584 
585  //@todo: add vpe/mt check here thru mvpcontrol & vpecontrol regs
586  if (tcHalt.h == 1 || tcStatus.a == 0) {
587  haltThread(cpu->getContext(tid));
588  } else if (tcHalt.h == 0 && tcStatus.a == 1) {
589  restoreThread(cpu->getContext(tid));
590  }
591  }
592 
593  num_threads = mvpConf0.ptc + 1;
594 
595  // Toggle update flag after we finished updating
596  cp0Updated = false;
597 }
598 
599 void
601 {
602  switch (cp0EventType)
603  {
604  case UpdateCP0:
605  updateCPU(cpu);
606  break;
607  }
608 }
609 
610 } // namespace MipsISA
611 } // namespace gem5
#define DPRINTF(x,...)
Definition: trace.hh:186
virtual ThreadContext * getContext(int tn)
Given a thread num get tho thread context for it.
Definition: base.hh:284
ThreadContext * tc
Definition: isa.hh:65
RegClasses _regClasses
Definition: isa.hh:67
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:79
void processCP0Event(BaseCPU *cpu, CP0EventType)
Process a CP0 event.
Definition: isa.cc:600
ISA(const Params &p)
Definition: isa.cc:111
void setMiscReg(RegIndex idx, RegVal val, ThreadID tid)
Definition: isa.cc:514
std::vector< std::vector< RegVal > > miscRegFile
Definition: isa.hh:75
void updateCPU(BaseCPU *cpu)
Definition: isa.cc:571
RegVal readMiscRegNoEffect(RegIndex idx, ThreadID tid) const
Definition: isa.cc:461
bool cp0Updated
Definition: isa.hh:141
RegVal readMiscReg(RegIndex idx, ThreadID tid)
Definition: isa.cc:474
unsigned getVPENum(ThreadID tid) const
Definition: isa.cc:454
void setRegMask(RegIndex idx, RegVal val, ThreadID tid=0)
Definition: isa.cc:499
void setMiscRegNoEffect(RegIndex idx, RegVal val, ThreadID tid)
Definition: isa.cc:486
std::vector< BankType > bankType
Definition: isa.hh:77
void scheduleCP0Update(BaseCPU *cpu, Cycles delay=Cycles(0))
Definition: isa.cc:557
RegVal filterCP0Write(RegIndex idx, int reg_sel, RegVal val)
This method doesn't need to adjust the Control Register Offset since it has already been done in the ...
Definition: isa.cc:537
std::vector< std::vector< RegVal > > miscRegFile_WriteMask
Definition: isa.hh:76
void copyRegsFrom(ThreadContext *src) override
Definition: isa.cc:185
static std::string miscRegNames[misc_reg::NumRegs]
Definition: isa.hh:159
void configCP()
Definition: isa.cc:205
uint8_t numThreads
Definition: isa.hh:65
uint8_t numVpes
Definition: isa.hh:66
@ perVirtProcessor
Definition: isa.hh:72
@ perThreadContext
Definition: isa.hh:71
void clear() override
Definition: isa.cc:173
MipsISAParams Params
Definition: isa.hh:61
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual RegVal getReg(const RegId &reg) const
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
virtual const PCStateBase & pcState() const =0
virtual void setReg(const RegId &reg, RegVal val)
virtual BaseCPU * getCpuPtr()=0
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
constexpr void replaceBits(T &val, unsigned first, unsigned last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
Definition: bitfield.hh:197
void schedule(Event &event, Tick when)
Definition: eventq.hh:1019
static const Priority CPU_Tick_Pri
CPU ticks must come after other associated CPU events (such as writebacks).
Definition: eventq.hh:204
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
ISA-specific helper functions for multithreaded execution.
constexpr RegClass ccRegClass(CCRegClass, CCRegClassName, cc_reg::NumRegs, debug::CCRegs)
constexpr RegClass vecElemClass
Definition: vec.hh:105
Bitfield< 5, 0 > status
Definition: misc_types.hh:429
constexpr RegClass vecPredRegClass
Definition: vec.hh:109
Bitfield< 24 > j
Definition: misc_types.hh:57
constexpr RegClass vecRegClass
Definition: vec.hh:101
void restoreThread(TC *tc)
Definition: mt.hh:152
constexpr RegClass miscRegClass(MiscRegClass, MiscRegClassName, misc_reg::NumRegs, debug::MiscRegs)
constexpr RegClass intRegClass(IntRegClass, IntRegClassName, int_reg::NumRegs, debug::IntRegs)
void haltThread(TC *tc)
Definition: mt.hh:133
constexpr RegClass floatRegClass(FloatRegClass, FloatRegClassName, float_reg::NumRegs, debug::FloatRegs)
Bitfield< 0 > p
Bitfield< 15, 8 > procId
Bitfield< 23 > k
Definition: dt_constants.hh:81
Bitfield< 2 > i
Bitfield< 63 > val
Definition: misc.hh:776
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:235
constexpr char CCRegClassName[]
Definition: reg_class.hh:78
uint16_t RegIndex
Definition: types.hh:176
constexpr char VecPredRegClassName[]
Definition: reg_class.hh:77
constexpr char VecRegClassName[]
Definition: reg_class.hh:75
uint64_t RegVal
Definition: types.hh:173
@ VecPredRegClass
Definition: reg_class.hh:66
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:67
@ VecRegClass
Vector Register.
Definition: reg_class.hh:63
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:65
constexpr char VecElemClassName[]
Definition: reg_class.hh:76
unsigned CP0_PRId_CompanyOptions
Definition: types.hh:109
unsigned CP0_PRId_ProcessorID
Definition: types.hh:111

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