41 #include "debug/MipsPRA.hh"
42 #include "params/MipsISA.hh"
53 "Index",
"MVPControl",
"MVPConf0",
"MVPConf1",
"",
"",
"",
"",
54 "Random",
"VPEControl",
"VPEConf0",
"VPEConf1",
55 "YQMask",
"VPESchedule",
"VPEScheFBack",
"VPEOpt",
56 "EntryLo0",
"TCStatus",
"TCBind",
"TCRestart",
57 "TCHalt",
"TCContext",
"TCSchedule",
"TCScheFBack",
58 "EntryLo1",
"",
"",
"",
"",
"",
"",
"",
59 "Context",
"ContextConfig",
"",
"",
"",
"",
"",
"",
60 "PageMask",
"PageGrain",
"",
"",
"",
"",
"",
"",
61 "Wired",
"SRSConf0",
"SRCConf1",
"SRSConf2",
62 "SRSConf3",
"SRSConf4",
"",
"",
63 "HWREna",
"",
"",
"",
"",
"",
"",
"",
64 "BadVAddr",
"",
"",
"",
"",
"",
"",
"",
65 "Count",
"",
"",
"",
"",
"",
"",
"",
66 "EntryHi",
"",
"",
"",
"",
"",
"",
"",
67 "Compare",
"",
"",
"",
"",
"",
"",
"",
68 "Status",
"IntCtl",
"SRSCtl",
"SRSMap",
"",
"",
"",
"",
69 "Cause",
"",
"",
"",
"",
"",
"",
"",
70 "EPC",
"",
"",
"",
"",
"",
"",
"",
71 "PRId",
"EBase",
"",
"",
"",
"",
"",
"",
72 "Config",
"Config1",
"Config2",
"Config3",
"",
"",
"",
"",
73 "LLAddr",
"",
"",
"",
"",
"",
"",
"",
74 "WatchLo0",
"WatchLo1",
"WatchLo2",
"WatchLo3",
75 "WatchLo4",
"WatchLo5",
"WatchLo6",
"WatchLo7",
76 "WatchHi0",
"WatchHi1",
"WatchHi2",
"WatchHi3",
77 "WatchHi4",
"WatchHi5",
"WatchHi6",
"WatchHi7",
78 "XCContext64",
"",
"",
"",
"",
"",
"",
"",
79 "",
"",
"",
"",
"",
"",
"",
"",
80 "",
"",
"",
"",
"",
"",
"",
"",
81 "Debug",
"TraceControl1",
"TraceControl2",
"UserTraceData",
82 "TraceBPC",
"",
"",
"",
83 "DEPC",
"",
"",
"",
"",
"",
"",
"",
84 "PerfCnt0",
"PerfCnt1",
"PerfCnt2",
"PerfCnt3",
85 "PerfCnt4",
"PerfCnt5",
"PerfCnt6",
"PerfCnt7",
86 "ErrCtl",
"",
"",
"",
"",
"",
"",
"",
87 "CacheErr0",
"CacheErr1",
"CacheErr2",
"CacheErr3",
"",
"",
"",
"",
88 "TagLo0",
"DataLo1",
"TagLo2",
"DataLo3",
89 "TagLo4",
"DataLo5",
"TagLo6",
"DataLo7",
90 "TagHi0",
"DataHi1",
"TagHi2",
"DataHi3",
91 "TagHi4",
"DataHi5",
"TagHi6",
"DataHi7",
92 "ErrorEPC",
"",
"",
"",
"",
"",
"",
"",
93 "DESAVE",
"",
"",
"",
"",
"",
"",
"",
146 uint32_t num_vpe_regs =
sizeof(per_vpe_regs) / 4;
147 for (
int i = 0;
i < num_vpe_regs;
i++) {
162 uint32_t num_tc_regs =
sizeof(per_tc_regs) / 4;
164 for (
int i = 0;
i < num_tc_regs;
i++) {
207 DPRINTF(MipsPRA,
"Resetting CP0 State with %i TCs and %i VPEs\n",
211 panic(
"CP state must be set before the following code is used");
218 DPRINTF(MipsPRA,
"Initializing CP0 State.... ");
242 RegVal cfg_Mask = 0x7FFF0007;
281 RegVal cfg2_Mask = 0x7000F000;
307 RegVal EB_Mask = 0x3FFFF000;
317 RegVal SC_Mask = 0x0000F3C0;
327 RegVal IC_Mask = 0x000003E0;
336 RegVal wh_Mask = 0x7FFF0FFF;
346 RegVal pc_Mask = 0x00007FF;
362 RegVal pg_Mask = 0x10000000;
381 RegVal stat_Mask = 0xFF78FF17;
457 return tcBind.curVPE;
465 DPRINTF(MipsPRA,
"Reading CP0 Register:%u Select:%u (%s) (%lx).\n",
479 "Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n",
491 "[tid:%i] Setting (direct set) CP0 Register:%u "
492 "Select:%u (%s) to %#x.\n",
504 "[tid:%i] Setting CP0 Register: %u Select: %u (%s) to %#x\n",
520 "[tid:%i] Setting CP0 Register:%u "
521 "Select:%u (%s) to %#x, with effect.\n",
548 "filterCP0Write: Mask: %lx, Inverse Mask: %lx, write Val: %x, "
549 "current val: %lx, written val: %x\n",
579 ThreadID num_threads = mvpConf0.ptc + 1;
581 for (
ThreadID tid = 0; tid < num_threads; tid++) {
586 if (tcHalt.h == 1 || tcStatus.a == 0) {
588 }
else if (tcHalt.h == 0 && tcStatus.a == 1) {
593 num_threads = mvpConf0.ptc + 1;
602 switch (cp0EventType)
virtual ThreadContext * getContext(int tn)
Given a thread num get tho thread context for it.
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Cycles is a wrapper class for representing cycle counts, i.e.
void processCP0Event(BaseCPU *cpu, CP0EventType)
Process a CP0 event.
void setMiscReg(RegIndex idx, RegVal val, ThreadID tid)
std::vector< std::vector< RegVal > > miscRegFile
void updateCPU(BaseCPU *cpu)
RegVal readMiscRegNoEffect(RegIndex idx, ThreadID tid) const
RegVal readMiscReg(RegIndex idx, ThreadID tid)
unsigned getVPENum(ThreadID tid) const
void setRegMask(RegIndex idx, RegVal val, ThreadID tid=0)
void setMiscRegNoEffect(RegIndex idx, RegVal val, ThreadID tid)
std::vector< BankType > bankType
void scheduleCP0Update(BaseCPU *cpu, Cycles delay=Cycles(0))
RegVal filterCP0Write(RegIndex idx, int reg_sel, RegVal val)
This method doesn't need to adjust the Control Register Offset since it has already been done in the ...
std::vector< std::vector< RegVal > > miscRegFile_WriteMask
void copyRegsFrom(ThreadContext *src) override
static std::string miscRegNames[misc_reg::NumRegs]
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual RegVal getReg(const RegId ®) const
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
virtual const PCStateBase & pcState() const =0
virtual void setReg(const RegId ®, RegVal val)
virtual BaseCPU * getCpuPtr()=0
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
constexpr void replaceBits(T &val, unsigned first, unsigned last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
void schedule(Event &event, Tick when)
static const Priority CPU_Tick_Pri
CPU ticks must come after other associated CPU events (such as writebacks).
#define panic(...)
This implements a cprintf based panic() function.
ISA-specific helper functions for multithreaded execution.
constexpr RegClass ccRegClass(CCRegClass, CCRegClassName, cc_reg::NumRegs, debug::CCRegs)
constexpr RegClass vecElemClass
constexpr RegClass vecPredRegClass
constexpr RegClass vecRegClass
void restoreThread(TC *tc)
constexpr RegClass miscRegClass(MiscRegClass, MiscRegClassName, misc_reg::NumRegs, debug::MiscRegs)
constexpr RegClass intRegClass(IntRegClass, IntRegClassName, int_reg::NumRegs, debug::IntRegs)
constexpr RegClass floatRegClass(FloatRegClass, FloatRegClassName, float_reg::NumRegs, debug::FloatRegs)
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
int16_t ThreadID
Thread index/ID type.
constexpr char CCRegClassName[]
constexpr char VecPredRegClassName[]
constexpr char VecRegClassName[]
@ CCRegClass
Condition-code register.
@ VecRegClass
Vector Register.
@ VecElemClass
Vector Register Native Elem lane.
constexpr char VecElemClassName[]
unsigned CP0_IntCtl_IPPCI
unsigned CP0_PRId_Revision
unsigned CP0_PRId_CompanyID
unsigned CP0_PRId_CompanyOptions
unsigned CP0_EBase_CPUNum
unsigned CP0_PRId_ProcessorID