gem5  v21.1.0.2
op_encodings.hh
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33 
34 #ifndef __ARCH_GCN3_INSTS_OP_ENCODINGS_HH__
35 #define __ARCH_GCN3_INSTS_OP_ENCODINGS_HH__
36 
41 #include "debug/GCN3.hh"
42 #include "debug/GPUExec.hh"
44 
45 namespace gem5
46 {
47 
48 namespace Gcn3ISA
49 {
51  {
52  uint64_t baseAddr : 48;
53  uint32_t stride : 14;
54  uint32_t cacheSwizzle : 1;
55  uint32_t swizzleEn : 1;
56  uint32_t numRecords : 32;
57  uint32_t dstSelX : 3;
58  uint32_t dstSelY : 3;
59  uint32_t dstSelZ : 3;
60  uint32_t dstSelW : 3;
61  uint32_t numFmt : 3;
62  uint32_t dataFmt : 4;
63  uint32_t elemSize : 2;
64  uint32_t idxStride : 2;
65  uint32_t addTidEn : 1;
66  uint32_t atc : 1;
67  uint32_t hashEn : 1;
68  uint32_t heap : 1;
69  uint32_t mType : 3;
70  uint32_t type : 2;
71  };
72 
73  // --- purely virtual instruction classes ---
74 
76  {
77  public:
78  Inst_SOP2(InFmt_SOP2*, const std::string &opcode);
79 
80  int instSize() const override;
81  void generateDisassembly() override;
82 
83  void initOperandInfo() override;
84 
85  protected:
86  // first instruction DWORD
88  // possible second DWORD
90  uint32_t varSize;
91 
92  private:
93  bool hasSecondDword(InFmt_SOP2 *);
94  }; // Inst_SOP2
95 
97  {
98  public:
99  Inst_SOPK(InFmt_SOPK*, const std::string &opcode);
100  ~Inst_SOPK();
101 
102  int instSize() const override;
103  void generateDisassembly() override;
104 
105  void initOperandInfo() override;
106 
107  protected:
108  // first instruction DWORD
110  // possible second DWORD
112  uint32_t varSize;
113 
114  private:
115  bool hasSecondDword(InFmt_SOPK *);
116  }; // Inst_SOPK
117 
119  {
120  public:
121  Inst_SOP1(InFmt_SOP1*, const std::string &opcode);
122  ~Inst_SOP1();
123 
124  int instSize() const override;
125  void generateDisassembly() override;
126 
127  void initOperandInfo() override;
128 
129  protected:
130  // first instruction DWORD
132  // possible second DWORD
134  uint32_t varSize;
135 
136  private:
137  bool hasSecondDword(InFmt_SOP1 *);
138  }; // Inst_SOP1
139 
141  {
142  public:
143  Inst_SOPC(InFmt_SOPC*, const std::string &opcode);
144  ~Inst_SOPC();
145 
146  int instSize() const override;
147  void generateDisassembly() override;
148 
149  void initOperandInfo() override;
150 
151  protected:
152  // first instruction DWORD
154  // possible second DWORD
156  uint32_t varSize;
157 
158  private:
159  bool hasSecondDword(InFmt_SOPC *);
160  }; // Inst_SOPC
161 
163  {
164  public:
165  Inst_SOPP(InFmt_SOPP*, const std::string &opcode);
166  ~Inst_SOPP();
167 
168  int instSize() const override;
169  void generateDisassembly() override;
170 
171  void initOperandInfo() override;
172 
173  protected:
174  // first instruction DWORD
176  }; // Inst_SOPP
177 
179  {
180  public:
181  Inst_SMEM(InFmt_SMEM*, const std::string &opcode);
182  ~Inst_SMEM();
183 
184  int instSize() const override;
185  void generateDisassembly() override;
186 
187  void initOperandInfo() override;
188 
189  protected:
193  template<int N>
194  void
196  {
197  initMemReqScalarHelper<ScalarRegU32, N>(gpuDynInst,
199  }
200 
204  template<int N>
205  void
207  {
208  initMemReqScalarHelper<ScalarRegU32, N>(gpuDynInst,
210  }
211 
215  void
218  {
219  Addr vaddr = ((addr.rawData() + offset) & ~0x3);
220  gpu_dyn_inst->scalarAddr = vaddr;
221  }
222 
228  void
229  calcAddr(GPUDynInstPtr gpu_dyn_inst,
231  {
232  BufferRsrcDescriptor rsrc_desc;
233  ScalarRegU32 clamped_offset(offset);
234  std::memcpy((void*)&rsrc_desc, s_rsrc_desc.rawDataPtr(),
235  sizeof(BufferRsrcDescriptor));
236 
242  if (!rsrc_desc.stride && offset >= rsrc_desc.numRecords) {
243  clamped_offset = rsrc_desc.numRecords;
244  } else if (rsrc_desc.stride && offset
245  > (rsrc_desc.stride * rsrc_desc.numRecords)) {
246  clamped_offset = (rsrc_desc.stride * rsrc_desc.numRecords);
247  }
248 
249  Addr vaddr = ((rsrc_desc.baseAddr + clamped_offset) & ~0x3);
250  gpu_dyn_inst->scalarAddr = vaddr;
251  }
252 
253  // first instruction DWORD
255  // second instruction DWORD
257  }; // Inst_SMEM
258 
260  {
261  public:
262  Inst_VOP2(InFmt_VOP2*, const std::string &opcode);
263  ~Inst_VOP2();
264 
265  int instSize() const override;
266  void generateDisassembly() override;
267 
268  void initOperandInfo() override;
269 
270  protected:
271  // first instruction DWORD
273  // possible second DWORD
275  uint32_t varSize;
276 
277  private:
278  bool hasSecondDword(InFmt_VOP2 *);
279  }; // Inst_VOP2
280 
282  {
283  public:
284  Inst_VOP1(InFmt_VOP1*, const std::string &opcode);
285  ~Inst_VOP1();
286 
287  int instSize() const override;
288  void generateDisassembly() override;
289 
290  void initOperandInfo() override;
291 
292  protected:
293  // first instruction DWORD
295  // possible second DWORD
297  uint32_t varSize;
298 
299  private:
300  bool hasSecondDword(InFmt_VOP1 *);
301  }; // Inst_VOP1
302 
304  {
305  public:
306  Inst_VOPC(InFmt_VOPC*, const std::string &opcode);
307  ~Inst_VOPC();
308 
309  int instSize() const override;
310  void generateDisassembly() override;
311 
312  void initOperandInfo() override;
313 
314  protected:
315  // first instruction DWORD
317  // possible second DWORD
319  uint32_t varSize;
320 
321  private:
322  bool hasSecondDword(InFmt_VOPC *);
323  }; // Inst_VOPC
324 
326  {
327  public:
328  Inst_VINTRP(InFmt_VINTRP*, const std::string &opcode);
329  ~Inst_VINTRP();
330 
331  int instSize() const override;
332 
333  protected:
334  // first instruction DWORD
336  }; // Inst_VINTRP
337 
339  {
340  public:
341  Inst_VOP3(InFmt_VOP3*, const std::string &opcode, bool sgpr_dst);
342  ~Inst_VOP3();
343 
344  int instSize() const override;
345  void generateDisassembly() override;
346 
347  void initOperandInfo() override;
348 
349  protected:
350  // first instruction DWORD
352  // second instruction DWORD
354 
355  private:
356  bool hasSecondDword(InFmt_VOP3 *);
367  const bool sgprDst;
368  }; // Inst_VOP3
369 
371  {
372  public:
373  Inst_VOP3_SDST_ENC(InFmt_VOP3_SDST_ENC*, const std::string &opcode);
375 
376  int instSize() const override;
377  void generateDisassembly() override;
378 
379  void initOperandInfo() override;
380 
381  protected:
382  // first instruction DWORD
384  // second instruction DWORD
386 
387  private:
389  }; // Inst_VOP3_SDST_ENC
390 
391  class Inst_DS : public GCN3GPUStaticInst
392  {
393  public:
394  Inst_DS(InFmt_DS*, const std::string &opcode);
395  ~Inst_DS();
396 
397  int instSize() const override;
398  void generateDisassembly() override;
399 
400  void initOperandInfo() override;
401 
402  protected:
403  template<typename T>
404  void
406  {
407  Wavefront *wf = gpuDynInst->wavefront();
408 
409  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
410  if (gpuDynInst->exec_mask[lane]) {
411  Addr vaddr = gpuDynInst->addr[lane] + offset;
412 
413  (reinterpret_cast<T*>(gpuDynInst->d_data))[lane]
414  = wf->ldsChunk->read<T>(vaddr);
415  }
416  }
417  }
418 
419  template<int N>
420  void
422  {
423  Wavefront *wf = gpuDynInst->wavefront();
424 
425  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
426  if (gpuDynInst->exec_mask[lane]) {
427  Addr vaddr = gpuDynInst->addr[lane] + offset;
428  for (int i = 0; i < N; ++i) {
429  (reinterpret_cast<VecElemU32*>(
430  gpuDynInst->d_data))[lane * N + i]
431  = wf->ldsChunk->read<VecElemU32>(
432  vaddr + i*sizeof(VecElemU32));
433  }
434  }
435  }
436  }
437 
438  template<typename T>
439  void
440  initDualMemRead(GPUDynInstPtr gpuDynInst, Addr offset0, Addr offset1)
441  {
442  Wavefront *wf = gpuDynInst->wavefront();
443 
444  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
445  if (gpuDynInst->exec_mask[lane]) {
446  Addr vaddr0 = gpuDynInst->addr[lane] + offset0;
447  Addr vaddr1 = gpuDynInst->addr[lane] + offset1;
448 
449  (reinterpret_cast<T*>(gpuDynInst->d_data))[lane * 2]
450  = wf->ldsChunk->read<T>(vaddr0);
451  (reinterpret_cast<T*>(gpuDynInst->d_data))[lane * 2 + 1]
452  = wf->ldsChunk->read<T>(vaddr1);
453  }
454  }
455  }
456 
457  template<typename T>
458  void
460  {
461  Wavefront *wf = gpuDynInst->wavefront();
462 
463  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
464  if (gpuDynInst->exec_mask[lane]) {
465  Addr vaddr = gpuDynInst->addr[lane] + offset;
466  wf->ldsChunk->write<T>(vaddr,
467  (reinterpret_cast<T*>(gpuDynInst->d_data))[lane]);
468  }
469  }
470  }
471 
472  template<int N>
473  void
475  {
476  Wavefront *wf = gpuDynInst->wavefront();
477 
478  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
479  if (gpuDynInst->exec_mask[lane]) {
480  Addr vaddr = gpuDynInst->addr[lane] + offset;
481  for (int i = 0; i < N; ++i) {
482  wf->ldsChunk->write<VecElemU32>(
483  vaddr + i*sizeof(VecElemU32),
484  (reinterpret_cast<VecElemU32*>(
485  gpuDynInst->d_data))[lane * N + i]);
486  }
487  }
488  }
489  }
490 
491  template<typename T>
492  void
493  initDualMemWrite(GPUDynInstPtr gpuDynInst, Addr offset0, Addr offset1)
494  {
495  Wavefront *wf = gpuDynInst->wavefront();
496 
497  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
498  if (gpuDynInst->exec_mask[lane]) {
499  Addr vaddr0 = gpuDynInst->addr[lane] + offset0;
500  Addr vaddr1 = gpuDynInst->addr[lane] + offset1;
501  wf->ldsChunk->write<T>(vaddr0, (reinterpret_cast<T*>(
502  gpuDynInst->d_data))[lane * 2]);
503  wf->ldsChunk->write<T>(vaddr1, (reinterpret_cast<T*>(
504  gpuDynInst->d_data))[lane * 2 + 1]);
505  }
506  }
507  }
508 
509  void
511  {
512  Wavefront *wf = gpuDynInst->wavefront();
513 
514  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
515  if (wf->execMask(lane)) {
516  gpuDynInst->addr.at(lane) = (Addr)addr[lane];
517  }
518  }
519  }
520 
521  // first instruction DWORD
523  // second instruction DWORD
525  }; // Inst_DS
526 
528  {
529  public:
530  Inst_MUBUF(InFmt_MUBUF*, const std::string &opcode);
531  ~Inst_MUBUF();
532 
533  int instSize() const override;
534  void generateDisassembly() override;
535 
536  void initOperandInfo() override;
537 
538  protected:
539  template<typename T>
540  void
542  {
543  // temporarily modify exec_mask to supress memory accesses to oob
544  // regions. Only issue memory requests for lanes that have their
545  // exec_mask set and are not out of bounds.
546  VectorMask old_exec_mask = gpuDynInst->exec_mask;
547  gpuDynInst->exec_mask &= ~oobMask;
548  initMemReqHelper<T, 1>(gpuDynInst, MemCmd::ReadReq);
549  gpuDynInst->exec_mask = old_exec_mask;
550  }
551 
552 
553  template<int N>
554  void
556  {
557  // temporarily modify exec_mask to supress memory accesses to oob
558  // regions. Only issue memory requests for lanes that have their
559  // exec_mask set and are not out of bounds.
560  VectorMask old_exec_mask = gpuDynInst->exec_mask;
561  gpuDynInst->exec_mask &= ~oobMask;
562  initMemReqHelper<VecElemU32, N>(gpuDynInst, MemCmd::ReadReq);
563  gpuDynInst->exec_mask = old_exec_mask;
564  }
565 
566  template<typename T>
567  void
569  {
570  // temporarily modify exec_mask to supress memory accesses to oob
571  // regions. Only issue memory requests for lanes that have their
572  // exec_mask set and are not out of bounds.
573  VectorMask old_exec_mask = gpuDynInst->exec_mask;
574  gpuDynInst->exec_mask &= ~oobMask;
575  initMemReqHelper<T, 1>(gpuDynInst, MemCmd::WriteReq);
576  gpuDynInst->exec_mask = old_exec_mask;
577  }
578 
579  template<int N>
580  void
582  {
583  // temporarily modify exec_mask to supress memory accesses to oob
584  // regions. Only issue memory requests for lanes that have their
585  // exec_mask set and are not out of bounds.
586  VectorMask old_exec_mask = gpuDynInst->exec_mask;
587  gpuDynInst->exec_mask &= ~oobMask;
588  initMemReqHelper<VecElemU32, N>(gpuDynInst, MemCmd::WriteReq);
589  gpuDynInst->exec_mask = old_exec_mask;
590  }
591 
592  void
594  {
595  // create request and set flags
596  gpuDynInst->resetEntireStatusVector();
597  gpuDynInst->setStatusVector(0, 1);
598  RequestPtr req = std::make_shared<Request>(0, 0, 0,
599  gpuDynInst->computeUnit()->
600  requestorId(), 0,
601  gpuDynInst->wfDynId);
602  gpuDynInst->setRequestFlags(req);
603  gpuDynInst->computeUnit()->
604  injectGlobalMemFence(gpuDynInst, false, req);
605  }
606 
627  template<typename VOFF, typename VIDX, typename SRSRC, typename SOFF>
628  void
629  calcAddr(GPUDynInstPtr gpuDynInst, VOFF v_off, VIDX v_idx,
630  SRSRC s_rsrc_desc, SOFF s_offset, int inst_offset)
631  {
632  Addr vaddr = 0;
633  Addr base_addr = 0;
634  Addr stride = 0;
635  Addr buf_idx = 0;
636  Addr buf_off = 0;
637  BufferRsrcDescriptor rsrc_desc;
638 
639  std::memcpy((void*)&rsrc_desc, s_rsrc_desc.rawDataPtr(),
640  sizeof(BufferRsrcDescriptor));
641 
642  base_addr = rsrc_desc.baseAddr;
643 
644  stride = rsrc_desc.addTidEn ? ((rsrc_desc.dataFmt << 14)
645  + rsrc_desc.stride) : rsrc_desc.stride;
646 
647  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
648  if (gpuDynInst->exec_mask[lane]) {
649  vaddr = base_addr + s_offset.rawData();
655  buf_idx = v_idx[lane] + (rsrc_desc.addTidEn ? lane : 0);
656 
657  buf_off = v_off[lane] + inst_offset;
658 
659 
667  if (rsrc_desc.stride == 0 || !rsrc_desc.swizzleEn) {
668  if (buf_off + stride * buf_idx >=
669  rsrc_desc.numRecords - s_offset.rawData()) {
670  DPRINTF(GCN3, "mubuf out-of-bounds condition 1: "
671  "lane = %d, buffer_offset = %llx, "
672  "const_stride = %llx, "
673  "const_num_records = %llx\n",
674  lane, buf_off + stride * buf_idx,
675  rsrc_desc.stride, rsrc_desc.numRecords);
676  oobMask.set(lane);
677  continue;
678  }
679  }
680 
681  if (rsrc_desc.stride != 0 && rsrc_desc.swizzleEn) {
682  if (buf_idx >= rsrc_desc.numRecords ||
683  buf_off >= stride) {
684  DPRINTF(GCN3, "mubuf out-of-bounds condition 2: "
685  "lane = %d, offset = %llx, "
686  "index = %llx, "
687  "const_num_records = %llx\n",
688  lane, buf_off, buf_idx,
689  rsrc_desc.numRecords);
690  oobMask.set(lane);
691  continue;
692  }
693  }
694 
695  if (rsrc_desc.swizzleEn) {
696  Addr idx_stride = 8 << rsrc_desc.idxStride;
697  Addr elem_size = 2 << rsrc_desc.elemSize;
698  Addr idx_msb = buf_idx / idx_stride;
699  Addr idx_lsb = buf_idx % idx_stride;
700  Addr off_msb = buf_off / elem_size;
701  Addr off_lsb = buf_off % elem_size;
702  DPRINTF(GCN3, "mubuf swizzled lane %d: "
703  "idx_stride = %llx, elem_size = %llx, "
704  "idx_msb = %llx, idx_lsb = %llx, "
705  "off_msb = %llx, off_lsb = %llx\n",
706  lane, idx_stride, elem_size, idx_msb, idx_lsb,
707  off_msb, off_lsb);
708 
709  vaddr += ((idx_msb * stride + off_msb * elem_size)
710  * idx_stride + idx_lsb * elem_size + off_lsb);
711  } else {
712  vaddr += buf_off + stride * buf_idx;
713  }
714 
715  DPRINTF(GCN3, "Calculating mubuf address for lane %d: "
716  "vaddr = %llx, base_addr = %llx, "
717  "stride = %llx, buf_idx = %llx, buf_off = %llx\n",
718  lane, vaddr, base_addr, stride,
719  buf_idx, buf_off);
720  gpuDynInst->addr.at(lane) = vaddr;
721  }
722  }
723  }
724 
725  // first instruction DWORD
727  // second instruction DWORD
729  // Mask of lanes with out-of-bounds accesses. Needs to be tracked
730  // seperately from the exec_mask so that we remember to write zero
731  // to the registers associated with out of bounds lanes.
733  }; // Inst_MUBUF
734 
736  {
737  public:
738  Inst_MTBUF(InFmt_MTBUF*, const std::string &opcode);
739  ~Inst_MTBUF();
740 
741  int instSize() const override;
742  void initOperandInfo() override;
743 
744  protected:
745  // first instruction DWORD
747  // second instruction DWORD
749 
750  private:
751  bool hasSecondDword(InFmt_MTBUF *);
752  }; // Inst_MTBUF
753 
755  {
756  public:
757  Inst_MIMG(InFmt_MIMG*, const std::string &opcode);
758  ~Inst_MIMG();
759 
760  int instSize() const override;
761  void initOperandInfo() override;
762 
763  protected:
764  // first instruction DWORD
766  // second instruction DWORD
768  }; // Inst_MIMG
769 
771  {
772  public:
773  Inst_EXP(InFmt_EXP*, const std::string &opcode);
774  ~Inst_EXP();
775 
776  int instSize() const override;
777  void initOperandInfo() override;
778 
779  protected:
780  // first instruction DWORD
782  // second instruction DWORD
784  }; // Inst_EXP
785 
787  {
788  public:
789  Inst_FLAT(InFmt_FLAT*, const std::string &opcode);
790  ~Inst_FLAT();
791 
792  int instSize() const override;
793  void generateDisassembly() override;
794 
795  void initOperandInfo() override;
796 
797  protected:
798  template<typename T>
799  void
801  {
802  if (gpuDynInst->executedAs() == enums::SC_GLOBAL) {
803  initMemReqHelper<T, 1>(gpuDynInst, MemCmd::ReadReq);
804  } else if (gpuDynInst->executedAs() == enums::SC_GROUP) {
805  Wavefront *wf = gpuDynInst->wavefront();
806  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
807  if (gpuDynInst->exec_mask[lane]) {
808  Addr vaddr = gpuDynInst->addr[lane];
809  (reinterpret_cast<T*>(gpuDynInst->d_data))[lane]
810  = wf->ldsChunk->read<T>(vaddr);
811  }
812  }
813  }
814  }
815 
816  template<int N>
817  void
819  {
820  if (gpuDynInst->executedAs() == enums::SC_GLOBAL) {
821  initMemReqHelper<VecElemU32, N>(gpuDynInst, MemCmd::ReadReq);
822  } else if (gpuDynInst->executedAs() == enums::SC_GROUP) {
823  Wavefront *wf = gpuDynInst->wavefront();
824  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
825  if (gpuDynInst->exec_mask[lane]) {
826  Addr vaddr = gpuDynInst->addr[lane];
827  for (int i = 0; i < N; ++i) {
828  (reinterpret_cast<VecElemU32*>(
829  gpuDynInst->d_data))[lane * N + i]
830  = wf->ldsChunk->read<VecElemU32>(
831  vaddr + i*sizeof(VecElemU32));
832  }
833  }
834  }
835  }
836  }
837 
838  template<typename T>
839  void
841  {
842  if (gpuDynInst->executedAs() == enums::SC_GLOBAL) {
843  initMemReqHelper<T, 1>(gpuDynInst, MemCmd::WriteReq);
844  } else if (gpuDynInst->executedAs() == enums::SC_GROUP) {
845  Wavefront *wf = gpuDynInst->wavefront();
846  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
847  if (gpuDynInst->exec_mask[lane]) {
848  Addr vaddr = gpuDynInst->addr[lane];
849  wf->ldsChunk->write<T>(vaddr,
850  (reinterpret_cast<T*>(gpuDynInst->d_data))[lane]);
851  }
852  }
853  }
854  }
855 
856  template<int N>
857  void
859  {
860  if (gpuDynInst->executedAs() == enums::SC_GLOBAL) {
861  initMemReqHelper<VecElemU32, N>(gpuDynInst, MemCmd::WriteReq);
862  } else if (gpuDynInst->executedAs() == enums::SC_GROUP) {
863  Wavefront *wf = gpuDynInst->wavefront();
864  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
865  if (gpuDynInst->exec_mask[lane]) {
866  Addr vaddr = gpuDynInst->addr[lane];
867  for (int i = 0; i < N; ++i) {
868  wf->ldsChunk->write<VecElemU32>(
869  vaddr + i*sizeof(VecElemU32),
870  (reinterpret_cast<VecElemU32*>(
871  gpuDynInst->d_data))[lane * N + i]);
872  }
873  }
874  }
875  }
876  }
877 
878  template<typename T>
879  void
881  {
882  if (gpuDynInst->executedAs() == enums::SC_GLOBAL) {
883  initMemReqHelper<T, 1>(gpuDynInst, MemCmd::SwapReq, true);
884  } else if (gpuDynInst->executedAs() == enums::SC_GROUP) {
885  Wavefront *wf = gpuDynInst->wavefront();
886  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
887  if (gpuDynInst->exec_mask[lane]) {
888  Addr vaddr = gpuDynInst->addr[lane];
889  AtomicOpFunctor* amo_op =
890  gpuDynInst->makeAtomicOpFunctor<T>(
891  &(reinterpret_cast<T*>(
892  gpuDynInst->a_data))[lane],
893  &(reinterpret_cast<T*>(
894  gpuDynInst->x_data))[lane]).get();
895 
896  T tmp = wf->ldsChunk->read<T>(vaddr);
897  (*amo_op)(reinterpret_cast<uint8_t *>(&tmp));
898  wf->ldsChunk->write<T>(vaddr, tmp);
899  (reinterpret_cast<T*>(gpuDynInst->d_data))[lane] = tmp;
900  }
901  }
902  }
903  }
904 
905  void
907  {
908  for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
909  if (gpuDynInst->exec_mask[lane]) {
910  gpuDynInst->addr.at(lane) = addr[lane];
911  }
912  }
913  gpuDynInst->resolveFlatSegment(gpuDynInst->exec_mask);
914  }
915 
916  // first instruction DWORD
918  // second instruction DWORD
920  }; // Inst_FLAT
921 } // namespace Gcn3ISA
922 } // namespace gem5
923 
924 #endif // __ARCH_GCN3_INSTS_OP_ENCODINGS_HH__
gem5::Gcn3ISA::Inst_SOP1
Definition: op_encodings.hh:118
gem5::Gcn3ISA::Inst_FLAT::extData
InFmt_FLAT_1 extData
Definition: op_encodings.hh:919
gpu_decoder.hh
gem5::Gcn3ISA::Inst_MUBUF::oobMask
VectorMask oobMask
Definition: op_encodings.hh:732
gem5::Gcn3ISA::Inst_DS::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:1170
gem5::Gcn3ISA::Inst_VOP2::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:685
gem5::Gcn3ISA::Inst_SOPC::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:358
gem5::Gcn3ISA::Inst_SOP2::hasSecondDword
bool hasSecondDword(InFmt_SOP2 *)
Definition: op_encodings.cc:93
gem5::Gcn3ISA::BufferRsrcDescriptor::elemSize
uint32_t elemSize
Definition: op_encodings.hh:63
gem5::Gcn3ISA::Inst_SOPC::instData
InFmt_SOPC instData
Definition: op_encodings.hh:153
gem5::Gcn3ISA::ScalarOperand::rawDataPtr
void * rawDataPtr()
Definition: operand.hh:404
gem5::Gcn3ISA::Inst_VOP1::hasSecondDword
bool hasSecondDword(InFmt_VOP1 *)
Definition: op_encodings.cc:779
gem5::Gcn3ISA::Inst_SOP1::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:247
gem5::Gcn3ISA::Inst_FLAT::~Inst_FLAT
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Definition: op_encodings.cc:1530
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Definition: gpu_decoder.hh:1539
gem5::Gcn3ISA::Inst_SOP1::extData
InstFormat extData
Definition: op_encodings.hh:133
gem5::Gcn3ISA::Inst_EXP::extData
InFmt_EXP_1 extData
Definition: op_encodings.hh:783
gem5::Gcn3ISA::Inst_SOPK::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:152
gem5::Gcn3ISA::Inst_DS::Inst_DS
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Definition: op_encodings.cc:1153
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Definition: gpu_decoder.hh:1375
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@ SwapReq
Definition: packet.hh:115
gem5::Gcn3ISA::Inst_MUBUF::instData
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Definition: op_encodings.hh:726
gem5::Gcn3ISA::Inst_DS::initMemRead
void initMemRead(GPUDynInstPtr gpuDynInst, Addr offset)
Definition: op_encodings.hh:405
gem5::Gcn3ISA::Inst_VOPC::hasSecondDword
bool hasSecondDword(InFmt_VOPC *)
Definition: op_encodings.cc:874
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Definition: amo.hh:43
gem5::Gcn3ISA::Inst_VOP2::~Inst_VOP2
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Definition: op_encodings.cc:610
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Definition: op_encodings.cc:1342
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Definition: op_encodings.hh:53
gem5::Gcn3ISA::Inst_VOPC::generateDisassembly
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Definition: op_encodings.cc:893
gem5::Gcn3ISA::VecElemU32
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Definition: gpu_registers.hh:167
gem5::Gcn3ISA::Inst_FLAT::calcAddr
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Definition: op_encodings.hh:906
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Definition: op_encodings.hh:325
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InstFormat extData
Definition: op_encodings.hh:89
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Definition: op_encodings.cc:1326
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Definition: op_encodings.hh:338
gem5::Gcn3ISA::Inst_SMEM::calcAddr
void calcAddr(GPUDynInstPtr gpu_dyn_inst, ConstScalarOperandU64 &addr, ScalarRegU32 offset)
For normal s_load_dword/s_store_dword instruction addresses.
Definition: op_encodings.hh:216
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LdsChunk * ldsChunk
Definition: wavefront.hh:225
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Definition: op_encodings.hh:754
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Definition: wavefront.hh:62
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Definition: gpu_decoder.hh:1601
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Definition: gpu_decoder.hh:1531
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Definition: op_encodings.cc:745
gem5::Gcn3ISA::Inst_SMEM::initOperandInfo
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Definition: op_encodings.cc:502
gem5::Gcn3ISA::Inst_SOPP::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:426
gem5::Gcn3ISA::Inst_VOP3_SDST_ENC::Inst_VOP3_SDST_ENC
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Definition: op_encodings.cc:1046
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Definition: op_encodings.cc:818
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Definition: op_encodings.hh:391
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Definition: gpu_decoder.hh:1433
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std::bitset< std::numeric_limits< unsigned long long >::digits > VectorMask
Definition: misc.hh:47
gem5::Gcn3ISA::Inst_SMEM::extData
InFmt_SMEM_1 extData
Definition: op_encodings.hh:256
gem5::Gcn3ISA::Inst_SMEM::initMemWrite
void initMemWrite(GPUDynInstPtr gpuDynInst)
initiate a memory write access for N dwords
Definition: op_encodings.hh:206
gem5::Gcn3ISA::Inst_SOPK::extData
InstFormat extData
Definition: op_encodings.hh:111
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Definition: operand.hh:103
gem5::Gcn3ISA::Inst_SOP2::varSize
uint32_t varSize
Definition: op_encodings.hh:90
gem5::Gcn3ISA::Inst_VOP2::Inst_VOP2
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Definition: op_encodings.cc:590
gem5::Gcn3ISA::Inst_MTBUF::instSize
int instSize() const override
Definition: op_encodings.cc:1391
gem5::Gcn3ISA::BufferRsrcDescriptor::dataFmt
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Definition: op_encodings.hh:62
gem5::Gcn3ISA::Inst_MUBUF::calcAddr
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Definition: op_encodings.hh:629
gem5::Gcn3ISA::Inst_FLAT::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:1535
gem5::Gcn3ISA::Inst_MUBUF::extData
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Definition: op_encodings.hh:728
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Definition: op_encodings.hh:66
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Definition: gpu_decoder.hh:1386
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Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::Gcn3ISA::Inst_VOP3_SDST_ENC::instSize
int instSize() const override
Definition: op_encodings.cc:1102
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Definition: op_encodings.cc:1414
gem5::Gcn3ISA::Inst_DS::instData
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Definition: op_encodings.hh:522
gem5::Gcn3ISA::Inst_VOP1::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:750
gem5::Gcn3ISA::Inst_SOPC::extData
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Definition: op_encodings.hh:155
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Definition: gpu_decoder.hh:1501
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Definition: op_encodings.cc:1249
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Definition: op_encodings.cc:906
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Definition: gpu_decoder.hh:1523
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Definition: op_encodings.hh:493
gem5::Gcn3ISA::BufferRsrcDescriptor::dstSelZ
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Definition: op_encodings.hh:59
gem5::Gcn3ISA::Inst_VOP3::instSize
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Definition: op_encodings.cc:981
gem5::Gcn3ISA::Inst_SOPC::Inst_SOPC
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Definition: op_encodings.cc:301
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Definition: op_encodings.hh:917
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Definition: op_encodings.hh:57
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Definition: gpu_decoder.hh:1455
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Definition: op_encodings.hh:55
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Definition: op_encodings.cc:1483
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Definition: op_encodings.cc:180
gem5::Gcn3ISA::Inst_SOPK::hasSecondDword
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Definition: op_encodings.cc:186
gem5::Gcn3ISA::Inst_VOP3::Inst_VOP3
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Definition: op_encodings.cc:925
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const std::string & opcode() const
Definition: gpu_static_inst.hh:264
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Definition: op_encodings.hh:50
gem5::Gcn3ISA::BufferRsrcDescriptor::dstSelY
uint32_t dstSelY
Definition: op_encodings.hh:58
gem5::Gcn3ISA::Inst_SOPK::Inst_SOPK
Inst_SOPK(InFmt_SOPK *, const std::string &opcode)
Definition: op_encodings.cc:130
gem5::Gcn3ISA::Inst_MTBUF::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:1347
gem5::Gcn3ISA::Inst_MIMG::Inst_MIMG
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Definition: op_encodings.cc:1398
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gem5::Gcn3ISA::Inst_SOPP::Inst_SOPP
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Definition: op_encodings.cc:382
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Definition: gpu_decoder.hh:1564
gem5::Gcn3ISA::Inst_EXP::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:1488
gem5::Gcn3ISA::Inst_MUBUF::initOperandInfo
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Definition: op_encodings.cc:1254
gem5::Gcn3ISA::Inst_SOPC::hasSecondDword
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Definition: op_encodings.cc:346
gem5::Gcn3ISA::BufferRsrcDescriptor::dstSelW
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Definition: op_encodings.hh:60
gem5::Gcn3ISA::Inst_VOP2::instData
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Definition: op_encodings.hh:272
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Definition: op_encodings.hh:162
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
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Definition: gpu_decoder.hh:1367
gem5::Gcn3ISA::BufferRsrcDescriptor::numFmt
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Definition: op_encodings.hh:61
gem5::Gcn3ISA::Inst_EXP::instSize
int instSize() const override
Definition: op_encodings.cc:1506
gem5::Gcn3ISA::NumVecElemPerVecReg
const int NumVecElemPerVecReg(64)
gpu_static_inst.hh
gem5::Gcn3ISA::ScalarOperand
Definition: operand.hh:99
gem5::Gcn3ISA::BufferRsrcDescriptor::addTidEn
uint32_t addTidEn
Definition: op_encodings.hh:65
gem5::Gcn3ISA::Inst_SOP1::hasSecondDword
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Definition: op_encodings.cc:274
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Definition: request.hh:92
gem5::Gcn3ISA::Inst_SOP1::instData
InFmt_SOP1 instData
Definition: op_encodings.hh:131
gem5::MemCmd::ReadReq
@ ReadReq
Definition: packet.hh:86
gem5::Gcn3ISA::Inst_MUBUF::initMemWrite
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Definition: op_encodings.hh:568
gem5::Gcn3ISA::Inst_SOP2::instData
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Definition: op_encodings.hh:87
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Definition: op_encodings.hh:748
gem5::Gcn3ISA::Inst_VOP2::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:615
gem5::Gcn3ISA::Inst_VOP1::generateDisassembly
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Definition: op_encodings.cc:798
gem5::Gcn3ISA::Inst_SOP1::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:283
gem5::Gcn3ISA::Inst_VOPC::extData
InstFormat extData
Definition: op_encodings.hh:318
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Definition: op_encodings.hh:96
gem5::Gcn3ISA::Inst_FLAT::initMemRead
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Definition: op_encodings.hh:800
gem5::Gcn3ISA::Inst_VOP2::instSize
int instSize() const override
Definition: op_encodings.cc:654
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Definition: types.hh:144
gem5::Gcn3ISA::BufferRsrcDescriptor::idxStride
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Definition: op_encodings.hh:64
gem5::Gcn3ISA::Inst_FLAT::generateDisassembly
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Definition: op_encodings.cc:1578
gem5::Gcn3ISA::Inst_FLAT::Inst_FLAT
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Definition: op_encodings.cc:1513
gem5::Gcn3ISA::Inst_MTBUF::hasSecondDword
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Definition: gpu_decoder.hh:1480
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Definition: lds_state.hh:92
gem5::Gcn3ISA::Inst_EXP::instData
InFmt_EXP instData
Definition: op_encodings.hh:781
gem5::Gcn3ISA::Inst_EXP::Inst_EXP
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Definition: op_encodings.cc:1473
gem5::Gcn3ISA::Inst_SOP2::instSize
int instSize() const override
Definition: op_encodings.cc:87
gem5::Gcn3ISA::Inst_VOP2::varSize
uint32_t varSize
Definition: op_encodings.hh:275
gem5::Gcn3ISA::Inst_SOP1::varSize
uint32_t varSize
Definition: op_encodings.hh:134
gem5::Gcn3ISA::Inst_VOP3_SDST_ENC::instData
InFmt_VOP3_SDST_ENC instData
Definition: op_encodings.hh:383
gem5::Gcn3ISA::Inst_VOPC::instSize
int instSize() const override
Definition: op_encodings.cc:868
gem5::Gcn3ISA::BufferRsrcDescriptor::hashEn
uint32_t hashEn
Definition: op_encodings.hh:67
gem5::Gcn3ISA::Inst_VOP3_SDST_ENC
Definition: op_encodings.hh:370
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VectorMask & execMask()
Definition: wavefront.cc:1377
gem5::Gcn3ISA::Inst_SOPP::instData
InFmt_SOPP instData
Definition: op_encodings.hh:175
gem5::Gcn3ISA::Inst_VOPC::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:844
gem5::Gcn3ISA::InFmt_SOP2
Definition: gpu_decoder.hh:1514
gem5::Gcn3ISA::Inst_SOP2::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:63
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uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::Gcn3ISA::Inst_VOP3::instData
InFmt_VOP3 instData
Definition: op_encodings.hh:351
gem5::Gcn3ISA::Inst_SOPP::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:396
gem5::Gcn3ISA::Inst_FLAT::initMemWrite
void initMemWrite(GPUDynInstPtr gpuDynInst)
Definition: op_encodings.hh:840
gem5::Gcn3ISA::Inst_SOPK::instData
InFmt_SOPK instData
Definition: op_encodings.hh:109
gem5::Gcn3ISA::Inst_SMEM::calcAddr
void calcAddr(GPUDynInstPtr gpu_dyn_inst, ConstScalarOperandU128 &s_rsrc_desc, ScalarRegU32 offset)
For s_buffer_load_dword/s_buffer_store_dword instruction addresses.
Definition: op_encodings.hh:229
gem5::Gcn3ISA::Inst_FLAT::initAtomicAccess
void initAtomicAccess(GPUDynInstPtr gpuDynInst)
Definition: op_encodings.hh:880
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Definition: op_encodings.hh:770
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Definition: op_encodings.cc:913
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Definition: op_encodings.hh:297
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Definition: gpu_decoder.hh:1556
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std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition: misc.hh:51
gem5::Gcn3ISA::BufferRsrcDescriptor::type
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Definition: op_encodings.hh:70
gem5::Gcn3ISA::Inst_MIMG::initOperandInfo
void initOperandInfo() override
Definition: op_encodings.cc:1419
gem5::Gcn3ISA::Inst_MTBUF::instData
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Definition: op_encodings.hh:746
gem5::Gcn3ISA::InFmt_VINTRP
Definition: gpu_decoder.hh:1546
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void injectGlobalMemFence(GPUDynInstPtr gpuDynInst)
Definition: op_encodings.hh:593
gem5::Gcn3ISA::Inst_VOP3_SDST_ENC::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:1108
gem5::Gcn3ISA::Inst_SOPK::generateDisassembly
void generateDisassembly() override
Definition: op_encodings.cc:203
gem5::Gcn3ISA::Inst_VOPC
Definition: op_encodings.hh:303
gem5::Gcn3ISA::Inst_SOP2::Inst_SOP2
Inst_SOP2(InFmt_SOP2 *, const std::string &opcode)
Definition: op_encodings.cc:45
gem5::Gcn3ISA::Inst_VOP1::extData
InstFormat extData
Definition: op_encodings.hh:296
gem5::Gcn3ISA::InFmt_MIMG
Definition: gpu_decoder.hh:1418
gem5::Gcn3ISA::Inst_DS::~Inst_DS
~Inst_DS()
Definition: op_encodings.cc:1165
gem5::Gcn3ISA::Inst_SOPC::varSize
uint32_t varSize
Definition: op_encodings.hh:156
gem5::Gcn3ISA::Inst_FLAT
Definition: op_encodings.hh:786
gem5::Gcn3ISA::Inst_VOP1::Inst_VOP1
Inst_VOP1(InFmt_VOP1 *, const std::string &opcode)
Definition: op_encodings.cc:725
gem5::Gcn3ISA::Inst_VOP3_SDST_ENC::extData
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Definition: op_encodings.hh:385
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Definition: op_encodings.hh:140
gem5::Gcn3ISA::Inst_MUBUF
Definition: op_encodings.hh:527
gem5::Gcn3ISA::Inst_SMEM
Definition: op_encodings.hh:178
gem5::Gcn3ISA::BufferRsrcDescriptor::baseAddr
uint64_t baseAddr
Definition: op_encodings.hh:52
gem5::Gcn3ISA::Inst_SOP1::Inst_SOP1
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Definition: op_encodings.cc:225
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Definition: op_encodings.hh:335
gem5::Gcn3ISA::Inst_FLAT::instSize
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Definition: op_encodings.cc:1572
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Definition: op_encodings.cc:105
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Definition: op_encodings.hh:735
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Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
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Definition: gpu_static_inst.hh:49
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