gem5  v22.0.0.2
mmu.hh
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37 
38 #ifndef __ARCH_POWER_MMU_HH__
39 #define __ARCH_POWER_MMU_HH__
40 
41 #include "arch/generic/mmu.hh"
42 #include "arch/power/page_size.hh"
43 #include "params/PowerMMU.hh"
44 
45 namespace gem5
46 {
47 
48 namespace PowerISA {
49 
50 class MMU : public BaseMMU
51 {
52  public:
53  MMU(const PowerMMUParams &p)
54  : BaseMMU(p)
55  {}
56 
59  Mode mode, Request::Flags flags) override
60  {
62  PageBytes, start, size, tc, this, mode, flags));
63  }
64 };
65 
66 } // namespace PowerISA
67 } // namespace gem5
68 
69 #endif // __ARCH_POWER_MMU_HH__
gem5::PowerISA::PageBytes
const Addr PageBytes
Definition: page_size.hh:44
gem5::PowerISA::MMU::translateFunctional
TranslationGenPtr translateFunctional(Addr start, Addr size, ThreadContext *tc, Mode mode, Request::Flags flags) override
Returns a translation generator for a region of virtual addresses, instead of directly translating a ...
Definition: mmu.hh:58
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:56
gem5::BaseMMU
Definition: mmu.hh:53
gem5::Flags< FlagsType >
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
mmu.hh
flags
uint8_t flags
Definition: helpers.cc:66
gem5::PowerISA::MMU
Definition: mmu.hh:50
page_size.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::PowerISA::MMU::MMU
MMU(const PowerMMUParams &p)
Definition: mmu.hh:53
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::TranslationGenPtr
std::unique_ptr< TranslationGen > TranslationGenPtr
Definition: translation_gen.hh:128
gem5::BaseMMU::MMUTranslationGen
Definition: mmu.hh:126
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74

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