gem5  v22.0.0.1
rename_map.cc
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41 
42 #include "cpu/o3/rename_map.hh"
43 
44 #include <vector>
45 
46 #include "arch/vecregs.hh"
47 #include "cpu/o3/dyn_inst.hh"
48 #include "cpu/reg_class.hh"
49 #include "debug/Rename.hh"
50 
51 namespace gem5
52 {
53 
54 namespace o3
55 {
56 
58 {
59 }
60 
61 
62 void
63 SimpleRenameMap::init(const RegClass &reg_class, SimpleFreeList *_freeList)
64 {
65  assert(freeList == NULL);
66  assert(map.empty());
67 
68  map.resize(reg_class.numRegs());
69  freeList = _freeList;
70 }
71 
74 {
75  PhysRegIdPtr renamed_reg;
76  // Record the current physical register that is renamed to the
77  // requested architected register.
78  PhysRegIdPtr prev_reg = map[arch_reg.index()];
79 
80  if (arch_reg.is(InvalidRegClass)) {
81  assert(prev_reg->is(InvalidRegClass));
82  renamed_reg = prev_reg;
83  } else if (prev_reg->getNumPinnedWrites() > 0) {
84  // Do not rename if the register is pinned
85  assert(arch_reg.getNumPinnedWrites() == 0); // Prevent pinning the
86  // same register twice
87  DPRINTF(Rename, "Renaming pinned reg, numPinnedWrites %d\n",
88  prev_reg->getNumPinnedWrites());
89  renamed_reg = prev_reg;
90  renamed_reg->decrNumPinnedWrites();
91  } else {
92  renamed_reg = freeList->getReg();
93  map[arch_reg.index()] = renamed_reg;
94  renamed_reg->setNumPinnedWrites(arch_reg.getNumPinnedWrites());
95  renamed_reg->setNumPinnedWritesToComplete(
96  arch_reg.getNumPinnedWrites() + 1);
97  }
98 
99  DPRINTF(Rename, "Renamed reg %d to physical reg %d (%d) old mapping was"
100  " %d (%d)\n",
101  arch_reg, renamed_reg->flatIndex(), renamed_reg->flatIndex(),
102  prev_reg->flatIndex(), prev_reg->flatIndex());
103 
104  return RenameInfo(renamed_reg, prev_reg);
105 }
106 
107 
108 /**** UnifiedRenameMap methods ****/
109 
110 void
112  PhysRegFile *_regFile, UnifiedFreeList *freeList)
113 {
114  regFile = _regFile;
115 
116  for (int i = 0; i < renameMaps.size(); i++)
117  renameMaps[i].init(regClasses.at(i), &(freeList->freeLists[i]));
118 }
119 
120 bool
122 {
123  for (int i = 0; i < renameMaps.size(); i++) {
124  if (inst->numDestRegs((RegClassType)i) >
125  renameMaps[i].numFreeEntries()) {
126  return false;
127  }
128  }
129  return true;
130 }
131 
132 } // namespace o3
133 } // namespace gem5
gem5::RegId::getNumPinnedWrites
int getNumPinnedWrites() const
Definition: reg_class.hh:199
gem5::InvalidRegClass
@ InvalidRegClass
Definition: reg_class.hh:67
gem5::o3::SimpleFreeList
Free list for a single class of registers (e.g., integer or floating point).
Definition: free_list.hh:71
gem5::PhysRegId::getNumPinnedWrites
int getNumPinnedWrites() const
Definition: reg_class.hh:304
gem5::o3::SimpleRenameMap::freeList
SimpleFreeList * freeList
Pointer to the free list from which new physical registers should be allocated in rename()
Definition: rename_map.hh:86
gem5::o3::UnifiedFreeList
FreeList class that simply holds the list of free integer and floating point registers.
Definition: free_list.hh:124
std::vector< RegClass >
dyn_inst.hh
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::RefCountingPtr< DynInst >
gem5::PhysRegId::decrNumPinnedWrites
void decrNumPinnedWrites()
Definition: reg_class.hh:319
gem5::PhysRegId::flatIndex
const RegIndex & flatIndex() const
Flat index accessor.
Definition: reg_class.hh:302
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::o3::PhysRegFile
Simple physical register file class.
Definition: regfile.hh:67
gem5::o3::SimpleRenameMap::SimpleRenameMap
SimpleRenameMap()
Definition: rename_map.cc:57
std::pair
STL pair class.
Definition: stl.hh:58
rename_map.hh
gem5::PhysRegId::is
constexpr bool is(RegClassType reg_class) const
Definition: reg_class.hh:181
gem5::o3::SimpleRenameMap::rename
RenameInfo rename(const RegId &arch_reg)
Tell rename map to get a new free physical register to remap the specified architectural register.
Definition: rename_map.cc:73
gem5::o3::UnifiedRenameMap::renameMaps
std::array< SimpleRenameMap, CCRegClass+1 > renameMaps
Definition: rename_map.hh:171
gem5::RegClass
Definition: reg_class.hh:81
gem5::o3::SimpleRenameMap::RenameInfo
std::pair< PhysRegIdPtr, PhysRegIdPtr > RenameInfo
Pair of a physical register and a physical register.
Definition: rename_map.hh:105
gem5::o3::SimpleFreeList::getReg
PhysRegIdPtr getReg()
Get the next available register from the free list.
Definition: free_list.hh:95
gem5::o3::Rename
Rename handles both single threaded and SMT rename.
Definition: rename.hh:78
gem5::o3::SimpleRenameMap::init
void init(const RegClass &reg_class, SimpleFreeList *_freeList)
Because we have an array of rename maps (one per thread) in the CPU, it's awkward to initialize this ...
Definition: rename_map.cc:63
gem5::RegClassType
RegClassType
Enumerate the classes of registers.
Definition: reg_class.hh:56
gem5::o3::UnifiedFreeList::freeLists
std::array< SimpleFreeList, CCRegClass+1 > freeLists
Definition: free_list.hh:132
gem5::o3::UnifiedRenameMap::canRename
bool canRename(DynInstPtr inst) const
Return whether there are enough registers to serve the request.
Definition: rename_map.cc:121
reg_class.hh
gem5::PhysRegId::setNumPinnedWrites
void setNumPinnedWrites(int numWrites)
Definition: reg_class.hh:307
gem5::PhysRegId
Physical register ID.
Definition: reg_class.hh:245
gem5::PhysRegId::setNumPinnedWritesToComplete
void setNumPinnedWritesToComplete(int numWrites)
Definition: reg_class.hh:331
gem5::RegId::index
constexpr RegIndex index() const
Index accessors.
Definition: reg_class.hh:188
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::o3::UnifiedRenameMap::init
void init(const BaseISA::RegClasses &regClasses, PhysRegFile *_regFile, UnifiedFreeList *freeList)
Initializes rename map with given parameters.
Definition: rename_map.cc:111
gem5::RegId::is
constexpr bool is(RegClassType reg_class) const
Definition: reg_class.hh:181
gem5::o3::SimpleRenameMap::map
Arch2PhysMap map
The acutal arch-to-phys register map.
Definition: rename_map.hh:76
gem5::o3::UnifiedRenameMap::regFile
PhysRegFile * regFile
The register file object is used only to get PhysRegIdPtr on MiscRegs, as they are stored in it.
Definition: rename_map.hh:179
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126
gem5::RegClass::numRegs
constexpr size_t numRegs() const
Definition: reg_class.hh:108

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