gem5  v21.1.0.2
rename_map.cc
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41 
42 #include "cpu/o3/rename_map.hh"
43 
44 #include <vector>
45 
46 #include "arch/vecregs.hh"
47 #include "cpu/reg_class.hh"
48 #include "debug/Rename.hh"
49 
50 namespace gem5
51 {
52 
53 namespace o3
54 {
55 
57  : freeList(NULL), zeroReg(IntRegClass, 0)
58 {
59 }
60 
61 
62 void
63 SimpleRenameMap::init(const RegClassInfo &reg_class_info,
64  SimpleFreeList *_freeList)
65 {
66  assert(freeList == NULL);
67  assert(map.empty());
68 
69  map.resize(reg_class_info.size());
70  freeList = _freeList;
71  zeroReg = RegId(IntRegClass, reg_class_info.zeroReg());
72 }
73 
76 {
77  PhysRegIdPtr renamed_reg;
78  // Record the current physical register that is renamed to the
79  // requested architected register.
80  PhysRegIdPtr prev_reg = map[arch_reg.flatIndex()];
81 
82  if (arch_reg == zeroReg) {
83  assert(prev_reg->index() == zeroReg.index());
84  renamed_reg = prev_reg;
85  } else if (prev_reg->getNumPinnedWrites() > 0) {
86  // Do not rename if the register is pinned
87  assert(arch_reg.getNumPinnedWrites() == 0); // Prevent pinning the
88  // same register twice
89  DPRINTF(Rename, "Renaming pinned reg, numPinnedWrites %d\n",
90  prev_reg->getNumPinnedWrites());
91  renamed_reg = prev_reg;
92  renamed_reg->decrNumPinnedWrites();
93  } else {
94  renamed_reg = freeList->getReg();
95  map[arch_reg.flatIndex()] = renamed_reg;
96  renamed_reg->setNumPinnedWrites(arch_reg.getNumPinnedWrites());
97  renamed_reg->setNumPinnedWritesToComplete(
98  arch_reg.getNumPinnedWrites() + 1);
99  }
100 
101  DPRINTF(Rename, "Renamed reg %d to physical reg %d (%d) old mapping was"
102  " %d (%d)\n",
103  arch_reg, renamed_reg->flatIndex(), renamed_reg->flatIndex(),
104  prev_reg->flatIndex(), prev_reg->flatIndex());
105 
106  return RenameInfo(renamed_reg, prev_reg);
107 }
108 
109 
110 /**** UnifiedRenameMap methods ****/
111 
112 void
114  PhysRegFile *_regFile, UnifiedFreeList *freeList, VecMode _mode)
115 {
116  regFile = _regFile;
117  vecMode = _mode;
118 
119  intMap.init(regClasses.at(IntRegClass), &(freeList->intList));
120  floatMap.init(regClasses.at(FloatRegClass), &(freeList->floatList));
121  vecMap.init(regClasses.at(VecRegClass), &(freeList->vecList));
122  vecElemMap.init(regClasses.at(VecElemClass), &(freeList->vecElemList));
123  predMap.init(regClasses.at(VecPredRegClass), &(freeList->predList));
124  ccMap.init(regClasses.at(CCRegClass), &(freeList->ccList));
125 
126 }
127 
128 void
130 {
131  if (vecMode == enums::Elem) {
132 
133  /* The free list should currently be tracking full registers. */
134  panic_if(freeList->hasFreeVecElems(),
135  "The free list is already tracking Vec elems");
136  panic_if(freeList->numFreeVecRegs() !=
138  "The free list has lost vector registers");
139 
140  /* Split the free regs. */
141  while (freeList->hasFreeVecRegs()) {
142  auto vr = freeList->getVecReg();
143  auto range = this->regFile->getRegElemIds(vr);
144  freeList->addRegs(range.first, range.second);
145  }
146 
147  } else if (vecMode == enums::Full) {
148 
149  /* The free list should currently be tracking register elems. */
150  panic_if(freeList->hasFreeVecRegs(),
151  "The free list is already tracking full Vec");
152  panic_if(freeList->numFreeVecElems() !=
154  "The free list has lost vector register elements");
155 
156  auto range = regFile->getRegIds(VecRegClass);
157  freeList->addRegs(range.first + vecMap.numArchRegs(), range.second);
158 
159  /* We remove the elems from the free list. */
160  while (freeList->hasFreeVecElems())
161  freeList->getVecElem();
162  }
163 }
164 
165 void
167 {
168  if (newVecMode == enums::Elem && vecMode == enums::Full) {
169 
170  /* Switch to vector element rename mode. */
171  vecMode = enums::Elem;
172 
173  /* Split the mapping of each arch reg. */
174  int vec_idx = 0;
175  for (auto &vec: vecMap) {
177  auto idx = 0;
178  for (auto phys_elem = range.first;
179  phys_elem < range.second; idx++, phys_elem++) {
180 
181  setEntry(RegId(VecElemClass, vec_idx, idx), &(*phys_elem));
182  }
183  vec_idx++;
184  }
185 
186  } else if (newVecMode == enums::Full && vecMode == enums::Elem) {
187 
188  /* Switch to full vector register rename mode. */
189  vecMode = enums::Full;
190 
191  /* To rebuild the arch regs we take the easy road:
192  * 1.- Stitch the elems together into vectors.
193  * 2.- Replace the contents of the register file with the vectors
194  * 3.- Set the remaining registers as free
195  */
197  const size_t numVecs = vecMap.numArchRegs();
198  const size_t numElems = vecElemMap.numArchRegs();
199  const size_t elemsPerVec = numElems / numVecs;
200  for (uint32_t i = 0; i < numVecs; i++) {
201  TheISA::VecElem *dst = new_RF[i].as<TheISA::VecElem>();
202  for (uint32_t l = 0; l < elemsPerVec; l++) {
203  RegId s_rid(VecElemClass, i, l);
204  PhysRegIdPtr s_prid = vecElemMap.lookup(s_rid);
205  dst[l] = regFile->readVecElem(s_prid);
206  }
207  }
208 
209  for (uint32_t i = 0; i < numVecs; i++) {
210  PhysRegId pregId(VecRegClass, i, 0);
211  regFile->setVecReg(regFile->getTrueId(&pregId), new_RF[i]);
212  }
213 
214  auto range = regFile->getRegIds(VecRegClass);
215  for (uint32_t i = 0; i < numVecs; i++) {
216  setEntry(RegId(VecRegClass, i), &(*(range.first + i)));
217  }
218 
219  }
220 }
221 
222 } // namespace o3
223 } // namespace gem5
gem5::o3::UnifiedRenameMap::switchMode
void switchMode(VecMode newVecMode)
Set vector mode to Full or Elem.
Definition: rename_map.cc:166
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:62
gem5::o3::SimpleRenameMap::zeroReg
RegId zeroReg
The architectural index of the zero register.
Definition: rename_map.hh:92
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:64
gem5::o3::PhysRegFile::readVecElem
const TheISA::VecElem & readVecElem(PhysRegIdPtr phys_reg) const
Reads a vector element.
Definition: regfile.hh:230
gem5::RegId::getNumPinnedWrites
int getNumPinnedWrites() const
Definition: reg_class.hh:184
gem5::o3::UnifiedFreeList::hasFreeVecRegs
bool hasFreeVecRegs() const
Checks if there are any free vector registers.
Definition: free_list.hh:233
gem5::RegId::flatIndex
RegIndex flatIndex() const
Index flattening.
Definition: reg_class.hh:160
gem5::o3::SimpleFreeList
Free list for a single class of registers (e.g., integer or floating point).
Definition: free_list.hh:69
gem5::RegClassInfo::zeroReg
RegIndex zeroReg() const
Definition: reg_class.hh:80
gem5::PhysRegId::getNumPinnedWrites
int getNumPinnedWrites() const
Definition: reg_class.hh:272
gem5::o3::SimpleRenameMap::freeList
SimpleFreeList * freeList
Pointer to the free list from which new physical registers should be allocated in rename()
Definition: rename_map.hh:83
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:58
gem5::o3::UnifiedFreeList
FreeList class that simply holds the list of free integer and floating point registers.
Definition: free_list.hh:122
gem5::VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:63
gem5::o3::UnifiedRenameMap::intMap
SimpleRenameMap intMap
The integer register rename map.
Definition: rename_map.hh:178
gem5::o3::UnifiedFreeList::vecElemList
SimpleFreeList vecElemList
The list of free vector element registers.
Definition: free_list.hh:142
std::vector< RegClassInfo >
gem5::o3::UnifiedFreeList::hasFreeVecElems
bool hasFreeVecElems() const
Checks if there are any free vector registers.
Definition: free_list.hh:236
gem5::o3::PhysRegFile::getRegIds
IdRange getRegIds(RegClass cls)
Get the PhysRegIds of the elems of all vector registers.
Definition: regfile.cc:200
gem5::o3::UnifiedFreeList::numFreeVecElems
unsigned numFreeVecElems() const
Returns the number of free vector registers.
Definition: free_list.hh:254
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::RegId::index
RegIndex index() const
Index accessors.
Definition: reg_class.hh:154
gem5::RegClassInfo::size
size_t size() const
Definition: reg_class.hh:79
gem5::o3::SimpleRenameMap::init
void init(const RegClassInfo &reg_class_info, SimpleFreeList *_freeList)
Because we have an array of rename maps (one per thread) in the CPU, it's awkward to initialize this ...
Definition: rename_map.cc:63
gem5::o3::UnifiedRenameMap::vecElemMap
SimpleRenameMap vecElemMap
The vector element register rename map.
Definition: rename_map.hh:190
gem5::o3::PhysRegFile::getTrueId
PhysRegIdPtr getTrueId(PhysRegIdPtr reg)
Get the true physical register id.
Definition: regfile.cc:225
gem5::o3::UnifiedFreeList::floatList
SimpleFreeList floatList
The list of free floating point registers.
Definition: free_list.hh:134
gem5::o3::UnifiedRenameMap::predMap
SimpleRenameMap predMap
The predicate register rename map.
Definition: rename_map.hh:193
gem5::PhysRegId::decrNumPinnedWrites
void decrNumPinnedWrites()
Definition: reg_class.hh:287
gem5::PhysRegId::flatIndex
const RegIndex & flatIndex() const
Flat index accessor.
Definition: reg_class.hh:263
gem5::o3::UnifiedFreeList::predList
SimpleFreeList predList
The list of free predicate registers.
Definition: free_list.hh:146
gem5::o3::UnifiedRenameMap::ccMap
SimpleRenameMap ccMap
The condition-code register rename map.
Definition: rename_map.hh:184
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::o3::PhysRegFile
Simple physical register file class.
Definition: regfile.hh:66
gem5::o3::UnifiedRenameMap::switchFreeList
void switchFreeList(UnifiedFreeList *freeList)
Switch freeList of registers from Full to Elem or vicevers depending on vecMode (vector renaming mode...
Definition: rename_map.cc:129
gem5::o3::UnifiedRenameMap::vecMap
SimpleRenameMap vecMap
The vector register rename map.
Definition: rename_map.hh:187
gem5::o3::SimpleRenameMap::SimpleRenameMap
SimpleRenameMap()
Definition: rename_map.cc:56
gem5::o3::SimpleRenameMap::lookup
PhysRegIdPtr lookup(const RegId &arch_reg) const
Look up the physical register mapped to an architectural register.
Definition: rename_map.hh:128
gem5::o3::SimpleRenameMap::numArchRegs
size_t numArchRegs() const
Definition: rename_map.hh:150
gem5::o3::UnifiedFreeList::addRegs
void addRegs(InputIt first, InputIt last)
Adds a register back to the free list.
Definition: free_list.hh:265
gem5::MipsISA::l
Bitfield< 5 > l
Definition: pra_constants.hh:323
gem5::ArmISA::VecRegContainer
gem5::VecRegContainer< NumVecElemPerVecReg *sizeof(VecElem)> VecRegContainer
Definition: vec.hh:62
gem5::o3::UnifiedFreeList::numFreeVecRegs
unsigned numFreeVecRegs() const
Returns the number of free vector registers.
Definition: free_list.hh:251
gem5::o3::UnifiedRenameMap::init
void init(const BaseISA::RegClasses &regClasses, PhysRegFile *_regFile, UnifiedFreeList *freeList, VecMode _mode)
Initializes rename map with given parameters.
Definition: rename_map.cc:113
std::pair
STL pair class.
Definition: stl.hh:58
rename_map.hh
gem5::o3::SimpleRenameMap::rename
RenameInfo rename(const RegId &arch_reg)
Tell rename map to get a new free physical register to remap the specified architectural register.
Definition: rename_map.cc:75
gem5::o3::UnifiedFreeList::getVecElem
PhysRegIdPtr getVecElem()
Gets a free vector elemenet register.
Definition: free_list.hh:191
gem5::o3::PhysRegFile::numVecPhysRegs
unsigned numVecPhysRegs() const
Definition: regfile.hh:165
gem5::o3::UnifiedRenameMap::floatMap
SimpleRenameMap floatMap
The floating-point register rename map.
Definition: rename_map.hh:181
gem5::o3::SimpleRenameMap::RenameInfo
std::pair< PhysRegIdPtr, PhysRegIdPtr > RenameInfo
Pair of a physical register and a physical register.
Definition: rename_map.hh:111
gem5::o3::SimpleFreeList::getReg
PhysRegIdPtr getReg()
Get the next available register from the free list.
Definition: free_list.hh:93
gem5::o3::UnifiedFreeList::getVecReg
PhysRegIdPtr getVecReg()
Gets a free vector register.
Definition: free_list.hh:188
gem5::o3::Rename
Rename handles both single threaded and SMT rename.
Definition: rename.hh:78
gem5::o3::PhysRegFile::getRegElemIds
IdRange getRegElemIds(PhysRegIdPtr reg)
Get the PhysRegIds of the elems of a vector register.
Definition: regfile.cc:189
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:60
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::o3::UnifiedFreeList::ccList
SimpleFreeList ccList
The list of free condition-code registers.
Definition: free_list.hh:149
gem5::ArmISA::VecElem
uint32_t VecElem
Definition: vec.hh:60
gem5::PowerISA::vec
Bitfield< 25 > vec
Definition: misc.hh:108
reg_class.hh
gem5::PhysRegId::setNumPinnedWrites
void setNumPinnedWrites(int numWrites)
Definition: reg_class.hh:275
gem5::PhysRegId
Physical register ID.
Definition: reg_class.hh:198
gem5::PhysRegId::setNumPinnedWritesToComplete
void setNumPinnedWritesToComplete(int numWrites)
Definition: reg_class.hh:299
gem5::RegClassInfo
Definition: reg_class.hh:68
gem5::o3::PhysRegFile::setVecReg
void setVecReg(PhysRegIdPtr phys_reg, const TheISA::VecRegContainer &val)
Sets a vector register to the given value.
Definition: regfile.hh:302
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::o3::UnifiedFreeList::intList
SimpleFreeList intList
The list of free integer registers.
Definition: free_list.hh:131
gem5::o3::UnifiedRenameMap::vecMode
VecMode vecMode
Definition: rename_map.hh:196
gem5::PhysRegId::index
RegIndex index() const
Visible RegId methods.
Definition: reg_class.hh:154
gem5::o3::SimpleRenameMap::map
Arch2PhysMap map
The acutal arch-to-phys register map.
Definition: rename_map.hh:73
gem5::o3::PhysRegFile::numVecElemPhysRegs
unsigned numVecElemPhysRegs() const
Definition: regfile.hh:170
gem5::o3::UnifiedRenameMap::regFile
PhysRegFile * regFile
The register file object is used only to get PhysRegIdPtr on MiscRegs, as they are stored in it.
Definition: rename_map.hh:202
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88
gem5::o3::UnifiedRenameMap::VecMode
enums::VecRegRenameMode VecMode
Definition: rename_map.hh:195
gem5::o3::UnifiedRenameMap::setEntry
void setEntry(const RegId &arch_reg, PhysRegIdPtr phys_reg)
Update rename map with a specific mapping.
Definition: rename_map.hh:309
gem5::o3::UnifiedFreeList::vecList
SimpleFreeList vecList
The following two are exclusive interfaces.
Definition: free_list.hh:139

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