gem5  v22.0.0.1
mmu.hh
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37 
38 #ifndef __ARCH_RISCV_MMU_HH__
39 #define __ARCH_RISCV_MMU_HH__
40 
41 #include "arch/generic/mmu.hh"
42 #include "arch/riscv/isa.hh"
43 #include "arch/riscv/page_size.hh"
45 #include "arch/riscv/tlb.hh"
46 
47 #include "params/RiscvMMU.hh"
48 
49 namespace gem5
50 {
51 
52 namespace RiscvISA {
53 
54 class MMU : public BaseMMU
55 {
56  public:
58 
59  MMU(const RiscvMMUParams &p)
60  : BaseMMU(p), pma(p.pma_checker)
61  {}
62 
65  Mode mode, Request::Flags flags) override
66  {
68  PageBytes, start, size, tc, this, mode, flags));
69  }
70 
73  {
74  return static_cast<TLB*>(dtb)->getMemPriv(tc, mode);
75  }
76 
77  Walker *
79  {
80  return static_cast<TLB*>(dtb)->getWalker();
81  }
82 
83  void
84  takeOverFrom(BaseMMU *old_mmu) override
85  {
86  MMU *ommu = dynamic_cast<MMU*>(old_mmu);
88  pma->takeOverFrom(ommu->pma);
89 
90  }
91 
92  PMP *
94  {
95  return static_cast<TLB*>(dtb)->pmp;
96  }
97 };
98 
99 } // namespace RiscvISA
100 } // namespace gem5
101 
102 #endif // __ARCH_RISCV_MMU_HH__
gem5::PMP
This class helps to implement RISCV's physical memory protection (pmp) primitive.
Definition: pmp.hh:53
gem5::RiscvISA::MMU::getMemPriv
PrivilegeMode getMemPriv(ThreadContext *tc, BaseMMU::Mode mode)
Definition: mmu.hh:72
gem5::RiscvISA::MMU::translateFunctional
TranslationGenPtr translateFunctional(Addr start, Addr size, ThreadContext *tc, Mode mode, Request::Flags flags) override
Returns a translation generator for a region of virtual addresses, instead of directly translating a ...
Definition: mmu.hh:64
gem5::BaseMMU::dtb
BaseTLB * dtb
Definition: mmu.hh:158
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:56
gem5::RiscvISA::MMU::takeOverFrom
void takeOverFrom(BaseMMU *old_mmu) override
Definition: mmu.hh:84
gem5::RiscvISA::MMU
Definition: mmu.hh:54
gem5::RiscvISA::MMU::getDataWalker
Walker * getDataWalker()
Definition: mmu.hh:78
gem5::RiscvISA::PrivilegeMode
PrivilegeMode
Definition: isa.hh:53
pma_checker.hh
gem5::RiscvISA::MMU::MMU
MMU(const RiscvMMUParams &p)
Definition: mmu.hh:59
gem5::PMAChecker
Based on the RISC-V ISA privileged specifications V1.11, there is no implementation guidelines on the...
Definition: pma_checker.hh:60
isa.hh
gem5::BaseMMU
Definition: mmu.hh:53
gem5::Flags< FlagsType >
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::RiscvISA::MMU::getPMP
PMP * getPMP()
Definition: mmu.hh:93
tlb.hh
mmu.hh
page_size.hh
gem5::RiscvISA::PageBytes
const Addr PageBytes
Definition: page_size.hh:54
flags
uint8_t flags
Definition: helpers.cc:66
gem5::RiscvISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::RiscvISA::TLB
Definition: tlb.hh:59
gem5::RiscvISA::MMU::pma
PMAChecker * pma
Definition: mmu.hh:57
gem5::RiscvISA::Walker
Definition: pagetable_walker.hh:63
gem5::RiscvISA::mode
mode
Definition: pagetable.hh:46
gem5::PMAChecker::takeOverFrom
void takeOverFrom(PMAChecker *old)
Definition: pma_checker.cc:89
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::BaseMMU::takeOverFrom
virtual void takeOverFrom(BaseMMU *old_mmu)
Definition: mmu.cc:157
gem5::TranslationGenPtr
std::unique_ptr< TranslationGen > TranslationGenPtr
Definition: translation_gen.hh:128
gem5::BaseMMU::MMUTranslationGen
Definition: mmu.hh:126

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