mmu.hh

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#ifndef __ARCH_RISCV_MMU_HH__
#define __ARCH_RISCV_MMU_HH__
 
#include "arch/generic/mmu.hh"
#include "arch/riscv/isa.hh"
#include "arch/riscv/page_size.hh"
#include "arch/riscv/pma_checker.hh"
#include "arch/riscv/tlb.hh"
 
#include "params/RiscvMMU.hh"
 
namespace gem5
{
 
namespace RiscvISA {
 
class MMU : public BaseMMU
{
  public:
    PMAChecker *pma;
 
    MMU(const RiscvMMUParams &p)
      : BaseMMU(p), pma(p.pma_checker)
    {}
 
    TranslationGenPtr
    translateFunctional(Addr start, Addr size, ThreadContext *tc,
            Mode mode, Request::Flags flags) override
    {
        return TranslationGenPtr(new MMUTranslationGen(
                PageBytes, start, size, tc, this, mode, flags));
    }
 
    PrivilegeMode
    getMemPriv(ThreadContext *tc, BaseMMU::Mode mode)
    {
        return static_cast<TLB*>(dtb)->getMemPriv(tc, mode);
    }
 
    Walker *
    getDataWalker()
    {
        return static_cast<TLB*>(dtb)->getWalker();
    }
 
    void
    takeOverFrom(BaseMMU *old_mmu) override
    {
      MMU *ommu = dynamic_cast<MMU*>(old_mmu);
      BaseMMU::takeOverFrom(ommu);
      pma->takeOverFrom(ommu->pma);
 
    }
 
    PMP *
    getPMP()
    {
        return static_cast<TLB*>(dtb)->pmp;
    }
};
 
} // namespace RiscvISA
} // namespace gem5
 
#endif  // __ARCH_RISCV_MMU_HH__