gem5  v21.2.0.0
tlb.hh
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31 
32 #ifndef __ARCH_RISCV_TLB_HH__
33 #define __ARCH_RISCV_TLB_HH__
34 
35 #include <list>
36 
37 #include "arch/generic/tlb.hh"
38 #include "arch/riscv/isa.hh"
39 #include "arch/riscv/pagetable.hh"
41 #include "arch/riscv/regs/misc.hh"
42 #include "arch/riscv/utility.hh"
43 #include "base/statistics.hh"
44 #include "mem/request.hh"
45 #include "params/RiscvTLB.hh"
46 #include "sim/sim_object.hh"
47 
48 namespace gem5
49 {
50 
51 class ThreadContext;
52 
53 /* To maintain compatibility with other architectures, we'll
54  simply create an ITLB and DTLB that will point to the real TLB */
55 namespace RiscvISA {
56 
57 class Walker;
58 
59 class TLB : public BaseTLB
60 {
62 
63  protected:
64  size_t size;
66  TlbEntryTrie trie; // for quick access
67  EntryList freeList; // free entries
68  uint64_t lruSeq;
69 
71 
72  struct TlbStats : public statistics::Group
73  {
74  TlbStats(statistics::Group *parent);
75 
82 
86  } stats;
87 
88  public:
90  PMP *pmp;
91 
92  public:
93  typedef RiscvTLBParams Params;
94  TLB(const Params &p);
95 
96  Walker *getWalker();
97 
98  void takeOverFrom(BaseTLB *old) override {}
99 
100  TlbEntry *insert(Addr vpn, const TlbEntry &entry);
101  void flushAll() override;
102  void demapPage(Addr vaddr, uint64_t asn) override;
103 
105  BaseMMU::Mode mode, PTESv39 pte);
107 
109 
110  // Checkpointing
111  void serialize(CheckpointOut &cp) const override;
112  void unserialize(CheckpointIn &cp) override;
113 
124  Port *getTableWalkerPort() override;
125 
127 
128  Fault translateAtomic(const RequestPtr &req,
129  ThreadContext *tc, BaseMMU::Mode mode) override;
130  void translateTiming(const RequestPtr &req, ThreadContext *tc,
131  BaseMMU::Translation *translation,
132  BaseMMU::Mode mode) override;
134  BaseMMU::Mode mode) override;
136  BaseMMU::Mode mode) const override;
137 
138  private:
139  uint64_t nextSeq() { return ++lruSeq; }
140 
141  TlbEntry *lookup(Addr vpn, uint16_t asid, BaseMMU::Mode mode, bool hidden);
142 
143  void evictLRU();
144  void remove(size_t idx);
145 
146  Fault translate(const RequestPtr &req, ThreadContext *tc,
148  bool &delayed);
149  Fault doTranslate(const RequestPtr &req, ThreadContext *tc,
151  bool &delayed);
152 };
153 
154 } // namespace RiscvISA
155 } // namespace gem5
156 
157 #endif // __RISCV_MEMORY_HH__
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1930
gem5::RiscvISA::TLB::evictLRU
void evictLRU()
gem5::PMP
This class helps to implement RISCV's physical memory protection (pmp) primitive.
Definition: pmp.hh:53
gem5::RiscvISA::TLB::TlbStats::writeHits
statistics::Scalar writeHits
Definition: tlb.hh:79
gem5::RiscvISA::TLB::translateWithTLB
Addr translateWithTLB(Addr vaddr, uint16_t asid, BaseMMU::Mode mode)
Definition: tlb.cc:270
gem5::RiscvISA::TLB::pma
PMAChecker * pma
Definition: tlb.hh:89
gem5::RiscvISA::TLB::insert
TlbEntry * insert(Addr vpn, const TlbEntry &entry)
gem5::RiscvISA::TLB::TLB
TLB(const Params &p)
gem5::RiscvISA::TLB::finalizePhysical
Fault finalizePhysical(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) const override
Do post-translation physical address finalization.
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:56
gem5::RiscvISA::TLB::TlbStats::misses
statistics::Formula misses
Definition: tlb.hh:84
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::RiscvISA::TLB::tlb
std::vector< TlbEntry > tlb
Definition: tlb.hh:65
tlb.hh
gem5::RiscvISA::PrivilegeMode
PrivilegeMode
Definition: isa.hh:53
gem5::RiscvISA::TLB::createPagefault
Fault createPagefault(Addr vaddr, BaseMMU::Mode mode)
Definition: tlb.cc:257
gem5::RiscvISA::TLB::getWalker
Walker * getWalker()
pma_checker.hh
gem5::RiscvISA::TLB::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
gem5::statistics::Formula
A formula for statistics that is calculated when printed.
Definition: statistics.hh:2539
std::vector
STL vector class.
Definition: stl.hh:37
gem5::PMAChecker
Based on the RISC-V ISA privileged specifications V1.11, there is no implementation guidelines on the...
Definition: pma_checker.hh:60
gem5::RiscvISA::TLB::translate
Fault translate(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode, bool &delayed)
Definition: tlb.cc:336
isa.hh
request.hh
misc.hh
gem5::RiscvISA::TLB::doTranslate
Fault doTranslate(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode, bool &delayed)
Definition: tlb.cc:278
gem5::RiscvISA::TLB::checkPermissions
Fault checkPermissions(STATUS status, PrivilegeMode pmode, Addr vaddr, BaseMMU::Mode mode, PTESv39 pte)
Definition: tlb.cc:223
gem5::Trie< Addr, TlbEntry >
gem5::RiscvISA::TLB::TlbStats::writeMisses
statistics::Scalar writeMisses
Definition: tlb.hh:80
gem5::RiscvISA::TLB::TlbStats
Definition: tlb.hh:72
gem5::RiscvISA::TLB::EntryList
std::list< TlbEntry * > EntryList
Definition: tlb.hh:61
gem5::RiscvISA::TLB::translateAtomic
Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
sim_object.hh
gem5::RiscvISA::TlbEntry
Definition: pagetable.hh:82
gem5::RiscvISA::TLB::nextSeq
uint64_t nextSeq()
Definition: tlb.hh:139
gem5::RiscvISA::TLB::walker
Walker * walker
Definition: tlb.hh:70
gem5::RiscvISA::TLB::TlbStats::readAccesses
statistics::Scalar readAccesses
Definition: tlb.hh:78
statistics.hh
gem5::RiscvISA::TLB::TlbStats::hits
statistics::Formula hits
Definition: tlb.hh:83
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::RiscvISA::TLB::TlbStats::TlbStats
TlbStats(statistics::Group *parent)
gem5::BaseTLB
Definition: tlb.hh:58
gem5::RiscvISA::TLB::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
gem5::RiscvISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::RiscvISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::RiscvISA::asid
Bitfield< 59, 44 > asid
Definition: pagetable.hh:47
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::RiscvISA::TLB
Definition: tlb.hh:59
gem5::RiscvISA::TLB::size
size_t size
Definition: tlb.hh:64
gem5::RiscvISA::TLB::Params
RiscvTLBParams Params
Definition: tlb.hh:93
gem5::RiscvISA::TLB::TlbStats::readMisses
statistics::Scalar readMisses
Definition: tlb.hh:77
gem5::RiscvISA::TLB::getTableWalkerPort
Port * getTableWalkerPort() override
Get the table walker port.
gem5::BaseMMU::Translation
Definition: mmu.hh:58
gem5::RiscvISA::TLB::lruSeq
uint64_t lruSeq
Definition: tlb.hh:68
gem5::RiscvISA::TLB::TlbStats::readHits
statistics::Scalar readHits
Definition: tlb.hh:76
gem5::RiscvISA::TLB::translateFunctional
Fault translateFunctional(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override
gem5::RiscvISA::TLB::takeOverFrom
void takeOverFrom(BaseTLB *old) override
Take over from an old tlb context.
Definition: tlb.hh:98
gem5::RiscvISA::Walker
Definition: pagetable_walker.hh:63
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::RiscvISA::TLB::pmp
PMP * pmp
Definition: tlb.hh:90
gem5::RiscvISA::TLB::remove
void remove(size_t idx)
Definition: tlb.cc:210
gem5::RiscvISA::mode
mode
Definition: pagetable.hh:46
gem5::RiscvISA::TLB::TlbStats::accesses
statistics::Formula accesses
Definition: tlb.hh:85
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::RiscvISA::TLB::trie
TlbEntryTrie trie
Definition: tlb.hh:66
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
utility.hh
gem5::RiscvISA::TLB::lookup
TlbEntry * lookup(Addr vpn, uint16_t asid, BaseMMU::Mode mode, bool hidden)
Definition: tlb.cc:109
std::list< TlbEntry * >
gem5::RiscvISA::TLB::translateTiming
void translateTiming(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode) override
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::RiscvISA::TLB::flushAll
void flushAll() override
Remove all entries from the TLB.
gem5::RiscvISA::TLB::freeList
EntryList freeList
Definition: tlb.hh:67
gem5::RiscvISA::TLB::getMemPriv
PrivilegeMode getMemPriv(ThreadContext *tc, BaseMMU::Mode mode)
Definition: tlb.cc:326
pagetable.hh
gem5::RiscvISA::TLB::stats
gem5::RiscvISA::TLB::TlbStats stats
gem5::RiscvISA::TLB::TlbStats::writeAccesses
statistics::Scalar writeAccesses
Definition: tlb.hh:81
gem5::ArmISA::status
Bitfield< 5, 0 > status
Definition: misc_types.hh:423
gem5::RiscvISA::TLB::demapPage
void demapPage(Addr vaddr, uint64_t asn) override

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