gem5  v21.1.0.2
pagetable_walker.hh
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38 
39 #ifndef __ARCH_RISCV_TABLE_WALKER_HH__
40 #define __ARCH_RISCV_TABLE_WALKER_HH__
41 
42 #include <vector>
43 
44 #include "arch/generic/mmu.hh"
45 #include "arch/riscv/pagetable.hh"
47 #include "arch/riscv/pmp.hh"
48 #include "arch/riscv/tlb.hh"
49 #include "base/types.hh"
50 #include "mem/packet.hh"
51 #include "params/RiscvPagetableWalker.hh"
52 #include "sim/clocked_object.hh"
53 #include "sim/faults.hh"
54 #include "sim/system.hh"
55 
56 namespace gem5
57 {
58 
59 class ThreadContext;
60 
61 namespace RiscvISA
62 {
63  class Walker : public ClockedObject
64  {
65  protected:
66  // Port for accessing memory
67  class WalkerPort : public RequestPort
68  {
69  public:
70  WalkerPort(const std::string &_name, Walker * _walker) :
71  RequestPort(_name, _walker), walker(_walker)
72  {}
73 
74  protected:
76 
77  bool recvTimingResp(PacketPtr pkt);
78  void recvReqRetry();
79  };
80 
81  friend class WalkerPort;
83 
84  // State to track each walk of the page table
86  {
87  friend class Walker;
88  private:
89  enum State
90  {
94  };
95 
96  protected:
102  int level;
103  unsigned inflight;
110  SATP satp;
111  STATUS status;
114  bool timing;
115  bool retrying;
116  bool started;
117  bool squashed;
118  public:
119  WalkerState(Walker * _walker, BaseMMU::Translation *_translation,
120  const RequestPtr &_req, bool _isFunctional = false) :
121  walker(_walker), req(_req), state(Ready),
122  nextState(Ready), level(0), inflight(0),
123  translation(_translation),
124  functional(_isFunctional), timing(false),
125  retrying(false), started(false), squashed(false)
126  {
127  }
128  void initState(ThreadContext * _tc, BaseMMU::Mode _mode,
129  bool _isTiming = false);
130  Fault startWalk();
131  Fault startFunctional(Addr &addr, unsigned &logBytes);
132  bool recvPacket(PacketPtr pkt);
133  unsigned numInflight() const;
134  bool isRetrying();
135  bool wasStarted();
136  bool isTiming();
137  void retry();
138  void squash();
139  std::string name() const {return walker->name();}
140 
141  private:
142  void setupWalk(Addr vaddr);
143  Fault stepWalk(PacketPtr &write);
144  void sendPackets();
145  void endWalk();
146  Fault pageFault(bool present);
147  };
148 
149  friend class WalkerState;
150  // State for timing and atomic accesses (need multiple per walker in
151  // the case of multiple outstanding requests in timing mode)
153  // State for functional accesses (only need one of these per walker)
155 
157  {
160  senderWalk(_senderWalk) {}
161  };
162 
163  public:
164  // Kick off the state machine.
165  Fault start(ThreadContext * _tc, BaseMMU::Translation *translation,
166  const RequestPtr &req, BaseMMU::Mode mode);
168  unsigned &logBytes, BaseMMU::Mode mode);
169  Port &getPort(const std::string &if_name,
170  PortID idx=InvalidPortID) override;
171 
172  protected:
173  // The TLB we're supposed to load.
174  TLB * tlb;
177  PMP * pmp;
179 
180  // The number of outstanding walks that can be squashed per cycle.
181  unsigned numSquashable;
182 
183  // Wrapper for checking for squashes before starting a translation.
184  void startWalkWrapper();
185 
190 
191  // Functions for dealing with packets.
192  bool recvTimingResp(PacketPtr pkt);
193  void recvReqRetry();
194  bool sendTiming(WalkerState * sendingState, PacketPtr pkt);
195 
196  public:
197 
198  void setTLB(TLB * _tlb)
199  {
200  tlb = _tlb;
201  }
202 
203  using Params = RiscvPagetableWalkerParams;
204 
205  Walker(const Params &params) :
206  ClockedObject(params), port(name() + ".port", this),
207  funcState(this, NULL, NULL, true), tlb(NULL), sys(params.system),
208  pma(params.pma_checker),
209  pmp(params.pmp),
210  requestorId(sys->getRequestorId(this)),
211  numSquashable(params.num_squash_per_cycle),
213  {
214  }
215  };
216 
217 } // namespace RiscvISA
218 } // namespace gem5
219 
220 #endif // __ARCH_RISCV_PAGE_TABLE_WALKER_HH__
gem5::RiscvISA::Walker::WalkerState::functional
bool functional
Definition: pagetable_walker.hh:113
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::PMP
This class helps to implement RISCV's physical memory protection (pmp) primitive.
Definition: pmp.hh:53
gem5::RiscvISA::Walker::startWalkWrapper
void startWalkWrapper()
Definition: pagetable_walker.cc:198
gem5::RiscvISA::Walker::Params
RiscvPagetableWalkerParams Params
Definition: pagetable_walker.hh:203
gem5::RiscvISA::Walker::WalkerPort::recvTimingResp
bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
Definition: pagetable_walker.cc:105
system.hh
gem5::RiscvISA::Walker::WalkerState::req
RequestPtr req
Definition: pagetable_walker.hh:99
gem5::RiscvISA::Walker::WalkerState::Ready
@ Ready
Definition: pagetable_walker.hh:91
gem5::RiscvISA::Walker::WalkerState::writes
std::vector< PacketPtr > writes
Definition: pagetable_walker.hh:106
gem5::RiscvISA::Walker::WalkerState::wasStarted
bool wasStarted()
Definition: pagetable_walker.cc:591
gem5::RiscvISA::Walker::WalkerState::timingFault
Fault timingFault
Definition: pagetable_walker.hh:107
gem5::RiscvISA::Walker::WalkerState::State
State
Definition: pagetable_walker.hh:89
gem5::RiscvISA::Walker::WalkerState::setupWalk
void setupWalk(Addr vaddr)
Definition: pagetable_walker.cc:447
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:53
gem5::RiscvISA::Walker::startFunctional
Fault startFunctional(ThreadContext *_tc, Addr &addr, unsigned &logBytes, BaseMMU::Mode mode)
Definition: pagetable_walker.cc:97
gem5::RiscvISA::Walker::WalkerSenderState
Definition: pagetable_walker.hh:156
gem5::RiscvISA::Walker::port
WalkerPort port
Definition: pagetable_walker.hh:82
gem5::RiscvISA::Walker::WalkerState::startWalk
Fault startWalk()
Definition: pagetable_walker.cc:235
gem5::RiscvISA::Walker::Walker
Walker(const Params &params)
Definition: pagetable_walker.hh:205
gem5::RiscvISA::PrivilegeMode
PrivilegeMode
Definition: isa.hh:52
gem5::RiscvISA::Walker::WalkerState::satp
SATP satp
Definition: pagetable_walker.hh:110
gem5::RiscvISA::Walker::pma
PMAChecker * pma
Definition: pagetable_walker.hh:176
gem5::RiscvISA::Walker::WalkerState::startFunctional
Fault startFunctional(Addr &addr, unsigned &logBytes)
Definition: pagetable_walker.cc:264
gem5::RiscvISA::Walker::WalkerState::read
PacketPtr read
Definition: pagetable_walker.hh:105
pma_checker.hh
gem5::RiscvISA::Walker::WalkerState::pmode
PrivilegeMode pmode
Definition: pagetable_walker.hh:112
gem5::RiscvISA::Walker::recvReqRetry
void recvReqRetry()
Definition: pagetable_walker.cc:145
gem5::RiscvISA::Walker::WalkerState::squashed
bool squashed
Definition: pagetable_walker.hh:117
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:1003
gem5::RiscvISA::Walker::WalkerState
Definition: pagetable_walker.hh:85
std::vector
STL vector class.
Definition: stl.hh:37
gem5::RiscvISA::Walker::pmp
PMP * pmp
Definition: pagetable_walker.hh:177
gem5::RiscvISA::Walker::WalkerState::recvPacket
bool recvPacket(PacketPtr pkt)
Definition: pagetable_walker.cc:473
gem5::PMAChecker
Based on the RISC-V ISA privileged specifications V1.11, there is no implementation guidelines on the...
Definition: pma_checker.hh:60
gem5::RiscvISA::Walker::WalkerState::status
STATUS status
Definition: pagetable_walker.hh:111
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:253
gem5::RiscvISA::Walker::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: pagetable_walker.cc:173
faults.hh
gem5::RiscvISA::Walker::WalkerState::retrying
bool retrying
Definition: pagetable_walker.hh:115
gem5::RiscvISA::Walker::WalkerPort
Definition: pagetable_walker.hh:67
gem5::RiscvISA::Walker::WalkerState::mode
BaseMMU::Mode mode
Definition: pagetable_walker.hh:109
gem5::RiscvISA::Walker::WalkerState::sendPackets
void sendPackets()
Definition: pagetable_walker.cc:540
gem5::RiscvISA::Walker::numSquashable
unsigned numSquashable
Definition: pagetable_walker.hh:181
gem5::RiscvISA::Walker::start
Fault start(ThreadContext *_tc, BaseMMU::Translation *translation, const RequestPtr &req, BaseMMU::Mode mode)
Definition: pagetable_walker.cc:72
packet.hh
gem5::RiscvISA::Walker::WalkerPort::WalkerPort
WalkerPort(const std::string &_name, Walker *_walker)
Definition: pagetable_walker.hh:70
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::RiscvISA::Walker::WalkerState::translation
BaseMMU::Translation * translation
Definition: pagetable_walker.hh:108
gem5::RiscvISA::Walker::WalkerState::pageFault
Fault pageFault(bool present)
Definition: pagetable_walker.cc:610
gem5::X86ISA::present
Bitfield< 7 > present
Definition: misc.hh:998
pmp.hh
gem5::System
Definition: system.hh:77
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
tlb.hh
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::RiscvISA::TlbEntry
Definition: pagetable.hh:82
gem5::RiscvISA::Walker::funcState
WalkerState funcState
Definition: pagetable_walker.hh:154
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::RiscvISA::Walker::tlb
TLB * tlb
Definition: pagetable_walker.hh:174
gem5::RiscvISA::Walker::WalkerState::timing
bool timing
Definition: pagetable_walker.hh:114
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
mmu.hh
gem5::RiscvISA::Walker::WalkerState::entry
TlbEntry entry
Definition: pagetable_walker.hh:104
gem5::RiscvISA::Walker::startWalkWrapperEvent
EventFunctionWrapper startWalkWrapperEvent
Event used to call startWalkWrapper.
Definition: pagetable_walker.hh:189
gem5::RiscvISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::Packet::SenderState
A virtual base opaque structure used to hold state associated with the packet (e.g....
Definition: packet.hh:457
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::RiscvISA::Walker::WalkerState::walker
Walker * walker
Definition: pagetable_walker.hh:97
gem5::RiscvISA::Walker::WalkerState::isRetrying
bool isRetrying()
Definition: pagetable_walker.cc:579
gem5::RiscvISA::Walker::WalkerState::numInflight
unsigned numInflight() const
Definition: pagetable_walker.cc:573
gem5::RiscvISA::Walker::WalkerPort::recvReqRetry
void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Definition: pagetable_walker.cc:139
gem5::RiscvISA::TLB
Definition: tlb.hh:59
gem5::RiscvISA::Walker::WalkerState::inflight
unsigned inflight
Definition: pagetable_walker.hh:103
gem5::RiscvISA::Walker::WalkerState::stepWalk
Fault stepWalk(PacketPtr &write)
Definition: pagetable_walker.cc:288
gem5::ClockedObject
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Definition: clocked_object.hh:234
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::BaseMMU::Translation
Definition: mmu.hh:55
gem5::RiscvISA::Walker::WalkerState::state
State state
Definition: pagetable_walker.hh:100
gem5::RiscvISA::Walker::WalkerState::name
std::string name() const
Definition: pagetable_walker.hh:139
gem5::RiscvISA::Walker::WalkerState::Translate
@ Translate
Definition: pagetable_walker.hh:93
gem5::RiscvISA::Walker::sys
System * sys
Definition: pagetable_walker.hh:175
gem5::RiscvISA::Walker::WalkerState::endWalk
void endWalk()
Definition: pagetable_walker.cc:439
gem5::RiscvISA::Walker
Definition: pagetable_walker.hh:63
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::RiscvISA::Walker::WalkerState::nextState
State nextState
Definition: pagetable_walker.hh:101
types.hh
gem5::RiscvISA::Walker::requestorId
RequestorID requestorId
Definition: pagetable_walker.hh:178
gem5::RiscvISA::Walker::WalkerState::squash
void squash()
Definition: pagetable_walker.cc:597
gem5::RiscvISA::Walker::recvTimingResp
bool recvTimingResp(PacketPtr pkt)
Definition: pagetable_walker.cc:111
gem5::RiscvISA::mode
mode
Definition: pagetable.hh:46
clocked_object.hh
gem5::RiscvISA::Walker::WalkerState::WalkerState
WalkerState(Walker *_walker, BaseMMU::Translation *_translation, const RequestPtr &_req, bool _isFunctional=false)
Definition: pagetable_walker.hh:119
gem5::RiscvISA::Walker::sendTiming
bool sendTiming(WalkerState *sendingState, PacketPtr pkt)
Definition: pagetable_walker.cc:156
gem5::RiscvISA::Walker::WalkerState::retry
void retry()
Definition: pagetable_walker.cc:603
gem5::RiscvISA::Walker::WalkerState::Waiting
@ Waiting
Definition: pagetable_walker.hh:92
gem5::RiscvISA::Walker::WalkerState::isTiming
bool isTiming()
Definition: pagetable_walker.cc:585
gem5::RequestorID
uint16_t RequestorID
Definition: request.hh:95
gem5::RiscvISA::Walker::WalkerState::started
bool started
Definition: pagetable_walker.hh:116
std::list
STL list class.
Definition: stl.hh:51
gem5::RiscvISA::Walker::WalkerSenderState::WalkerSenderState
WalkerSenderState(WalkerState *_senderWalk)
Definition: pagetable_walker.hh:159
gem5::RiscvISA::Walker::currStates
std::list< WalkerState * > currStates
Definition: pagetable_walker.hh:152
gem5::RiscvISA::Walker::WalkerState::tc
ThreadContext * tc
Definition: pagetable_walker.hh:98
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::RiscvISA::Walker::WalkerState::level
int level
Definition: pagetable_walker.hh:102
pagetable.hh
gem5::RiscvISA::Walker::WalkerState::initState
void initState(ThreadContext *_tc, BaseMMU::Mode _mode, bool _isTiming=false)
Definition: pagetable_walker.cc:182
gem5::RiscvISA::Walker::setTLB
void setTLB(TLB *_tlb)
Definition: pagetable_walker.hh:198
gem5::RiscvISA::Walker::WalkerSenderState::senderWalk
WalkerState * senderWalk
Definition: pagetable_walker.hh:158
gem5::Named::_name
const std::string _name
Definition: named.hh:41
gem5::RiscvISA::Walker::WalkerPort::walker
Walker * walker
Definition: pagetable_walker.hh:75
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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