gem5::SparcISA::TLB Class Reference

#include <tlb.hh>

Inheritance diagram for gem5::SparcISA::TLB:

Public Types
typedef SparcTLBParams	Params
Public Types inherited from gem5::SimObject
typedef SimObjectParams	Params

Public Member Functions
TlbEntry *	lookup (Addr va, int partition_id, bool real, int context_id=0, bool update_used=true)
	lookup an entry in the TLB based on the partition id, and real bit if real is true or the partition id, and context id if real is false.
void	flushAll () override
	Remove all entries from the TLB.
	TLB (const Params &p)
void	takeOverFrom (BaseTLB *otlb) override
	Take over from an old tlb context.
void	demapPage (Addr vaddr, uint64_t asn) override
void	dumpAll ()
Fault	translateAtomic (const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override
Fault	translateFunctional (const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override
void	translateTiming (const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode) override
Fault	finalizePhysical (const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) const override
	Do post-translation physical address finalization.
Cycles	doMmuRegRead (ThreadContext *tc, Packet *pkt)
Cycles	doMmuRegWrite (ThreadContext *tc, Packet *pkt)
void	GetTsbPtr (ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
void	serialize (CheckpointOut &cp) const override
	Serialize an object.
void	unserialize (CheckpointIn &cp) override
	Unserialize an object.
uint64_t	TteRead (int entry)
	Give an entry id, read that tlb entries' tte.
Public Member Functions inherited from gem5::BaseTLB
virtual Port *	getTableWalkerPort ()
	Get the table walker port if present.
void	memInvalidate ()
	Invalidate the contents of memory buffers.
TypeTLB	type () const
BaseTLB *	nextLevel () const
Public Member Functions inherited from gem5::SimObject
const Params &	params () const
	SimObject (const Params &p)
virtual	~SimObject ()
virtual void	init ()
	init() is called after all C++ SimObjects have been created and all ports are connected.
virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint.
virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint.
virtual void	regProbePoints ()
	Register probe points for this object.
virtual void	regProbeListeners ()
	Register probe listeners for this object.
ProbeManager *	getProbeManager ()
	Get the probe manager for this object.
virtual Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID)
	Get a port with a given name and index.
virtual void	startup ()
	startup() is the final initialization call before simulation.
DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining.
virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes.
Public Member Functions inherited from gem5::EventManager
EventQueue *	eventQueue () const
void	schedule (Event &event, Tick when)
void	deschedule (Event &event)
void	reschedule (Event &event, Tick when, bool always=false)
void	schedule (Event *event, Tick when)
void	deschedule (Event *event)
void	reschedule (Event *event, Tick when, bool always=false)
void	wakeupEventQueue (Tick when=(Tick) -1)
	This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers.
void	setCurTick (Tick newVal)
	EventManager (EventManager &em)
	Event manger manages events in the event queue.
	EventManager (EventManager *em)
	EventManager (EventQueue *eq)
Public Member Functions inherited from gem5::Serializable
	Serializable ()
virtual	~Serializable ()
void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section.
void	serializeSection (CheckpointOut &cp, const std::string &name) const
void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object.
void	unserializeSection (CheckpointIn &cp, const std::string &name)
Public Member Functions inherited from gem5::Drainable
DrainState	drainState () const
	Return the current drain state of an object.
virtual void	notifyFork ()
	Notify a child process of a fork.
Public Member Functions inherited from gem5::statistics::Group
	Group (Group *parent, const char *name=nullptr)
	Construct a new statistics group.
virtual	~Group ()
virtual void	regStats ()
	Callback to set stat parameters.
virtual void	resetStats ()
	Callback to reset stats.
virtual void	preDumpStats ()
	Callback before stats are dumped.
void	addStat (statistics::Info *info)
	Register a stat with this group.
const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object.
const std::vector< Info * > &	getStats () const
	Get all stats associated with this object.
void	addStatGroup (const char *name, Group *block)
	Add a stat block as a child of this block.
const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group.
void	mergeStatGroup (Group *block)
	Merge the contents (stats & children) of a block to this block.
	Group ()=delete
	Group (const Group &)=delete
Group &	operator= (const Group &)=delete
Public Member Functions inherited from gem5::Named
	Named (const std::string &name_)
virtual	~Named ()=default
virtual std::string	name () const

Protected Types
enum	FaultTypes {   OtherFault = 0 , PrivViolation = 0x1 , SideEffect = 0x2 , AtomicToIo = 0x4 ,   IllegalAsi = 0x8 , LoadFromNfo = 0x10 , VaOutOfRange = 0x20 , VaOutOfRangeJmp = 0x40 }
enum	ContextType { Primary = 0 , Secondary = 1 , Nucleus = 2 }
enum	TsbPageSize { Ps0 , Ps1 }
typedef TlbMap::iterator	MapIter

Protected Member Functions
void	insert (Addr vpn, int partition_id, int context_id, bool real, const PageTableEntry &PTE, int entry=-1)
	Insert a PTE into the TLB.
uint64_t	TagRead (int entry)
	Given an entry id, read that tlb entries' tag.
void	demapAll (int partition_id)
	Remove all non-locked entries from the tlb that match partition id.
void	demapContext (int partition_id, int context_id)
	Remove all entries that match a given context/partition id.
void	demapPage (Addr va, int partition_id, bool real, int context_id)
	Remve all entries that match a certain partition id, (contextid), and va).
bool	validVirtualAddress (Addr va, bool am)
	Checks if the virtual address provided is a valid one.
void	writeSfsr (bool write, ContextType ct, bool se, FaultTypes ft, int asi)
void	clearUsedBits ()
void	writeTagAccess (Addr va, int context)
Fault	translateInst (const RequestPtr &req, ThreadContext *tc)
Fault	translateData (const RequestPtr &req, ThreadContext *tc, bool write)
Protected Member Functions inherited from gem5::BaseTLB
	BaseTLB (const BaseTLBParams &p)
Protected Member Functions inherited from gem5::Drainable
	Drainable ()
virtual	~Drainable ()
virtual void	drainResume ()
	Resume execution after a successful drain.
void	signalDrainDone () const
	Signal that an object is drained.

Protected Attributes
uint64_t	sfar
uint64_t	c0_tsb_ps0
uint64_t	c0_tsb_ps1
uint64_t	c0_config
uint64_t	cx_tsb_ps0
uint64_t	cx_tsb_ps1
uint64_t	cx_config
uint64_t	sfsr
uint64_t	tag_access
TlbMap	lookupTable
TlbEntry *	tlb
int	size
int	usedEntries
int	lastReplaced
uint64_t	cacheState
bool	cacheValid
std::list< TlbEntry * >	freeList
Protected Attributes inherited from gem5::BaseTLB
TypeTLB	_type
BaseTLB *	_nextLevel
Protected Attributes inherited from gem5::SimObject
const SimObjectParams &	_params
	Cached copy of the object parameters.
Protected Attributes inherited from gem5::EventManager
EventQueue *	eventq
	A pointer to this object's event queue.

Private Member Functions
void	writeSfsr (Addr a, bool write, ContextType ct, bool se, FaultTypes ft, int asi)
uint64_t	MakeTsbPtr (TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb, uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config)

Private Attributes
TlbEntry *	cacheEntry [2]
ASI	cacheAsi [2]

Friends
class	MMU

Additional Inherited Members
Static Public Member Functions inherited from gem5::SimObject
static void	serializeAll (const std::string &cpt_dir)
	Create a checkpoint by serializing all SimObjects in the system.
static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it.
static void	setSimObjectResolver (SimObjectResolver *resolver)
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints.
static SimObjectResolver *	getSimObjectResolver ()
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints.
Static Public Member Functions inherited from gem5::Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section.
static void	generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
	Generate a checkpoint file so that the serialization can be routed to it.

Detailed Description

Definition at line 53 of file tlb.hh.

Member Typedef Documentation

MapIter

typedef TlbMap::iterator gem5::SparcISA::TLB::MapIter

protected

Definition at line 72 of file tlb.hh.

Params

typedef SparcTLBParams gem5::SparcISA::TLB::Params

Definition at line 160 of file tlb.hh.

Member Enumeration Documentation

ContextType

enum gem5::SparcISA::TLB::ContextType

protected

Enumerator
Primary
Secondary
Nucleus

Definition at line 97 of file tlb.hh.

FaultTypes

enum gem5::SparcISA::TLB::FaultTypes

protected

Enumerator
OtherFault
PrivViolation
SideEffect
AtomicToIo
IllegalAsi
LoadFromNfo
VaOutOfRange
VaOutOfRangeJmp

Definition at line 85 of file tlb.hh.

TsbPageSize

enum gem5::SparcISA::TLB::TsbPageSize

protected

Enumerator
Ps0
Ps1

Definition at line 104 of file tlb.hh.

Constructor & Destructor Documentation

TLB()

gem5::SparcISA::TLB::TLB

(

const Params &

p

)

Definition at line 60 of file tlb.cc.

References c0_config, c0_tsb_ps0, c0_tsb_ps1, cacheEntry, cx_config, cx_tsb_ps0, cx_tsb_ps1, fatal, freeList, sfar, sfsr, size, tag_access, tlb, and gem5::RiscvISA::x.

Member Function Documentation

clearUsedBits()

void gem5::SparcISA::TLB::clearUsedBits ( )

protected

Definition at line 88 of file tlb.cc.

References gem5::SparcISA::TlbMap::begin(), gem5::SparcISA::TlbMap::end(), gem5::ArmISA::i, lookupTable, gem5::ArmISA::t, gem5::SparcISA::TlbEntry::used, and usedEntries.

Referenced by insert(), and lookup().

demapAll()

void gem5::SparcISA::TLB::demapAll ( int partition_id )

protected

Remove all non-locked entries from the tlb that match partition id.

Definition at line 308 of file tlb.cc.

References cacheValid, DPRINTF, gem5::SparcISA::TlbMap::erase(), freeList, lookupTable, gem5::SparcISA::TlbRange::partitionId, gem5::SparcISA::TlbEntry::range, size, tlb, gem5::SparcISA::TlbEntry::used, usedEntries, gem5::SparcISA::TlbEntry::valid, and gem5::RiscvISA::x.

Referenced by doMmuRegWrite().

demapContext()

void gem5::SparcISA::TLB::demapContext ( int partition_id, int context_id )

protected

Remove all entries that match a given context/partition id.

Definition at line 286 of file tlb.cc.

References cacheValid, DPRINTF, gem5::SparcISA::TlbMap::erase(), freeList, lookupTable, gem5::SparcISA::TlbRange::partitionId, gem5::SparcISA::TlbEntry::range, size, tlb, gem5::SparcISA::TlbEntry::used, usedEntries, gem5::SparcISA::TlbEntry::valid, and gem5::RiscvISA::x.

Referenced by doMmuRegWrite().

demapPage() [1/2]

void gem5::SparcISA::TLB::demapPage ( Addr va, int partition_id, bool real, int context_id )

protected

Remve all entries that match a certain partition id, (contextid), and va).

Definition at line 254 of file tlb.cc.

References cacheValid, gem5::SparcISA::TlbRange::contextId, DPRINTF, gem5::SparcISA::TlbMap::end(), gem5::SparcISA::TlbMap::erase(), gem5::SparcISA::TlbMap::find(), freeList, gem5::ArmISA::i, lookupTable, gem5::SparcISA::TlbRange::partitionId, gem5::SparcISA::TlbRange::real, gem5::SparcISA::TlbRange::size, usedEntries, gem5::ArmISA::va, and gem5::SparcISA::TlbRange::va.

Referenced by doMmuRegWrite().

demapPage() [2/2]

void gem5::SparcISA::TLB::demapPage ( Addr vaddr, uint64_t asn )

inlineoverridevirtual

Implements gem5::BaseTLB.

Definition at line 166 of file tlb.hh.

References panic.

doMmuRegRead()

Cycles gem5::SparcISA::TLB::doMmuRegRead	(	ThreadContext *	tc,
		Packet *	pkt )

Definition at line 956 of file tlb.cc.

References gem5::SparcISA::ASI_DMMU, gem5::SparcISA::ASI_DMMU_CTXT_NONZERO_CONFIG, gem5::SparcISA::ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0, gem5::SparcISA::ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1, gem5::SparcISA::ASI_DMMU_CTXT_ZERO_CONFIG, gem5::SparcISA::ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0, gem5::SparcISA::ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1, gem5::SparcISA::ASI_DMMU_TSB_PS0_PTR_REG, gem5::SparcISA::ASI_DMMU_TSB_PS1_PTR_REG, gem5::SparcISA::ASI_HYP_SCRATCHPAD, gem5::SparcISA::ASI_IMMU, gem5::SparcISA::ASI_IMMU_CTXT_NONZERO_CONFIG, gem5::SparcISA::ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0, gem5::SparcISA::ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1, gem5::SparcISA::ASI_IMMU_CTXT_ZERO_CONFIG, gem5::SparcISA::ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0, gem5::SparcISA::ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1, gem5::SparcISA::ASI_IMMU_TSB_PS0_PTR_REG, gem5::SparcISA::ASI_IMMU_TSB_PS1_PTR_REG, gem5::SparcISA::ASI_LSU_CONTROL_REG, gem5::SparcISA::ASI_MMU, gem5::SparcISA::ASI_QUEUE, gem5::SparcISA::ASI_SCRATCHPAD, gem5::SparcISA::ASI_SPARC_ERROR_STATUS_REG, gem5::SparcISA::ASI_SWVR_INTR_RECEIVE, gem5::SparcISA::ASI_SWVR_UDB_INTR_R, gem5::bits(), c0_config, c0_tsb_ps0, c0_tsb_ps1, gem5::BaseCPU::clearInterrupt(), cx_config, cx_tsb_ps0, cx_tsb_ps1, DPRINTF, gem5::findMsbSet(), gem5::SparcISA::Interrupts::get_vec(), gem5::Packet::getAddr(), gem5::ThreadContext::getCpuPtr(), gem5::BaseCPU::getInterruptController(), gem5::ThreadContext::getMMUPtr(), gem5::SparcISA::IT_INT_VEC, gem5::BaseMMU::itb, gem5::Packet::makeAtomicResponse(), MakeTsbPtr(), gem5::SparcISA::MISCREG_MMU_LSU_CTRL, gem5::SparcISA::MISCREG_MMU_P_CONTEXT, gem5::SparcISA::MISCREG_MMU_PART_ID, gem5::SparcISA::MISCREG_MMU_S_CONTEXT, gem5::SparcISA::MISCREG_QUEUE_CPU_MONDO_HEAD, gem5::SparcISA::MISCREG_SCRATCHPAD_R0, panic, Ps0, Ps1, gem5::ThreadContext::readMiscReg(), gem5::Packet::req, gem5::Packet::setBE(), sfar, sfsr, tag_access, and gem5::ArmISA::va.

doMmuRegWrite()

Cycles gem5::SparcISA::TLB::doMmuRegWrite	(	ThreadContext *	tc,
		Packet *	pkt )

Definition at line 1141 of file tlb.cc.

References gem5::SparcISA::ASI_DMMU, gem5::SparcISA::ASI_DMMU_CTXT_NONZERO_CONFIG, gem5::SparcISA::ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0, gem5::SparcISA::ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1, gem5::SparcISA::ASI_DMMU_CTXT_ZERO_CONFIG, gem5::SparcISA::ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0, gem5::SparcISA::ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1, gem5::SparcISA::ASI_DMMU_DEMAP, gem5::SparcISA::ASI_DTLB_DATA_ACCESS_REG, gem5::SparcISA::ASI_DTLB_DATA_IN_REG, gem5::SparcISA::ASI_HYP_SCRATCHPAD, gem5::SparcISA::ASI_IMMU, gem5::SparcISA::ASI_IMMU_CTXT_NONZERO_CONFIG, gem5::SparcISA::ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0, gem5::SparcISA::ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1, gem5::SparcISA::ASI_IMMU_CTXT_ZERO_CONFIG, gem5::SparcISA::ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0, gem5::SparcISA::ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1, gem5::SparcISA::ASI_IMMU_DEMAP, gem5::SparcISA::ASI_ITLB_DATA_ACCESS_REG, gem5::SparcISA::ASI_ITLB_DATA_IN_REG, gem5::SparcISA::ASI_LSU_CONTROL_REG, gem5::SparcISA::ASI_MMU, gem5::SparcISA::ASI_QUEUE, gem5::SparcISA::ASI_SCRATCHPAD, gem5::SparcISA::ASI_SPARC_ERROR_EN_REG, gem5::SparcISA::ASI_SPARC_ERROR_STATUS_REG, gem5::SparcISA::ASI_SWVR_INTR_RECEIVE, gem5::SparcISA::ASI_SWVR_UDB_INTR_W, gem5::bits(), c0_config, c0_tsb_ps0, c0_tsb_ps1, gem5::BaseCPU::clearInterrupt(), cx_config, cx_tsb_ps0, cx_tsb_ps1, data, demapAll(), demapContext(), demapPage(), DPRINTF, gem5::findMsbSet(), gem5::SparcISA::Interrupts::get_vec(), gem5::Packet::getAddr(), gem5::Packet::getBE(), gem5::ThreadContext::getCpuPtr(), gem5::BaseCPU::getInterruptController(), gem5::ThreadContext::getMMUPtr(), gem5::ThreadContext::getSystemPtr(), gem5::ignore(), inform, insert(), gem5::SparcISA::IT_INT_VEC, gem5::BaseMMU::itb, gem5::Packet::makeAtomicResponse(), gem5::mbits(), gem5::SparcISA::MISCREG_MMU_LSU_CTRL, gem5::SparcISA::MISCREG_MMU_P_CONTEXT, gem5::SparcISA::MISCREG_MMU_PART_ID, gem5::SparcISA::MISCREG_MMU_S_CONTEXT, gem5::SparcISA::MISCREG_QUEUE_CPU_MONDO_HEAD, gem5::SparcISA::MISCREG_SCRATCHPAD_R0, panic, gem5::SparcISA::PageTableEntry::populate(), gem5::ThreadContext::readMiscReg(), gem5::Packet::req, gem5::ThreadContext::setMiscReg(), sfsr, gem5::SparcISA::PageTableEntry::sun4u, gem5::SparcISA::PageTableEntry::sun4v, gem5::szext(), tag_access, gem5::System::threads, and gem5::ArmISA::va.

dumpAll()

void gem5::SparcISA::TLB::dumpAll

(

)

Definition at line 240 of file tlb.cc.

References gem5::SparcISA::TlbRange::contextId, DPRINTFN, gem5::ArmISA::i, gem5::SparcISA::PageTableEntry::paddr(), gem5::SparcISA::TlbEntry::pte, gem5::SparcISA::TlbEntry::range, gem5::SparcISA::TlbRange::real, size, gem5::SparcISA::TlbRange::size, tlb, gem5::SparcISA::TlbRange::va, and gem5::RiscvISA::x.

finalizePhysical()

Fault gem5::SparcISA::TLB::finalizePhysical ( const RequestPtr & req, ThreadContext * tc, BaseMMU::Mode mode ) const

overridevirtual

Do post-translation physical address finalization.

This method is used by some architectures that need post-translation massaging of physical addresses. For example, X86 uses this to remap physical addresses in the APIC range to a range of physical memory not normally available to real x86 implementations.

Parameters

req	Request to updated in-place.
tc	Thread context that created the request.
mode	Request type (read/write/execute).

Returns

A fault on failure, NoFault otherwise.

Implements gem5::BaseTLB.

Definition at line 949 of file tlb.cc.

References gem5::NoFault.

flushAll()

void gem5::SparcISA::TLB::flushAll ( )

overridevirtual

Remove all entries from the TLB.

Implements gem5::BaseTLB.

Definition at line 327 of file tlb.cc.

References cacheValid, gem5::SparcISA::TlbMap::clear(), freeList, lookupTable, size, tlb, gem5::SparcISA::TlbEntry::used, usedEntries, gem5::SparcISA::TlbEntry::valid, and gem5::RiscvISA::x.

GetTsbPtr()

void gem5::SparcISA::TLB::GetTsbPtr	(	ThreadContext *	tc,
		Addr	addr,
		int	ctx,
		Addr *	ptrs )

Definition at line 1393 of file tlb.cc.

References gem5::X86ISA::addr, c0_config, c0_tsb_ps0, c0_tsb_ps1, cx_config, cx_tsb_ps0, cx_tsb_ps1, gem5::ThreadContext::getMMUPtr(), gem5::BaseMMU::itb, MakeTsbPtr(), gem5::mbits(), Ps0, Ps1, and tag_access.

Referenced by translateFunctional().

insert()

void gem5::SparcISA::TLB::insert ( Addr vpn, int partition_id, int context_id, bool real, const PageTableEntry & PTE, int entry = -1 )

protected

Insert a PTE into the TLB.

Definition at line 102 of file tlb.cc.

References cacheValid, clearUsedBits(), gem5::SparcISA::TlbRange::contextId, DPRINTF, gem5::SparcISA::TlbMap::end(), gem5::SparcISA::TlbMap::erase(), freeList, gem5::ArmISA::i, gem5::SparcISA::TlbMap::insert(), lastReplaced, lookupTable, gem5::SparcISA::TlbRange::partitionId, gem5::SparcISA::TlbEntry::pte, gem5::SparcISA::TlbEntry::range, gem5::SparcISA::TlbRange::real, size, gem5::SparcISA::TlbRange::size, tlb, gem5::SparcISA::TlbEntry::used, usedEntries, gem5::ArmISA::va, gem5::SparcISA::TlbRange::va, gem5::SparcISA::TlbEntry::valid, and gem5::RiscvISA::x.

Referenced by doMmuRegWrite().

lookup()

TlbEntry * gem5::SparcISA::TLB::lookup	(	Addr	va,
		int	partition_id,
		bool	real,
		int	context_id = 0,
		bool	update_used = true )

lookup an entry in the TLB based on the partition id, and real bit if real is true or the partition id, and context id if real is false.

Parameters

va	the virtual address not shifted (e.g. bottom 13 bits are 0)
paritition_id	partition this entry is for
real	is this a real->phys or virt->phys translation
context_id	if this is virt->phys what context
update_used	should ew update the used bits in the entries on not useful if we are trying to do a va->pa without mucking with any state for a debug read for example.

Returns

A pointer to a tlb entry

Definition at line 196 of file tlb.cc.

References clearUsedBits(), gem5::SparcISA::TlbRange::contextId, DPRINTF, gem5::SparcISA::TlbMap::end(), gem5::SparcISA::TlbMap::find(), gem5::ArmISA::i, lookupTable, gem5::SparcISA::TlbRange::partitionId, gem5::SparcISA::TlbRange::real, size, gem5::SparcISA::TlbRange::size, gem5::ArmISA::t, usedEntries, gem5::ArmISA::va, and gem5::SparcISA::TlbRange::va.

Referenced by translateFunctional().

MakeTsbPtr()

uint64_t gem5::SparcISA::TLB::MakeTsbPtr ( TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb, uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config )

private

Definition at line 1420 of file tlb.cc.

References gem5::bits(), c0_config, gem5::ArmISA::mask, gem5::mbits(), gem5::ArmISA::ps, Ps0, Ps1, and tag_access.

Referenced by doMmuRegRead(), and GetTsbPtr().

serialize()

void gem5::SparcISA::TLB::serialize ( CheckpointOut & cp ) const

overridevirtual

Serialize an object.

Output an object's state into the current checkpoint section.

Parameters

cp	Checkpoint state

Reimplemented from gem5::SimObject.

Definition at line 1447 of file tlb.cc.

References c0_config, c0_tsb_ps0, c0_tsb_ps1, gem5::csprintf(), cx_config, cx_tsb_ps0, cx_tsb_ps1, freeList, lastReplaced, gem5::SparcISA::TlbEntry::serialize(), SERIALIZE_CONTAINER, SERIALIZE_SCALAR, sfar, sfsr, size, tag_access, tlb, usedEntries, and gem5::RiscvISA::x.

TagRead()

uint64_t gem5::SparcISA::TLB::TagRead ( int entry )

protected

Given an entry id, read that tlb entries' tag.

Definition at line 355 of file tlb.cc.

References gem5::SparcISA::TlbRange::contextId, gem5::SparcISA::TlbEntry::range, gem5::SparcISA::TlbRange::real, size, tlb, and gem5::SparcISA::TlbRange::va.

takeOverFrom()

void gem5::SparcISA::TLB::takeOverFrom ( BaseTLB * otlb )

inlineoverridevirtual

Take over from an old tlb context.

Implements gem5::BaseTLB.

Definition at line 163 of file tlb.hh.

translateAtomic()

Fault gem5::SparcISA::TLB::translateAtomic ( const RequestPtr & req, ThreadContext * tc, BaseMMU::Mode mode )

overridevirtual

Implements gem5::BaseTLB.

Definition at line 834 of file tlb.cc.

References gem5::BaseMMU::Execute, gem5::ArmISA::mode, translateData(), translateInst(), and gem5::BaseMMU::Write.

Referenced by translateTiming().

translateData()

Fault gem5::SparcISA::TLB::translateData ( const RequestPtr & req, ThreadContext * tc, bool write )

protected

Normal flow ends here.

Definition at line 234 of file tlb.cc.

References gem5::ThreadContext::getProcessPtr(), gem5::Process::pTable, and gem5::EmulationPageTable::translate().

Referenced by translateAtomic().

translateFunctional()

Fault gem5::SparcISA::TLB::translateFunctional ( const RequestPtr & req, ThreadContext * tc, BaseMMU::Mode mode )

overridevirtual

Reimplemented from gem5::BaseTLB.

Definition at line 844 of file tlb.cc.

References gem5::betoh(), gem5::bits(), gem5::System::cacheLineSize(), DPRINTF, gem5::BaseMMU::Execute, gem5::FullSystem, gem5::ThreadContext::getProcessPtr(), gem5::ThreadContext::getSystemPtr(), GetTsbPtr(), gem5::SparcISA::hpriv, lookup(), mem, gem5::SparcISA::MISCREG_TLB_DATA, gem5::ArmISA::mode, gem5::NoFault, gem5::SparcISA::PageTableEntry::populate(), gem5::Process::pTable, gem5::ThreadContext::readMiscRegNoEffect(), gem5::SparcISA::PageTableEntry::sun4v, gem5::MipsISA::tbe, gem5::EmulationPageTable::translate(), gem5::SparcISA::PageTableEntry::translate(), gem5::SparcISA::TteTag::va(), gem5::MipsISA::vaddr, gem5::SparcISA::VAddrAMask, gem5::SparcISA::TteTag::valid(), validVirtualAddress(), and gem5::RiscvISA::x.

translateInst()

Fault gem5::SparcISA::TLB::translateInst ( const RequestPtr & req, ThreadContext * tc )

protected

Definition at line 219 of file tlb.cc.

References DPRINTF, gem5::ThreadContext::getProcessPtr(), gem5::Process::pTable, gem5::EmulationPageTable::translate(), and gem5::MipsISA::vaddr.

Referenced by translateAtomic().

translateTiming()

void gem5::SparcISA::TLB::translateTiming ( const RequestPtr & req, ThreadContext * tc, BaseMMU::Translation * translation, BaseMMU::Mode mode )

overridevirtual

Implements gem5::BaseTLB.

Definition at line 941 of file tlb.cc.

References gem5::BaseMMU::Translation::finish(), gem5::ArmISA::mode, and translateAtomic().

TteRead()

uint64_t gem5::SparcISA::TLB::TteRead

(

int

entry

)

Give an entry id, read that tlb entries' tte.

Definition at line 342 of file tlb.cc.

References panic, gem5::SparcISA::TlbEntry::pte, size, and tlb.

unserialize()

void gem5::SparcISA::TLB::unserialize ( CheckpointIn & cp )

overridevirtual

Unserialize an object.

Read an object's state from the current checkpoint section.

Parameters

cp	Checkpoint state

Reimplemented from gem5::SimObject.

Definition at line 1477 of file tlb.cc.

References c0_config, c0_tsb_ps0, c0_tsb_ps1, gem5::SparcISA::TlbMap::clear(), gem5::csprintf(), cx_config, cx_tsb_ps0, cx_tsb_ps1, freeList, gem5::SparcISA::TlbMap::insert(), lastReplaced, lookupTable, panic, gem5::paramIn(), sfar, sfsr, size, tag_access, tlb, gem5::SparcISA::TlbEntry::unserialize(), UNSERIALIZE_CONTAINER, UNSERIALIZE_SCALAR, usedEntries, and gem5::RiscvISA::x.

validVirtualAddress()

bool gem5::SparcISA::TLB::validVirtualAddress ( Addr va, bool am )

protected

Checks if the virtual address provided is a valid one.

Definition at line 371 of file tlb.cc.

References gem5::SparcISA::am, gem5::SparcISA::EndVAddrHole, gem5::SparcISA::StartVAddrHole, and gem5::ArmISA::va.

Referenced by translateFunctional().

writeSfsr() [1/2]

void gem5::SparcISA::TLB::writeSfsr ( Addr a, bool write, ContextType ct, bool se, FaultTypes ft, int asi )

private

Definition at line 407 of file tlb.cc.

References gem5::ArmISA::a, DPRINTF, sfar, and writeSfsr().

writeSfsr() [2/2]

void gem5::SparcISA::TLB::writeSfsr ( bool write, ContextType ct, bool se, FaultTypes ft, int asi )

protected

Definition at line 381 of file tlb.cc.

References sfsr.

Referenced by writeSfsr().

writeTagAccess()

void gem5::SparcISA::TLB::writeTagAccess ( Addr va, int context )

protected

Definition at line 398 of file tlb.cc.

References DPRINTF, gem5::mbits(), tag_access, and gem5::ArmISA::va.

Friends And Related Symbol Documentation

MMU

friend class MMU

friend

Definition at line 55 of file tlb.hh.

Member Data Documentation

c0_config

uint64_t gem5::SparcISA::TLB::c0_config

protected

Definition at line 63 of file tlb.hh.

Referenced by doMmuRegRead(), doMmuRegWrite(), GetTsbPtr(), MakeTsbPtr(), serialize(), TLB(), and unserialize().

c0_tsb_ps0

uint64_t gem5::SparcISA::TLB::c0_tsb_ps0

protected

Definition at line 61 of file tlb.hh.

Referenced by doMmuRegRead(), doMmuRegWrite(), GetTsbPtr(), serialize(), TLB(), and unserialize().

c0_tsb_ps1

uint64_t gem5::SparcISA::TLB::c0_tsb_ps1

protected

Definition at line 62 of file tlb.hh.

Referenced by doMmuRegRead(), doMmuRegWrite(), GetTsbPtr(), serialize(), TLB(), and unserialize().

cacheAsi

ASI gem5::SparcISA::TLB::cacheAsi[2]

private

Definition at line 203 of file tlb.hh.

cacheEntry

TlbEntry* gem5::SparcISA::TLB::cacheEntry[2]

private

Definition at line 202 of file tlb.hh.

Referenced by TLB().

cacheState

uint64_t gem5::SparcISA::TLB::cacheState

protected

Definition at line 80 of file tlb.hh.

cacheValid

bool gem5::SparcISA::TLB::cacheValid

protected

Definition at line 81 of file tlb.hh.

Referenced by demapAll(), demapContext(), demapPage(), flushAll(), and insert().

cx_config

uint64_t gem5::SparcISA::TLB::cx_config

protected

Definition at line 66 of file tlb.hh.

Referenced by doMmuRegRead(), doMmuRegWrite(), GetTsbPtr(), serialize(), TLB(), and unserialize().

cx_tsb_ps0

uint64_t gem5::SparcISA::TLB::cx_tsb_ps0

protected

Definition at line 64 of file tlb.hh.

Referenced by doMmuRegRead(), doMmuRegWrite(), GetTsbPtr(), serialize(), TLB(), and unserialize().

cx_tsb_ps1

uint64_t gem5::SparcISA::TLB::cx_tsb_ps1

protected

Definition at line 65 of file tlb.hh.

Referenced by doMmuRegRead(), doMmuRegWrite(), GetTsbPtr(), serialize(), TLB(), and unserialize().

freeList

std::list<TlbEntry*> gem5::SparcISA::TLB::freeList

protected

Definition at line 83 of file tlb.hh.

Referenced by demapAll(), demapContext(), demapPage(), flushAll(), insert(), serialize(), TLB(), and unserialize().

lastReplaced

int gem5::SparcISA::TLB::lastReplaced

protected

Definition at line 78 of file tlb.hh.

Referenced by insert(), serialize(), and unserialize().

lookupTable

TlbMap gem5::SparcISA::TLB::lookupTable

protected

Definition at line 71 of file tlb.hh.

Referenced by clearUsedBits(), demapAll(), demapContext(), demapPage(), flushAll(), insert(), lookup(), and unserialize().

sfar

uint64_t gem5::SparcISA::TLB::sfar

protected

Definition at line 60 of file tlb.hh.

Referenced by doMmuRegRead(), serialize(), TLB(), unserialize(), and writeSfsr().

sfsr

uint64_t gem5::SparcISA::TLB::sfsr

protected

Definition at line 67 of file tlb.hh.

Referenced by doMmuRegRead(), doMmuRegWrite(), serialize(), TLB(), unserialize(), and writeSfsr().

size

int gem5::SparcISA::TLB::size

protected

Definition at line 76 of file tlb.hh.

Referenced by demapAll(), demapContext(), dumpAll(), flushAll(), insert(), lookup(), serialize(), TagRead(), TLB(), TteRead(), and unserialize().

tag_access

uint64_t gem5::SparcISA::TLB::tag_access

protected

Definition at line 68 of file tlb.hh.

Referenced by doMmuRegRead(), doMmuRegWrite(), GetTsbPtr(), MakeTsbPtr(), serialize(), TLB(), unserialize(), and writeTagAccess().

tlb

TlbEntry* gem5::SparcISA::TLB::tlb

protected

Definition at line 74 of file tlb.hh.

Referenced by demapAll(), demapContext(), dumpAll(), flushAll(), insert(), serialize(), TagRead(), TLB(), TteRead(), and unserialize().

usedEntries

int gem5::SparcISA::TLB::usedEntries

protected

Definition at line 77 of file tlb.hh.

Referenced by clearUsedBits(), demapAll(), demapContext(), demapPage(), flushAll(), insert(), lookup(), serialize(), and unserialize().

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The documentation for this class was generated from the following files:

• arch/sparc/tlb.hh
• arch/power/tlb.cc
• arch/sparc/tlb.cc