gem5  v22.0.0.1
tlb.hh
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28 
29 #ifndef __ARCH_SPARC_TLB_HH__
30 #define __ARCH_SPARC_TLB_HH__
31 
32 #include "arch/generic/tlb.hh"
33 #include "arch/sparc/asi.hh"
34 #include "arch/sparc/tlb_map.hh"
35 #include "base/logging.hh"
36 #include "mem/request.hh"
37 #include "params/SparcTLB.hh"
38 
39 namespace gem5
40 {
41 
42 class ThreadContext;
43 class Packet;
44 
45 namespace SparcISA
46 {
47 
48 const Addr StartVAddrHole = 0x0000800000000000ULL;
49 const Addr EndVAddrHole = 0xFFFF7FFFFFFFFFFFULL;
50 const Addr VAddrAMask = 0xFFFFFFFFULL;
51 const Addr PAddrImplMask = 0x000000FFFFFFFFFFULL;
52 
53 class TLB : public BaseTLB
54 {
55  friend class MMU;
56 
57  // TLB state
58  protected:
59  // Only used when this is the data TLB.
60  uint64_t sfar;
61  uint64_t c0_tsb_ps0;
62  uint64_t c0_tsb_ps1;
63  uint64_t c0_config;
64  uint64_t cx_tsb_ps0;
65  uint64_t cx_tsb_ps1;
66  uint64_t cx_config;
67  uint64_t sfsr;
68  uint64_t tag_access;
69 
70  protected:
72  typedef TlbMap::iterator MapIter;
73 
75 
76  int size;
79 
80  uint64_t cacheState;
81  bool cacheValid;
82 
84 
86  {
89  SideEffect = 0x2,
90  AtomicToIo = 0x4,
91  IllegalAsi = 0x8,
92  LoadFromNfo = 0x10,
93  VaOutOfRange = 0x20,
95  };
96 
98  {
99  Primary = 0,
102  };
103 
105  {
108  };
109  public:
121  TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0,
122  bool update_used = true);
123 
125  void flushAll() override;
126 
127  protected:
129  void insert(Addr vpn, int partition_id, int context_id, bool real,
130  const PageTableEntry& PTE, int entry = -1);
131 
133  uint64_t TagRead(int entry);
134 
136  void demapAll(int partition_id);
137 
139  void demapContext(int partition_id, int context_id);
140 
143  void demapPage(Addr va, int partition_id, bool real, int context_id);
144 
146  bool validVirtualAddress(Addr va, bool am);
147 
148  void writeSfsr(bool write, ContextType ct,
149  bool se, FaultTypes ft, int asi);
150 
151  void clearUsedBits();
152 
153 
154  void writeTagAccess(Addr va, int context);
155 
156  Fault translateInst(const RequestPtr &req, ThreadContext *tc);
157  Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write);
158 
159  public:
160  typedef SparcTLBParams Params;
161  TLB(const Params &p);
162 
163  void takeOverFrom(BaseTLB *otlb) override {}
164 
165  void
166  demapPage(Addr vaddr, uint64_t asn) override
167  {
168  panic("demapPage(Addr) is not implemented.\n");
169  }
170 
171  void dumpAll();
172 
174  const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override;
176  const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override;
177  void translateTiming(
178  const RequestPtr &req, ThreadContext *tc,
179  BaseMMU::Translation *translation, BaseMMU::Mode mode) override;
181  const RequestPtr &req,
182  ThreadContext *tc, BaseMMU::Mode mode) const override;
185  void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
186 
187  // Checkpointing
188  void serialize(CheckpointOut &cp) const override;
189  void unserialize(CheckpointIn &cp) override;
190 
192  uint64_t TteRead(int entry);
193 
194  private:
195  void writeSfsr(Addr a, bool write, ContextType ct,
196  bool se, FaultTypes ft, int asi);
197 
198  uint64_t MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
199  uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config);
200 
201 
204 };
205 
206 } // namespace SparcISA
207 } // namespace gem5
208 
209 #endif // __ARCH_SPARC_TLB_HH__
gem5::SparcISA::TLB::GetTsbPtr
void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
Definition: tlb.cc:1393
gem5::SparcISA::TLB::AtomicToIo
@ AtomicToIo
Definition: tlb.hh:90
gem5::SparcISA::TLB::takeOverFrom
void takeOverFrom(BaseTLB *otlb) override
Take over from an old tlb context.
Definition: tlb.hh:163
gem5::SparcISA::TLB::PrivViolation
@ PrivViolation
Definition: tlb.hh:88
gem5::SparcISA::MMU
Definition: mmu.hh:52
gem5::SparcISA::TLB::translateAtomic
Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override
Definition: tlb.cc:834
gem5::SparcISA::TLB::flushAll
void flushAll() override
Remove all entries from the TLB.
Definition: tlb.cc:327
gem5::SparcISA::VAddrAMask
const Addr VAddrAMask
Definition: tlb.hh:50
gem5::SparcISA::TLB::VaOutOfRange
@ VaOutOfRange
Definition: tlb.hh:93
gem5::SparcISA::TLB::doMmuRegWrite
Cycles doMmuRegWrite(ThreadContext *tc, Packet *pkt)
Definition: tlb.cc:1141
gem5::SparcISA::TLB::insert
void insert(Addr vpn, int partition_id, int context_id, bool real, const PageTableEntry &PTE, int entry=-1)
Insert a PTE into the TLB.
Definition: tlb.cc:102
gem5::SparcISA::StartVAddrHole
const Addr StartVAddrHole
Definition: tlb.hh:48
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:56
gem5::SparcISA::TLB::tag_access
uint64_t tag_access
Definition: tlb.hh:68
gem5::CheckpointIn
Definition: serialize.hh:68
tlb_map.hh
gem5::SparcISA::TLB::writeTagAccess
void writeTagAccess(Addr va, int context)
Definition: tlb.cc:398
gem5::SparcISA::TLB::tlb
TlbEntry * tlb
Definition: tlb.hh:74
gem5::SparcISA::TLB::LoadFromNfo
@ LoadFromNfo
Definition: tlb.hh:92
gem5::SparcISA::TLB::doMmuRegRead
Cycles doMmuRegRead(ThreadContext *tc, Packet *pkt)
Definition: tlb.cc:956
tlb.hh
gem5::ArmISA::a
Bitfield< 8 > a
Definition: misc_types.hh:66
gem5::SparcISA::TLB::lastReplaced
int lastReplaced
Definition: tlb.hh:78
gem5::SparcISA::TLB::TteRead
uint64_t TteRead(int entry)
Give an entry id, read that tlb entries' tte.
Definition: tlb.cc:342
gem5::SparcISA::TLB::TLB
TLB(const Params &p)
Definition: tlb.cc:60
gem5::SparcISA::TLB::TagRead
uint64_t TagRead(int entry)
Given an entry id, read that tlb entries' tag.
Definition: tlb.cc:355
gem5::SparcISA::TLB::Primary
@ Primary
Definition: tlb.hh:99
request.hh
gem5::SparcISA::TlbMap
Definition: tlb_map.hh:42
gem5::SparcISA::TLB::Nucleus
@ Nucleus
Definition: tlb.hh:101
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::SparcISA::TLB::cacheEntry
TlbEntry * cacheEntry[2]
Definition: tlb.hh:202
gem5::SparcISA::TLB::translateFunctional
Fault translateFunctional(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override
Definition: tlb.cc:844
gem5::SparcISA::TLB::cx_config
uint64_t cx_config
Definition: tlb.hh:66
gem5::SparcISA::TLB::FaultTypes
FaultTypes
Definition: tlb.hh:85
gem5::SparcISA::TLB::dumpAll
void dumpAll()
Definition: tlb.cc:240
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::SparcISA::TLB::c0_config
uint64_t c0_config
Definition: tlb.hh:63
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::SparcISA::TLB::Ps0
@ Ps0
Definition: tlb.hh:106
gem5::SparcISA::TLB::demapPage
void demapPage(Addr vaddr, uint64_t asn) override
Definition: tlb.hh:166
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
asi.hh
gem5::SparcISA::TLB::SideEffect
@ SideEffect
Definition: tlb.hh:89
gem5::probing::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:109
gem5::SparcISA::TLB::validVirtualAddress
bool validVirtualAddress(Addr va, bool am)
Checks if the virtual address provided is a valid one.
Definition: tlb.cc:371
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::SparcISA::TLB::cx_tsb_ps1
uint64_t cx_tsb_ps1
Definition: tlb.hh:65
gem5::SparcISA::TLB::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: tlb.cc:1477
gem5::SparcISA::TLB::translateTiming
void translateTiming(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode) override
Definition: tlb.cc:941
gem5::BaseTLB
Definition: tlb.hh:58
gem5::SparcISA::TLB::ContextType
ContextType
Definition: tlb.hh:97
gem5::SparcISA::am
Bitfield< 3 > am
Definition: misc.hh:130
gem5::SparcISA::PAddrImplMask
const Addr PAddrImplMask
Definition: tlb.hh:51
gem5::SparcISA::PageTableEntry
Definition: pagetable.hh:68
gem5::SparcISA::TLB::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: tlb.cc:1447
gem5::SparcISA::TLB::IllegalAsi
@ IllegalAsi
Definition: tlb.hh:91
gem5::SparcISA::TLB::c0_tsb_ps0
uint64_t c0_tsb_ps0
Definition: tlb.hh:61
gem5::SparcISA::TLB::sfsr
uint64_t sfsr
Definition: tlb.hh:67
gem5::SparcISA::TLB::demapContext
void demapContext(int partition_id, int context_id)
Remove all entries that match a given context/partition id.
Definition: tlb.cc:286
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::SparcISA::TLB::demapAll
void demapAll(int partition_id)
Remove all non-locked entries from the tlb that match partition id.
Definition: tlb.cc:308
gem5::SparcISA::TLB::lookup
TlbEntry * lookup(Addr va, int partition_id, bool real, int context_id=0, bool update_used=true)
lookup an entry in the TLB based on the partition id, and real bit if real is true or the partition i...
Definition: tlb.cc:196
gem5::SparcISA::TLB::cx_tsb_ps0
uint64_t cx_tsb_ps0
Definition: tlb.hh:64
gem5::ArmISA::va
Bitfield< 8 > va
Definition: misc_types.hh:276
gem5::SparcISA::TLB::Secondary
@ Secondary
Definition: tlb.hh:100
gem5::SparcISA::TLB::clearUsedBits
void clearUsedBits()
Definition: tlb.cc:88
gem5::SparcISA::TLB::c0_tsb_ps1
uint64_t c0_tsb_ps1
Definition: tlb.hh:62
gem5::BaseMMU::Translation
Definition: mmu.hh:58
gem5::SparcISA::TLB::sfar
uint64_t sfar
Definition: tlb.hh:60
gem5::SparcISA::TLB::TsbPageSize
TsbPageSize
Definition: tlb.hh:104
gem5::SparcISA::TLB::size
int size
Definition: tlb.hh:76
gem5::SparcISA::TLB::MapIter
TlbMap::iterator MapIter
Definition: tlb.hh:71
gem5::SparcISA::TLB::translateData
Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write)
Definition: tlb.cc:234
gem5::SparcISA::EndVAddrHole
const Addr EndVAddrHole
Definition: tlb.hh:49
gem5::ArmISA::ps
Bitfield< 18, 16 > ps
Definition: misc_types.hh:514
gem5::SparcISA::TLB::cacheState
uint64_t cacheState
Definition: tlb.hh:80
gem5::SparcISA::TLB::usedEntries
int usedEntries
Definition: tlb.hh:77
logging.hh
gem5::SparcISA::TLB::writeSfsr
void writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi)
Definition: tlb.cc:381
gem5::SparcISA::ASI
ASI
Definition: asi.hh:38
gem5::SparcISA::TLB::Ps1
@ Ps1
Definition: tlb.hh:107
gem5::SparcISA::TLB::Params
SparcTLBParams Params
Definition: tlb.hh:160
gem5::SparcISA::TLB::OtherFault
@ OtherFault
Definition: tlb.hh:87
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::SparcISA::TlbMap::iterator
RangeMap::iterator iterator
Definition: tlb_map.hh:49
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
std::list< TlbEntry * >
gem5::SparcISA::TLB::freeList
std::list< TlbEntry * > freeList
Definition: tlb.hh:83
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::SparcISA::TLB::finalizePhysical
Fault finalizePhysical(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) const override
Do post-translation physical address finalization.
Definition: tlb.cc:949
gem5::SparcISA::TLB::VaOutOfRangeJmp
@ VaOutOfRangeJmp
Definition: tlb.hh:94
gem5::SparcISA::TLB
Definition: tlb.hh:53
gem5::SparcISA::TLB::lookupTable
TlbMap lookupTable
Definition: tlb.hh:71
gem5::SparcISA::TLB::MakeTsbPtr
uint64_t MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb, uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config)
Definition: tlb.cc:1420
gem5::ArmISA::PTE
Definition: pagetable.hh:76
gem5::SparcISA::TLB::cacheAsi
ASI cacheAsi[2]
Definition: tlb.hh:203
gem5::SparcISA::TLB::translateInst
Fault translateInst(const RequestPtr &req, ThreadContext *tc)
Definition: tlb.cc:219
gem5::SparcISA::TlbEntry
Definition: pagetable.hh:225
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::SparcISA::TLB::cacheValid
bool cacheValid
Definition: tlb.hh:81
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::SparcISA::TLB::demapPage
void demapPage(Addr va, int partition_id, bool real, int context_id)
Remve all entries that match a certain partition id, (contextid), and va).
Definition: tlb.cc:254

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