tlb.hh

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/*
 * Copyright (c) 2006 The Regents of The University of Michigan
 * All rights reserved.
 *
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 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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#ifndef __ARCH_SPARC_TLB_HH__
#define __ARCH_SPARC_TLB_HH__
 
#include "arch/generic/tlb.hh"
#include "arch/sparc/asi.hh"
#include "arch/sparc/tlb_map.hh"
#include "base/logging.hh"
#include "mem/request.hh"
#include "params/SparcTLB.hh"
 
namespace gem5
{
 
class ThreadContext;
class Packet;
 
namespace SparcISA
{
 
const Addr StartVAddrHole = 0x0000800000000000ULL;
const Addr EndVAddrHole = 0xFFFF7FFFFFFFFFFFULL;
const Addr VAddrAMask = 0xFFFFFFFFULL;
const Addr PAddrImplMask = 0x000000FFFFFFFFFFULL;
 
class TLB : public BaseTLB
{
    friend class MMU;
 
    // TLB state
  protected:
    // Only used when this is the data TLB.
    uint64_t sfar;
    uint64_t c0_tsb_ps0;
    uint64_t c0_tsb_ps1;
    uint64_t c0_config;
    uint64_t cx_tsb_ps0;
    uint64_t cx_tsb_ps1;
    uint64_t cx_config;
    uint64_t sfsr;
    uint64_t tag_access;
 
  protected:
    TlbMap lookupTable;;
    typedef TlbMap::iterator MapIter;
 
    TlbEntry *tlb;
 
    int size;
    int usedEntries;
    int lastReplaced;
 
    uint64_t cacheState;
    bool cacheValid;
 
    std::list<TlbEntry*> freeList;
 
    enum FaultTypes
    {
        OtherFault = 0,
        PrivViolation = 0x1,
        SideEffect = 0x2,
        AtomicToIo = 0x4,
        IllegalAsi = 0x8,
        LoadFromNfo = 0x10,
        VaOutOfRange = 0x20,
        VaOutOfRangeJmp = 0x40
    };
 
    enum ContextType
    {
        Primary = 0,
        Secondary = 1,
        Nucleus = 2
    };
 
    enum TsbPageSize
    {
        Ps0,
        Ps1
    };
  public:
    TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0,
            bool update_used = true);
 
    void flushAll() override;
 
  protected:
    void insert(Addr vpn, int partition_id, int context_id, bool real,
            const PageTableEntry& PTE, int entry = -1);
 
    uint64_t TagRead(int entry);
 
    void demapAll(int partition_id);
 
    void demapContext(int partition_id, int context_id);
 
    void demapPage(Addr va, int partition_id, bool real, int context_id);
 
    bool validVirtualAddress(Addr va, bool am);
 
    void writeSfsr(bool write, ContextType ct,
            bool se, FaultTypes ft, int asi);
 
    void clearUsedBits();
 
 
    void writeTagAccess(Addr va, int context);
 
    Fault translateInst(const RequestPtr &req, ThreadContext *tc);
    Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write);
 
  public:
    typedef SparcTLBParams Params;
    TLB(const Params &p);
 
    void takeOverFrom(BaseTLB *otlb) override {}
 
    void
    demapPage(Addr vaddr, uint64_t asn) override
    {
        panic("demapPage(Addr) is not implemented.\n");
    }
 
    void dumpAll();
 
    Fault translateAtomic(
        const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override;
    Fault translateFunctional(
        const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override;
    void translateTiming(
        const RequestPtr &req, ThreadContext *tc,
        BaseMMU::Translation *translation, BaseMMU::Mode mode) override;
    Fault finalizePhysical(
        const RequestPtr &req,
        ThreadContext *tc, BaseMMU::Mode mode) const override;
    Cycles doMmuRegRead(ThreadContext *tc, Packet *pkt);
    Cycles doMmuRegWrite(ThreadContext *tc, Packet *pkt);
    void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
 
    // Checkpointing
    void serialize(CheckpointOut &cp) const override;
    void unserialize(CheckpointIn &cp) override;
 
    uint64_t TteRead(int entry);
 
  private:
    void writeSfsr(Addr a, bool write, ContextType ct,
            bool se, FaultTypes ft, int asi);
 
    uint64_t MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
        uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config);
 
 
    TlbEntry *cacheEntry[2];
    ASI cacheAsi[2];
};
 
} // namespace SparcISA
} // namespace gem5
 
#endif // __ARCH_SPARC_TLB_HH__