spatter_gen.hh

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#ifndef __CPU_TESTERS_SPATTER_GEN_SPATTER_GEN_HH__
#define __CPU_TESTERS_SPATTER_GEN_SPATTER_GEN_HH__
 
#include <queue>
#include <unordered_map>
#include <vector>
 
#include "base/statistics.hh"
#include "base/stats/group.hh"
#include "cpu/testers/spatter_gen/utility_structs.hh"
#include "enums/SpatterKernelType.hh"
#include "enums/SpatterProcessingMode.hh"
#include "mem/packet.hh"
#include "mem/port.hh"
#include "params/SpatterGen.hh"
#include "sim/clocked_object.hh"
#include "sim/eventq.hh"
 
namespace gem5
{
 
 
class SpatterGen: public ClockedObject
{
  private:
    typedef enums::SpatterKernelType SpatterKernelType;
    typedef enums::SpatterProcessingMode SpatterProcessingMode;
 
    class SpatterGenEvent : public EventFunctionWrapper
    {
      private:
        // TODO: split pending into pendingInput and pendingOutput
        enum class SleepState
        {
            AWAKE,
            ASLEEP
        };
 
        SleepState _state;
 
      public:
        SpatterGenEvent(const std::function<void(void)> &callback,
                    const std::string &name):
            EventFunctionWrapper(callback, name), _state(SleepState::AWAKE)
        {}
        // a SpatterGenEvent will only be asleep if it is pending output
        bool pending() const { return _state == SleepState::ASLEEP; }
        void sleep() { _state = SleepState::ASLEEP; }
        void wake() { _state = SleepState::AWAKE; }
    };
 
    class SpatterGenPort: public RequestPort
    {
      private:
        SpatterGen* owner;
        PacketPtr blockedPacket;
 
      public:
        SpatterGenPort(SpatterGen* owner, const std::string& name):
            RequestPort(name), owner(owner), blockedPacket(nullptr) {}
 
        void sendPacket(PacketPtr pkt);
        bool blocked() const { return blockedPacket != nullptr; }
 
      protected:
        virtual bool recvTimingResp(PacketPtr pkt) override;
        virtual void recvReqRetry() override;
    };
 
    struct SpatterGenStats: public statistics::Group
    {
        SpatterGen* spatterGen;
 
        // TODO: When we enable multiple levels of indirection, we should
        // convert this to a vector with one stat for each level of index
        statistics::Scalar numIndexReads;
        // TODO: When we enable multiple levels of indirection, we should
        // convert this to a vector with one stat for each level of index
        statistics::Scalar indexBytesRead;
        statistics::Scalar totalIndexReadLatency;
 
        statistics::Scalar numValueReads;
        statistics::Scalar numValueWrites;
        statistics::Scalar valueBytesRead;
        statistics::Scalar valueBytesWritten;
        statistics::Scalar totalValueReadLatency;
        statistics::Scalar totalValueWriteLatency;
 
        // TODO: When we enable multiple levels of indirection, we should
        // convert this to a vector with one stat for each level of index
        statistics::Histogram indexAccessLatency;
        statistics::Histogram valueAccessLatency;
        statistics::Histogram totalIndirectAccessLatency;
 
        virtual void regStats() override;
 
        SpatterGenStats(SpatterGen* spatter_gen);
    };
 
    enum class SpatterGenState
    {
        // waiting for all other cores to get to WAITING state, no accesses
        WAITING,
        // only creating intermediate and ultimate accesses, i.e. wrapping up
        DRAINING,
        // creating all kinds of accesses, initial, intermediate, and ultimate
        RUNNING
    };
 
    // non param related members
    SpatterGenState state;
    std::queue<SpatterKernel> kernels;
    std::unordered_map<RequestPtr, Tick> requestDepartureTime;
 
    RequestorID requestorId;
    int numPendingMemRequests;
 
    SpatterGenStats stats;
 
    void checkForSimExit();
 
    bool initAccessOk(int int_regs, int fp_regs, Tick when) const;
    bool interAccessOk(int int_regs, int fp_regs, Tick when) const;
    bool ultAccessOk(int int_regs, int fp_regs, Tick when) const;
 
    // param related members (not necessarily one-to-one with params)
    SpatterProcessingMode mode;
    SpatterGenPort port;
    // size of the register files,
    // for every memory instruction we need to allocate one register.
    int intRegFileSize;
    int intRegUsed;
    int fpRegFileSize;
    int fpRegUsed;
    // laterncy to generate A request
    int requestGenLatency;
    // number of requests generated per event
    int requestGenRate;
    // tracking smallest tick when at least one "AGU" is available;
    Tick firstGeneratorAvailableTime;
    // tracking the busy state of our so called "AGU"s.
    std::vector<Tick> generatorBusyUntil;
    SpatterGenEvent nextGenEvent;
    void processNextGenEvent();
    // put requests to the cache in the request buffer.
    int requestBufferEntries;
    // store request packet along with their insertion time into this queue.
    TimedQueue<PacketPtr> requestBuffer;
    // if nextGenEvent has to be schedule at tick when then schedule it.
    // this function should only be called when nextGenEvent is not pending.
    void scheduleNextGenEvent(Tick when);
 
    // bandwidth to issue memory requests to cache,
    // this is supposed to model the number of cache ports
    // we will assume it takes 1 cycle to issue memory requests
    int sendRate;
    Tick firstPortAvailableTime;
    std::vector<Tick> portBusyUntil;
    SpatterGenEvent nextSendEvent;
    void processNextSendEvent();
    // if nextSendEvent has to be schedule at tick when then schedule it.
    // this function should only be called when nextSendEvent is not pending.
    void scheduleNextSendEvent(Tick when);
 
    // put the memory responses here.
    // no need to limit the size of this buffer.
    // it's a response buffer and it will automatically
    // be limited by requestBufferEntries, intRegFileSize, fpRegFileSize
    TimedQueue<SpatterAccess*> receiveBuffer;
 
  public:
    PARAMS(SpatterGen);
    SpatterGen(const Params& params);
 
    Port&
    getPort(const std::string& if_name, PortID idx = InvalidPortID) override;
 
    virtual void startup() override;
 
    void recvReqRetry();
    bool recvTimingResp(PacketPtr pkt);
 
    // PyBindMethod to interface adding a kernel with python JSON frontend.
    void addKernel(
        uint32_t id, uint32_t delta, uint32_t count,
        SpatterKernelType type,
        size_t index_size, Addr base_index_addr,
        size_t value_size, Addr base_value_addr,
        const std::vector<uint32_t>& indices
    );
 
    void proceedPastSyncPoint();
};
 
} // namespace gem5
 
#endif // __CPU_TESTERS_SPATTER_GEN_SPATTER_GEN_HH__