gem5 v24.1.0.1
Loading...
Searching...
No Matches
tester_thread.hh
Go to the documentation of this file.
1/*
2 * Copyright (c) 2017-2021 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32/*
33 * Tester thread issues requests to and receives responses from Ruby memory
34 */
35
36#ifndef CPU_TESTERS_PROTOCOL_TESTER_TESTER_THREAD_HH_
37#define CPU_TESTERS_PROTOCOL_TESTER_TESTER_THREAD_HH_
38
39#include "base/random.hh"
44#include "mem/token_port.hh"
45#include "sim/clocked_object.hh"
46
47namespace gem5
48{
49
51{
52 public:
53 typedef TesterThreadParams Params;
54 TesterThread(const Params &p);
55 virtual ~TesterThread();
56
59
60 void wakeup();
61 void scheduleWakeup();
62 void checkDeadlock();
64
67 ProtocolTester::GMTokenPort *_tokenPort = nullptr,
68 ProtocolTester::SeqPort *_sqcPort = nullptr,
69 ProtocolTester::SeqPort *_scalarPort = nullptr);
70
71 const std::string& getName() const { return threadName; }
72
73 // must be implemented by a child class
74 virtual void hitCallback(PacketPtr pkt) = 0;
75
76 int getTesterThreadId() const { return threadId; }
77 int getNumLanes() const { return numLanes; }
78 // check if the input location would satisfy DRF constraint
79 bool checkDRF(Location atomic_loc, Location loc, bool isStore) const;
80
81 void printAllOutstandingReqs(std::stringstream& ss) const;
82
83 protected:
84 class TesterThreadEvent : public Event
85 {
86 private:
88 std::string desc;
89
90 public:
91 TesterThreadEvent(TesterThread* _thread, std::string _description)
92 : Event(CPU_Tick_Pri), thread(_thread), desc(_description)
93 {}
94 void setDesc(std::string _description) { desc = _description; }
95 void process() override { thread->wakeup(); }
96 const std::string name() const override { return desc; }
97 };
98
100
102 {
103 private:
105
106 public:
108 : Event(CPU_Tick_Pri), thread(_thread)
109 {}
110 void process() override { thread->checkDeadlock(); }
111
112 const std::string
113 name() const override
114 {
115 return "Tester deadlock check";
116 }
117 };
118
120
122 {
123 int lane;
127
128 OutstandingReq(int _lane, Location _loc, Value _val, Cycles _cycle)
129 : lane(_lane), origLoc(_loc), storedValue(_val), issueCycle(_cycle)
130 {}
131
134 };
135
137 // the unique global id of this thread
139 // width of this thread (1 for cpu thread & wf size for gpu wavefront)
141 // thread name
142 std::string threadName;
143 // pointer to the main tester
145 // pointer to the address manager
147
148 ProtocolTester::SeqPort *port; // main data port (GPU-vector data)
151 ProtocolTester::SeqPort *sqcPort; // nullptr for CPU
152
153 // a list of issued episodes sorted by time
154 // the last episode in the list is the current episode
157 // pointer to the current episode
159 // pointer to the current action
161
162 // number of outstanding requests that are waiting for their responses
166
167 // last cycle when there is an event in this thread
170
171 // a per-address list of outstanding requests
173 typedef std::unordered_map<Addr, OutstandingReqList> OutstandingReqTable;
177
178 void issueNewEpisode();
179 // check if the next action in the current episode satisfies all wait_cnt
180 // constraints and is ready to issue
181 bool isNextActionReady();
182 void issueNextAction();
183 int getTokensNeeded();
184
185 // issue Ops to Ruby memory
186 // must be implemented by a child class
187 virtual void issueLoadOps() = 0;
188 virtual void issueStoreOps() = 0;
189 virtual void issueAtomicOps() = 0;
190 virtual void issueAcquireOp() = 0;
191 virtual void issueReleaseOp() = 0;
192
193 // add an outstanding request to its corresponding table
195 int lane, Location loc,
197
198 // pop an outstanding request from the input table
200 Addr address);
201
202 // validate all atomic responses
203 void validateAtomicResp(Location loc, int lane, Value ret_val);
204 // validate all Load responses
205 void validateLoadResp(Location loc, int lane, Value ret_val);
206
208 std::stringstream& ss) const;
209
210 std::string printAddress(Addr addr) const;
211
212 private:
214};
215
216} // namespace gem5
217
218#endif /* CPU_TESTERS_PROTOCOL_TESTER_TESTER_THREAD_HH_ */
static const int INVALID_VALUE
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Cycles is a wrapper class for representing cycle counts, i.e.
Definition types.hh:79
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition packet.hh:295
std::shared_ptr< Random > RandomPtr
Definition random.hh:65
static RandomPtr genRandom()
Definition random.hh:68
DeadlockCheckEvent(TesterThread *_thread)
const std::string name() const override
void setDesc(std::string _description)
const std::string name() const override
TesterThreadEvent(TesterThread *_thread, std::string _description)
AddressManager * addrManager
AddressManager::Value Value
void attachTesterThreadToPorts(ProtocolTester *_tester, ProtocolTester::SeqPort *_port, ProtocolTester::GMTokenPort *_tokenPort=nullptr, ProtocolTester::SeqPort *_sqcPort=nullptr, ProtocolTester::SeqPort *_scalarPort=nullptr)
virtual void issueReleaseOp()=0
OutstandingReqTable outstandingAtomics
AddressManager::Location Location
void scheduleDeadlockCheckEvent()
void validateAtomicResp(Location loc, int lane, Value ret_val)
ProtocolTester * tester
ProtocolTester::SeqPort * port
bool checkDRF(Location atomic_loc, Location loc, bool isStore) const
int getNumLanes() const
void printAllOutstandingReqs(std::stringstream &ss) const
DeadlockCheckEvent deadlockCheckEvent
virtual void issueAcquireOp()=0
ProtocolTester::SeqPort * scalarPort
OutstandingReqTable outstandingStores
void addOutstandingReqs(OutstandingReqTable &req_table, Addr addr, int lane, Location loc, Value stored_val=AddressManager::INVALID_VALUE)
virtual void issueStoreOps()=0
OutstandingReqTable outstandingLoads
ProtocolTester::GMTokenPort * tokenPort
EpisodeHistory episodeHistory
OutstandingReq popOutstandingReq(OutstandingReqTable &req_table, Addr address)
const Episode::Action * curAction
virtual void issueAtomicOps()=0
ProtocolTester::SeqPort * sqcPort
void printOutstandingReqs(const OutstandingReqTable &table, std::stringstream &ss) const
TesterThreadParams Params
Random::RandomPtr rng
virtual void issueLoadOps()=0
std::unordered_map< Addr, OutstandingReqList > OutstandingReqTable
std::vector< Episode * > EpisodeHistory
virtual void hitCallback(PacketPtr pkt)=0
TesterThreadEvent threadEvent
std::vector< OutstandingReq > OutstandingReqList
const std::string & getName() const
int getTesterThreadId() const
std::string printAddress(Addr addr) const
void validateLoadResp(Location loc, int lane, Value ret_val)
STL vector class.
Definition stl.hh:37
ClockedObject declaration and implementation.
static const Priority CPU_Tick_Pri
CPU ticks must come after other associated CPU events (such as writebacks).
Definition eventq.hh:207
Bitfield< 21 > ss
Definition misc_types.hh:60
Bitfield< 0 > p
Bitfield< 3 > addr
Definition types.hh:84
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
OutstandingReq(int _lane, Location _loc, Value _val, Cycles _cycle)

Generated on Mon Jan 13 2025 04:28:32 for gem5 by doxygen 1.9.8