gem5  v22.0.0.1
tme64ruby.cc
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37 
38 #include "arch/arm/faults.hh"
39 #include "arch/arm/htm.hh"
40 #include "arch/arm/insts/tme64.hh"
42 #include "debug/ArmTme.hh"
43 #include "mem/packet_access.hh"
44 #include "mem/request.hh"
45 
46 namespace gem5
47 {
48 
49 using namespace ArmISA;
50 
51 namespace ArmISAInst {
52 
53 Fault
54 Tstart64::initiateAcc(ExecContext *xc,
55  Trace::InstRecord *traceData) const
56 {
57  Fault fault = NoFault;
58  const uint64_t htm_depth = xc->getHtmTransactionalDepth();
59 
60  DPRINTF(ArmTme, "tme depth is %d\n", htm_depth);
61 
62  // Maximum TME nesting depth exceeded
63  if (htm_depth > ArmISA::HTMCheckpoint::MAX_HTM_DEPTH) {
64  const uint64_t htm_uid = xc->getHtmTransactionUid();
65  fault = std::make_shared<GenericHtmFailureFault>(
67  }
68 
69  if (fault == NoFault) {
70  Request::Flags memAccessFlags =
72 
73  // Nested transaction start/stops never leave the core.
74  // These Requests are marked as NO_ACCESS to indicate that the request
75  // should not be sent to the cache controller.
76  if (htm_depth > 1) {
77  memAccessFlags = memAccessFlags | Request::NO_ACCESS;
78  }
79 
80  fault = xc->initiateMemMgmtCmd(memAccessFlags);
81  }
82 
83  return fault;
84 }
85 
86 Fault
87 Tstart64::completeAcc(PacketPtr pkt, ExecContext *xc,
88  Trace::InstRecord *traceData) const
89 {
90  Fault fault = NoFault;
91  uint64_t Mem;
92  uint64_t Dest64 = 0;
93  ThreadContext *tc = xc->tcBase();
94  const uint64_t htm_depth = xc->getHtmTransactionalDepth();
95 
96  getMemLE(pkt, Mem, traceData);
97 
98  // sanity check
99  if (Mem != 0) {
100  fault = std::make_shared<IllegalInstSetStateFault>();
101  }
102 
103  // sanity check
104  if (!xc->inHtmTransactionalState()) {
105  fault = std::make_shared<IllegalInstSetStateFault>();
106  }
107 
108  if (fault == NoFault) {
109  Dest64 = 0x0; // tstart returns 0 on success
110 
111  // checkpointing occurs in the outer transaction only
112  if (htm_depth == 1) {
113  BaseHTMCheckpointPtr& cpt = xc->tcBase()->getHtmCheckpointPtr();
114 
115  HTMCheckpoint *armcpt =
116  dynamic_cast<HTMCheckpoint*>(cpt.get());
117  assert(armcpt != nullptr);
118 
119  armcpt->save(tc);
120  armcpt->destinationRegister(dest);
121 
122  tc->getIsaPtr()->globalClearExclusive();
123  }
124 
125  xc->setRegOperand(this, 0, Dest64 & mask(intWidth));
126 
127 
128  uint64_t final_val = Dest64;
129  if (traceData) { traceData->setData(final_val); }
130  }
131 
132  return fault;
133 }
134 
135 Fault
136 Ttest64::execute(ExecContext *xc, Trace::InstRecord *traceData) const
137 {
138  Fault fault = NoFault;
139  uint64_t Dest64 = 0;
140  const uint64_t htm_depth = xc->getHtmTransactionalDepth();
141 
142  // sanity check
143  if (htm_depth > ArmISA::HTMCheckpoint::MAX_HTM_DEPTH) {
144  fault = std::make_shared<IllegalInstSetStateFault>();
145  }
146 
147  Dest64 = htm_depth;
148 
149 
150  // sanity check
151  if (Dest64 == 0)
152  assert(!xc->inHtmTransactionalState());
153  else
154  assert(xc->inHtmTransactionalState());
155 
156  if (fault == NoFault) {
157  uint64_t final_val = Dest64;
158  xc->setRegOperand(this, 0, Dest64 & mask(intWidth));
159  if (traceData) { traceData->setData(final_val); }
160  }
161 
162  return fault;
163 }
164 
165 Fault
166 Tcancel64::initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const
167 {
168  Fault fault = NoFault;
169 
170  // sanity check
171  if (!xc->inHtmTransactionalState()) {
172  fault = std::make_shared<IllegalInstSetStateFault>();
173  }
174 
175  Request::Flags memAccessFlags =
177 
178  fault = xc->initiateMemMgmtCmd(memAccessFlags);
179 
180  return fault;
181 }
182 
183 Fault
184 Tcancel64::completeAcc(PacketPtr pkt, ExecContext *xc,
185  Trace::InstRecord *traceData) const
186 {
187  Fault fault = NoFault;
188  uint64_t Mem;
189 
190  getMemLE(pkt, Mem, traceData);
191 
192  // sanity check
193  if (Mem != 0) {
194  fault = std::make_shared<IllegalInstSetStateFault>();
195  }
196 
197  if (fault == NoFault) {
198  auto tme_checkpoint = static_cast<HTMCheckpoint*>(
199  xc->tcBase()->getHtmCheckpointPtr().get());
200  tme_checkpoint->cancelReason(imm);
201 
202  fault = std::make_shared<GenericHtmFailureFault>(
203  xc->getHtmTransactionUid(),
205  }
206 
207  return fault;
208 }
209 
210 Fault
211 MicroTcommit64::initiateAcc(ExecContext *xc,
212  Trace::InstRecord *traceData) const
213 {
214  Fault fault = NoFault;
215  const uint64_t htm_depth = xc->getHtmTransactionalDepth();
216 
217  // sanity check
218  if (!xc->inHtmTransactionalState()) {
219  fault = std::make_shared<IllegalInstSetStateFault>();
220  }
221 
222  DPRINTF(ArmTme, "tme depth is %d\n", htm_depth);
223 
224  Request::Flags memAccessFlags =
226 
227  // Nested transaction start/stops never leave the core.
228  // These Requests are marked as NO_ACCESS to indicate that the request
229  // should not be sent to the cache controller.
230  if (htm_depth > 1) {
231  memAccessFlags = memAccessFlags | Request::NO_ACCESS;
232  }
233 
234  fault = xc->initiateMemMgmtCmd(memAccessFlags);
235 
236  return fault;
237 }
238 
239 Fault
240 MicroTcommit64::completeAcc(PacketPtr pkt, ExecContext *xc,
241  Trace::InstRecord *traceData) const
242 {
243  Fault fault = NoFault;
244  uint64_t Mem;
245  ThreadContext *tc = xc->tcBase();
246  const uint64_t htm_depth = xc->getHtmTransactionalDepth();
247 
248  getMemLE(pkt, Mem, traceData);
249 
250  // sanity check
251  if (Mem != 0) {
252  fault = std::make_shared<IllegalInstSetStateFault>();
253  }
254 
255  if (fault == NoFault) {
256  if (htm_depth == 1) {
257  auto tme_checkpoint = static_cast<HTMCheckpoint*>(
258  xc->tcBase()->getHtmCheckpointPtr().get());
259 
260  assert(tme_checkpoint);
261  assert(tme_checkpoint->valid());
262 
263  tme_checkpoint->reset();
264  tc->getIsaPtr()->globalClearExclusive();
265  }
266  }
267 
268  return fault;
269 }
270 
271 } // namespace ArmISAInst
272 } // namespace gem5
gem5::HtmFailureFaultCause::NEST
@ NEST
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:253
gem5::BaseHTMCheckpointPtr
std::unique_ptr< BaseHTMCheckpoint > BaseHTMCheckpointPtr
Definition: htm.hh:125
gem5::ArmISAInst::Tstart64::initiateAcc
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const
Definition: tme64classic.cc:49
gem5::Request::HTM_CANCEL
@ HTM_CANCEL
The request cancels a HTM transaction.
Definition: request.hh:213
memhelpers.hh
gem5::ArmISAInst::Tcancel64::initiateAcc
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const
Definition: tme64classic.cc:76
gem5::Request::NO_ACCESS
@ NO_ACCESS
The request should not cause a memory access.
Definition: request.hh:146
gem5::Request::PHYSICAL
@ PHYSICAL
The virtual address is also the physical address.
Definition: request.hh:117
tme64.hh
gem5::HtmFailureFaultCause::EXPLICIT
@ EXPLICIT
gem5::Request::HTM_COMMIT
@ HTM_COMMIT
The request commits a HTM transaction.
Definition: request.hh:210
request.hh
gem5::ArmISA::HTMCheckpoint::MAX_HTM_DEPTH
const static int MAX_HTM_DEPTH
Definition: htm.hh:65
gem5::PacketPtr
Packet * PacketPtr
Definition: thread_context.hh:76
gem5::Request::Flags
gem5::Flags< FlagsType > Flags
Definition: request.hh:102
htm.hh
gem5::ArmISAInst::Ttest64::execute
Fault execute(ExecContext *, Trace::InstRecord *) const
Definition: tme64classic.cc:67
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::ArmISAInst::Tcancel64::completeAcc
Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const
Definition: tme64classic.cc:85
gem5::ArmISA::mask
Bitfield< 3, 0 > mask
Definition: pcstate.hh:63
gem5::ArmISAInst::Tstart64::completeAcc
Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const
Definition: tme64classic.cc:58
gem5::Request::HTM_START
@ HTM_START
hardware transactional memory
Definition: request.hh:207
faults.hh
packet_access.hh
gem5::Request::STRICT_ORDER
@ STRICT_ORDER
The request is required to be strictly ordered by CPU models and is non-speculative.
Definition: request.hh:135
gem5::ArmISA::imm
Bitfield< 7, 0 > imm
Definition: types.hh:132
gem5::getMemLE
void getMemLE(PacketPtr pkt, MemT &mem, Trace::InstRecord *traceData)
Definition: memhelpers.hh:87
gem5::ArmISAInst::MicroTcommit64::initiateAcc
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const
Definition: tme64classic.cc:94
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::ArmISAInst::MicroTcommit64::completeAcc
Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const
Definition: tme64classic.cc:103

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