gem5  v21.1.0.2
tme64.hh
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37 
38 #ifndef __ARCH_ARM_INSTS_TME64_HH__
39 #define __ARCH_ARM_INSTS_TME64_HH__
40 
44 
45 namespace gem5
46 {
47 
48 namespace ArmISAInst {
49 
51 {
52  protected:
54  OpClass __opClass)
55  : ArmISA::MicroOp(mnem, machInst, __opClass)
56  {}
57 };
58 
60 {
61  protected:
63  OpClass __opClass) :
64  MicroTmeOp(mnem, machInst, __opClass)
65  {}
66 
67  std::string generateDisassembly(Addr pc,
68  const loader::SymbolTable *symtab) const;
69 };
70 
72 {
73  protected:
74  uint64_t imm;
75 
77  OpClass __opClass, uint64_t _imm)
78  : ArmISA::ArmStaticInst(mnem, machInst, __opClass),
79  imm(_imm)
80  {}
81 
82  std::string generateDisassembly(Addr pc,
83  const loader::SymbolTable *symtab) const;
84 };
85 
87 {
88  protected:
89  ArmISA::IntRegIndex dest;
90 
92  OpClass __opClass, ArmISA::IntRegIndex _dest)
93  : ArmISA::ArmStaticInst(mnem, machInst, __opClass),
94  dest(_dest)
95  {}
96 
97  std::string generateDisassembly(Addr pc,
98  const loader::SymbolTable *symtab) const;
99 };
100 
101 class Tstart64 : public TmeRegNone64
102 {
103  private:
105 
106  public:
107  Tstart64(ArmISA::ExtMachInst, ArmISA::IntRegIndex);
108 
112 };
113 
114 class Ttest64 : public TmeRegNone64
115 {
116  private:
118 
119  public:
120  Ttest64(ArmISA::ExtMachInst, ArmISA::IntRegIndex);
121 
123 };
124 
125 class Tcancel64 : public TmeImmOp64
126 {
127  public:
128  Tcancel64(ArmISA::ExtMachInst, uint64_t);
129 
133 };
134 
136 {
137  public:
139 
143 };
144 
146 {
147  public:
149 
153 };
154 
155 
157 {
158  protected:
159  MacroTmeOp(const char *mnem, ArmISA::ExtMachInst _machInst,
160  OpClass __opClass);
161 };
162 
163 class Tcommit64 : public MacroTmeOp
164 {
165  public:
166  Tcommit64(ArmISA::ExtMachInst _machInst);
167 };
168 
169 } // namespace ArmISAInst
170 } // namespace gem5
171 
172 #endif
gem5::ArmISAInst::Tstart64::initiateAcc
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const
Definition: tme64classic.cc:49
gem5::ArmISAInst::Tcancel64::initiateAcc
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const
Definition: tme64classic.cc:76
gem5::ArmISA::ArmStaticInst
Definition: static_inst.hh:63
gem5::ArmISAInst::Tstart64::Tstart64
Tstart64(ArmISA::ExtMachInst, ArmISA::IntRegIndex)
Definition: tme64.cc:120
gem5::ArmISA::MicroOp
Base class for Memory microops.
Definition: macromem.hh:68
gem5::ArmISAInst::Tcommit64::Tcommit64
Tcommit64(ArmISA::ExtMachInst _machInst)
Definition: tme64.cc:241
gem5::ArmISAInst::MacroTmeOp::MacroTmeOp
MacroTmeOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass)
Definition: tme64.cc:201
gem5::ArmISAInst::MicroTfence64::completeAcc
Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const
Definition: tme64.cc:112
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::ArmISAInst::MicroTcommit64::execute
Fault execute(ExecContext *, Trace::InstRecord *) const
Definition: tme64.cc:234
gem5::ArmISAInst::MicroTfence64::execute
Fault execute(ExecContext *, Trace::InstRecord *) const
Definition: tme64.cc:96
gem5::ArmISAInst::MicroTcommit64::MicroTcommit64
MicroTcommit64(ArmISA::ExtMachInst)
Definition: tme64.cc:217
gem5::ArmISAInst::Ttest64
Definition: tme64.hh:114
gem5::ArmISA::ArmStaticInst::machInst
ExtMachInst machInst
Definition: static_inst.hh:149
gem5::ArmISAInst::Ttest64::destRegIdxArr
RegId destRegIdxArr[1]
Definition: tme64.hh:117
macromem.hh
gem5::ArmISAInst::Ttest64::Ttest64
Ttest64(ArmISA::ExtMachInst, ArmISA::IntRegIndex)
Definition: tme64.cc:154
gem5::ArmISAInst::MicroTfence64
Definition: tme64.hh:135
gem5::ArmISAInst::TmeImmOp64::TmeImmOp64
TmeImmOp64(const char *mnem, ArmISA::ExtMachInst machInst, OpClass __opClass, uint64_t _imm)
Definition: tme64.hh:76
gem5::ArmISAInst::Tcancel64::execute
Fault execute(ExecContext *, Trace::InstRecord *) const
Definition: tme64.cc:193
gem5::ArmISAInst::Tstart64::destRegIdxArr
RegId destRegIdxArr[1]
Definition: tme64.hh:104
gem5::ArmISAInst::Ttest64::execute
Fault execute(ExecContext *, Trace::InstRecord *) const
Definition: tme64classic.cc:67
gem5::ArmISAInst::Tcancel64
Definition: tme64.hh:125
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::ArmISAInst::TmeImmOp64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
Internal function to generate disassembly string.
Definition: tme64.cc:52
gem5::ArmISAInst::Tcommit64
Definition: tme64.hh:163
gem5::MipsISA::ExtMachInst
uint64_t ExtMachInst
Definition: types.hh:43
gem5::ArmISAInst::TmeRegNone64::dest
ArmISA::IntRegIndex dest
Definition: tme64.hh:89
gem5::ArmISAInst::MicroTmeBasic64
Definition: tme64.hh:59
gem5::ArmISAInst::Tcancel64::Tcancel64
Tcancel64(ArmISA::ExtMachInst, uint64_t)
Definition: tme64.cc:176
gem5::ArmISAInst::MicroTcommit64
Definition: tme64.hh:145
gem5::ArmISAInst::Tcancel64::completeAcc
Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const
Definition: tme64classic.cc:85
gem5::ArmISAInst::Tstart64::completeAcc
Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const
Definition: tme64classic.cc:58
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
pred_inst.hh
gem5::ArmISAInst::MicroTmeBasic64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
Internal function to generate disassembly string.
Definition: tme64.cc:72
gem5::ArmISA::PredMacroOp
Base class for predicated macro-operations.
Definition: pred_inst.hh:340
gem5::ArmISAInst::MicroTmeOp::MicroTmeOp
MicroTmeOp(const char *mnem, ArmISA::ExtMachInst machInst, OpClass __opClass)
Definition: tme64.hh:53
gem5::ArmISAInst::Tstart64
Definition: tme64.hh:101
gem5::ArmISAInst::TmeImmOp64::imm
uint64_t imm
Definition: tme64.hh:74
gem5::ArmISAInst::TmeRegNone64
Definition: tme64.hh:86
gem5::ArmISAInst::TmeRegNone64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
Internal function to generate disassembly string.
Definition: tme64.cc:62
static_inst.hh
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISAInst::TmeImmOp64
Definition: tme64.hh:71
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::ArmISAInst::MicroTcommit64::initiateAcc
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const
Definition: tme64classic.cc:94
gem5::ArmISAInst::MicroTmeBasic64::MicroTmeBasic64
MicroTmeBasic64(const char *mnem, ArmISA::ExtMachInst machInst, OpClass __opClass)
Definition: tme64.hh:62
gem5::ArmISAInst::MacroTmeOp
Definition: tme64.hh:156
gem5::ArmISAInst::MicroTmeOp
Definition: tme64.hh:50
gem5::ArmISAInst::TmeRegNone64::TmeRegNone64
TmeRegNone64(const char *mnem, ArmISA::ExtMachInst machInst, OpClass __opClass, ArmISA::IntRegIndex _dest)
Definition: tme64.hh:91
gem5::ArmISAInst::MicroTfence64::MicroTfence64
MicroTfence64(ArmISA::ExtMachInst)
Definition: tme64.cc:80
gem5::Trace::InstRecord
Definition: insttracer.hh:58
gem5::ArmISAInst::MicroTfence64::initiateAcc
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const
Definition: tme64.cc:103
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISAInst::Tstart64::execute
Fault execute(ExecContext *, Trace::InstRecord *) const
Definition: tme64.cc:146
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88
gem5::ArmISAInst::MicroTcommit64::completeAcc
Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const
Definition: tme64classic.cc:103

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