49 #include "debug/Decoder.hh" 59 decoderFlavour(isa->decoderFlavour())
103 uint16_t highBits = word & 0xF800;
104 if (highBits == 0xE800 || highBits == 0xF000 ||
105 highBits == 0xF800) {
117 "First half of 32 bit Thumb.\n");
118 emi.instBits = (uint32_t)word << 16;
132 if (
bits(word, 15, 8) == 0xbf &&
133 bits(word, 3, 0) != 0x0) {
137 "IT detected, cond = %#x, mask = %#x\n",
158 offset = (fetchPC >= pc.instAddr()) ? 0 : pc.instAddr() - fetchPC;
159 emi.thumb = pc.thumb();
160 emi.aarch64 = pc.aarch64();
165 const Addr alignment(pc.thumb() ? 0x1 : 0x3);
166 emi.decoderFault =
static_cast<uint8_t
>(
179 const int inst_size((!
emi.thumb ||
emi.bigThumb) ? 4 : 2);
182 pc.npc(pc.pc() + inst_size);
185 this_emi.itstate = pc.itstate();
186 this_emi.illegalExecution = pc.illegalExec() ? 1 : 0;
194 return decode(this_emi, pc.instAddr());
void consumeBytes(int numBytes)
Consume bytes by moving the offset into the data word and sanity check the results.
int sveLen
SVE vector length, encoded in the same format as the ZCR_EL<x>.LEN bitfields.
void process()
Pre-decode an instruction from the current state of the decoder.
static GenericISA::BasicDecodeCache defaultCache
A cache of decoded instruction objects.
unsigned getCurSveVecLenInBitsAtReset() const
Bitfield< 41, 40 > fpscrStride
StaticInstPtr decode(ArmISA::PCState &pc)
Decode an instruction or fetch it from the code cache.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
Feed data to the decoder.
Bitfield< 39, 37 > fpscrLen
GenericISA::SimplePCState< MachInst > PCState
Decoder(ISA *isa=nullptr)
void reset()
Reset the decoders internal state.
T bits(T val, int first, int last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it...
Unaligned instruction fault.