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base_gic.hh
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37  * Authors: Andreas Sandberg
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39 
44 #ifndef __DEV_ARM_BASE_GIC_H__
45 #define __DEV_ARM_BASE_GIC_H__
46 
47 #include <unordered_map>
48 
49 #include "arch/arm/system.hh"
50 #include "dev/io_device.hh"
51 
52 class Platform;
53 class RealView;
54 class ThreadContext;
55 class ArmInterruptPin;
56 class ArmSPI;
57 class ArmPPI;
58 
59 struct ArmInterruptPinParams;
60 struct ArmPPIParams;
61 struct ArmSPIParams;
62 struct BaseGicParams;
63 
64 class BaseGic : public PioDevice
65 {
66  public:
67  typedef BaseGicParams Params;
68  enum class GicVersion { GIC_V2, GIC_V3, GIC_V4 };
69 
70  BaseGic(const Params *p);
71  virtual ~BaseGic();
72  void init() override;
73 
74  const Params * params() const;
75 
84  virtual void sendInt(uint32_t num) = 0;
85 
92  virtual void sendPPInt(uint32_t num, uint32_t cpu) = 0;
93  virtual void clearPPInt(uint32_t num, uint32_t cpu) = 0;
94 
103  virtual void clearInt(uint32_t num) = 0;
104 
105  ArmSystem *
106  getSystem() const
107  {
108  return (ArmSystem *) sys;
109  }
110 
112  virtual bool supportsVersion(GicVersion version) = 0;
113 
114  protected:
117 };
118 
120 {
121  public:
122  virtual uint32_t readDistributor(ContextID ctx, Addr daddr) = 0;
123  virtual uint32_t readCpu(ContextID ctx, Addr daddr) = 0;
124 
125  virtual void writeDistributor(ContextID ctx, Addr daddr,
126  uint32_t data) = 0;
127  virtual void writeCpu(ContextID ctx, Addr daddr, uint32_t data) = 0;
128 };
129 
138 {
139  public:
140  ArmInterruptPinGen(const ArmInterruptPinParams *p);
141 
142  virtual ArmInterruptPin* get(ThreadContext *tc = nullptr) = 0;
143 };
144 
151 {
152  public:
153  ArmSPIGen(const ArmSPIParams *p);
154 
155  ArmInterruptPin* get(ThreadContext *tc = nullptr) override;
156  protected:
158 };
159 
166 {
167  public:
168  ArmPPIGen(const ArmPPIParams *p);
169 
170  ArmInterruptPin* get(ThreadContext* tc = nullptr) override;
171  protected:
172  std::unordered_map<ContextID, ArmPPI*> pins;
173 };
174 
179 {
180  friend class ArmInterruptPinGen;
181  protected:
183  uint32_t int_num);
184 
185  public: /* Public interface */
193  void setThreadContext(ThreadContext *tc);
194 
196  uint32_t num() const { return intNum; }
197 
199  virtual void raise() = 0;
201  virtual void clear() = 0;
202 
203  protected:
210  ContextID targetContext() const;
211 
217 
220 
222  const uint32_t intNum;
223 };
224 
225 class ArmSPI : public ArmInterruptPin
226 {
227  friend class ArmSPIGen;
228  private:
229  ArmSPI(Platform *platform, uint32_t int_num);
230 
231  public:
232  void raise() override;
233  void clear() override;
234 };
235 
236 class ArmPPI : public ArmInterruptPin
237 {
238  friend class ArmPPIGen;
239  private:
240  ArmPPI(Platform *platform, ThreadContext *tc, uint32_t int_num);
241 
242  public:
243  void raise() override;
244  void clear() override;
245 };
246 
247 #endif
const uint32_t intNum
Interrupt number to generate.
Definition: base_gic.hh:222
ArmSPI * pin
Definition: base_gic.hh:157
Platform * platform
Platform this GIC belongs to.
Definition: base_gic.hh:116
RealView *const platform
Arm platform to use for interrupt generation.
Definition: base_gic.hh:219
virtual void clearInt(uint32_t num)=0
Clear an interrupt from a device that is connected to the GIC.
BaseGicParams Params
Definition: base_gic.hh:67
Shared Peripheral Interrupt Generator It is capable of generating one interrupt only: it maintains a ...
Definition: base_gic.hh:150
ThreadContext is the external interface to all thread state for anything outside of the CPU...
virtual void sendPPInt(uint32_t num, uint32_t cpu)=0
Interface call for private peripheral interrupts.
virtual void sendInt(uint32_t num)=0
Post an interrupt from a device that is connected to the GIC.
This device is the base class which all devices senstive to an address range inherit from...
Definition: io_device.hh:102
GicVersion
Definition: base_gic.hh:68
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
System * sys
Definition: io_device.hh:105
uint32_t num() const
Get interrupt number.
Definition: base_gic.hh:196
virtual ~BaseGic()
Definition: base_gic.cc:63
const ThreadContext * threadContext
Pointer to the thread context that owns this interrupt in case it is a thread-/CPU-private interrupt...
Definition: base_gic.hh:216
std::unordered_map< ContextID, ArmPPI * > pins
Definition: base_gic.hh:172
This SimObject is instantiated in the python world and serves as an ArmInterruptPin generator...
Definition: base_gic.hh:137
Private Peripheral Interrupt Generator Since PPIs are banked in the GIC, this class is capable of gen...
Definition: base_gic.hh:165
ArmSystem * getSystem() const
Definition: base_gic.hh:106
Bitfield< 0 > p
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: base_gic.cc:68
BaseGic(const Params *p)
Definition: base_gic.cc:49
const char data[]
Generic representation of an Arm interrupt pin.
Definition: base_gic.hh:178
Abstract superclass for simulation objects.
Definition: sim_object.hh:96
int ContextID
Globally unique thread context ID.
Definition: types.hh:231
virtual void clearPPInt(uint32_t num, uint32_t cpu)=0
const Params * params() const
Definition: base_gic.cc:75
virtual bool supportsVersion(GicVersion version)=0
Check if version supported.

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