42 #include "arch/utility.hh" 46 #include "debug/Drain.hh" 47 #include "debug/MinorCPU.hh" 48 #include "debug/Quiesce.hh" 52 threadPolicy(params->threadPolicy)
60 params->itb, params->dtb, params->isa[
i]);
64 params->workload[
i], params->itb, params->dtb,
74 if (params->checker) {
75 fatal(
"The Minor model doesn't support checking (yet)\n");
98 if (!
params()->switched_out &&
101 fatal(
"The Minor CPU requires the memory system to be in " 106 for (
ThreadID thread_id = 0; thread_id <
threads.size(); thread_id++) {
125 threads[thread_id]->serialize(cp);
131 threads[thread_id]->unserialize(cp);
152 panic(
"No implementation for vtophy\n");
160 DPRINTF(Drain,
"[tid:%d] MinorCPU wakeup\n", tid);
188 DPRINTF(Drain,
"Minor CPU switched out, draining not needed.\n");
192 DPRINTF(Drain,
"MinorCPU drain\n");
197 DPRINTF(Drain,
"MinorCPU drained\n");
200 DPRINTF(Drain,
"MinorCPU not finished draining\n");
208 DPRINTF(Drain,
"MinorCPU drain done\n");
221 DPRINTF(Drain,
"drainResume while switched out. Ignoring\n");
225 DPRINTF(Drain,
"MinorCPU drainResume\n");
228 fatal(
"The Minor CPU requires the memory system to be in " 245 DPRINTF(Drain,
"MinorCPU memWriteback\n");
280 threads[thread_id]->activate();
300 DPRINTF(Quiesce,
"Event wakeup from stage %d\n", stage_id);
308 MinorCPUParams::create()
331 ret += (*i)->numInst;
#define panic(...)
This implements a cprintf based panic() function.
void signalDrainDone()
Signal from Pipeline that MinorCPU should signal that a drain is complete and set its drainState...
Ports are used to interface objects to each other.
void regStats(const std::string &name, BaseCPU &baseCpu)
Port & getInstPort() override
Return a reference to the instruction port.
#define fatal(...)
This implements a cprintf based fatal() function.
Stats::Scalar quiesceCycles
Number of cycles in quiescent state.
DrainState
Object drain/handover states.
ThreadID numThreads
Number of threads we're actually simulating (<= SMT_MAX_THREADS).
Counter totalOps() const override
void wakeupOnEvent(unsigned int stage_id)
Interface for stages to signal that they have become active after a callback or eventq event where th...
void startup() override
startup() is the final initialization call before simulation.
virtual void activateContext(ThreadID thread_num)
Notify the CPU that the indicated context is now active.
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
void signalDrainDone() const
Signal that an object is drained.
bool switchedOut() const
Determine if the CPU is switched out.
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
void setStatus(Status newStatus) override
Minor::Pipeline * pipeline
pipeline is a container for the clockable pipeline stage objects.
void unserialize(CheckpointIn &cp) override
Reconstruct the state of this object from a checkpoint.
void reset()
Clears the time buffer and the activity count.
void drainResume() override
Resume execution after a successful drain.
ThreadContext is the external interface to all thread state for anything outside of the CPU...
DrainState drain() override
Drain interface.
void regStats() override
Callback to set stat parameters.
std::vector< ThreadContext * > threadContexts
void unserialize(CheckpointIn &cp) override
Reconstruct the state of this object from a checkpoint.
Addr dbg_vtophys(Addr addr)
void schedulePowerGatingEvent()
void init() override
Starting, waking and initialisation.
virtual void takeOverFrom(BaseCPU *cpu)
Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be sw...
void unserializeThread(CheckpointIn &cp, ThreadID tid) override
Unserialize one thread.
void serialize(CheckpointOut &cp) const override
Serialize pipeline data.
SimpleThread MinorThread
Minor will use the SimpleThread state for now.
void activateStage(const int idx)
Marks a stage as active.
void startup() override
startup() is the final initialization call before simulation.
void memWriteback() override
Write back dirty buffers to memory using functional writes.
Minor::MinorActivityRecorder * activityRecorder
Activity recording for pipeline.
static void init()
Initialise the class.
Enums::MemoryMode getMemoryMode() const
Get the memory mode of the system.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
ThreadContext * getTC()
Returns the pointer to this SimpleThread's ThreadContext.
Draining buffers pending serialization/handover.
virtual const std::string name() const
int64_t Counter
Statistics counter type.
void takeOverFrom(BaseCPU *old_cpu) override
Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be sw...
Port & getDataPort() override
Return a reference to the data port.
virtual void switchOut()
Prepare for another CPU to take over execution.
Fetch1 is responsible for fetching "lines" from memory and passing them to Fetch2.
int16_t ThreadID
Thread index/ID type.
MinorCPU(MinorCPUParams *params)
std::ostream CheckpointOut
void deschedulePowerGatingEvent()
void suspendContext(ThreadID thread_id) override
Notify the CPU that the indicated context is now suspended.
Top level definition of the Minor in-order CPU model.
void wakeup(ThreadID tid) override
The dynamic instruction and instruction/line id (sequence numbers) definition for Minor...
virtual ThreadContext * getContext(int tn)
Given a thread num get tho thread context for it.
std::vector< Minor::MinorThread * > threads
These are thread state-representing objects for this CPU.
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
The constructed pipeline.
void serialize(CheckpointOut &cp) const override
Serialize this object to the given output stream.
MinorCPU is an in-order CPU model with four fixed pipeline stages:
bool isTimingMode() const
Is the system in timing mode?
Minor::MinorStats stats
Processor-specific statistics.
void activateContext(ThreadID thread_id) override
Thread activation interface from BaseCPU.
virtual void initMemProxies(ThreadContext *tc)=0
Initialise the physical and virtual port proxies and tie them to the data port of the CPU...
The constructed pipeline.
void serializeThread(CheckpointOut &cp, ThreadID tid) const override
Serialize a single thread.
const Params * params() const
void switchOut() override
Switching interface from BaseCPU.
void regStats() override
Stats interface from SimObject (by way of BaseCPU)
Counter totalInsts() const override
Simple inst count interface from BaseCPU.
virtual void suspendContext(ThreadID thread_num)
Notify the CPU that the indicated context is now suspended.