gem5  v19.0.0.0
All Classes Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros Modules Pages
cpu.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2012-2014, 2017 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Redistribution and use in source and binary forms, with or without
15  * modification, are permitted provided that the following conditions are
16  * met: redistributions of source code must retain the above copyright
17  * notice, this list of conditions and the following disclaimer;
18  * redistributions in binary form must reproduce the above copyright
19  * notice, this list of conditions and the following disclaimer in the
20  * documentation and/or other materials provided with the distribution;
21  * neither the name of the copyright holders nor the names of its
22  * contributors may be used to endorse or promote products derived from
23  * this software without specific prior written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  *
37  * Authors: Andrew Bardsley
38  */
39 
40 #include "cpu/minor/cpu.hh"
41 
42 #include "arch/utility.hh"
43 #include "cpu/minor/dyn_inst.hh"
44 #include "cpu/minor/fetch1.hh"
45 #include "cpu/minor/pipeline.hh"
46 #include "debug/Drain.hh"
47 #include "debug/MinorCPU.hh"
48 #include "debug/Quiesce.hh"
49 
50 MinorCPU::MinorCPU(MinorCPUParams *params) :
51  BaseCPU(params),
52  threadPolicy(params->threadPolicy)
53 {
54  /* This is only written for one thread at the moment */
55  Minor::MinorThread *thread;
56 
57  for (ThreadID i = 0; i < numThreads; i++) {
58  if (FullSystem) {
59  thread = new Minor::MinorThread(this, i, params->system,
60  params->itb, params->dtb, params->isa[i]);
62  } else {
63  thread = new Minor::MinorThread(this, i, params->system,
64  params->workload[i], params->itb, params->dtb,
65  params->isa[i]);
66  }
67 
68  threads.push_back(thread);
69  ThreadContext *tc = thread->getTC();
70  threadContexts.push_back(tc);
71  }
72 
73 
74  if (params->checker) {
75  fatal("The Minor model doesn't support checking (yet)\n");
76  }
77 
79 
80  pipeline = new Minor::Pipeline(*this, *params);
81  activityRecorder = pipeline->getActivityRecorder();
82 }
83 
85 {
86  delete pipeline;
87 
88  for (ThreadID thread_id = 0; thread_id < threads.size(); thread_id++) {
89  delete threads[thread_id];
90  }
91 }
92 
93 void
95 {
96  BaseCPU::init();
97 
98  if (!params()->switched_out &&
99  system->getMemoryMode() != Enums::timing)
100  {
101  fatal("The Minor CPU requires the memory system to be in "
102  "'timing' mode.\n");
103  }
104 
105  /* Initialise the ThreadContext's memory proxies */
106  for (ThreadID thread_id = 0; thread_id < threads.size(); thread_id++) {
107  ThreadContext *tc = getContext(thread_id);
108 
109  tc->initMemProxies(tc);
110  }
111 }
112 
114 void
116 {
118  stats.regStats(name(), *this);
119  pipeline->regStats();
120 }
121 
122 void
124 {
125  threads[thread_id]->serialize(cp);
126 }
127 
128 void
130 {
131  threads[thread_id]->unserialize(cp);
132 }
133 
134 void
136 {
137  pipeline->serialize(cp);
138  BaseCPU::serialize(cp);
139 }
140 
141 void
143 {
144  pipeline->unserialize(cp);
146 }
147 
148 Addr
150 {
151  /* Note that this gives you the translation for thread 0 */
152  panic("No implementation for vtophy\n");
153 
154  return 0;
155 }
156 
157 void
159 {
160  DPRINTF(Drain, "[tid:%d] MinorCPU wakeup\n", tid);
161  assert(tid < numThreads);
162 
163  if (threads[tid]->status() == ThreadContext::Suspended) {
164  threads[tid]->activate();
165  }
166 }
167 
168 void
170 {
171  DPRINTF(MinorCPU, "MinorCPU startup\n");
172 
174 
175  for (ThreadID tid = 0; tid < numThreads; tid++) {
176  threads[tid]->startup();
177  pipeline->wakeupFetch(tid);
178  }
179 }
180 
183 {
184  // Deschedule any power gating event (if any)
186 
187  if (switchedOut()) {
188  DPRINTF(Drain, "Minor CPU switched out, draining not needed.\n");
189  return DrainState::Drained;
190  }
191 
192  DPRINTF(Drain, "MinorCPU drain\n");
193 
194  /* Need to suspend all threads and wait for Execute to idle.
195  * Tell Fetch1 not to fetch */
196  if (pipeline->drain()) {
197  DPRINTF(Drain, "MinorCPU drained\n");
198  return DrainState::Drained;
199  } else {
200  DPRINTF(Drain, "MinorCPU not finished draining\n");
201  return DrainState::Draining;
202  }
203 }
204 
205 void
207 {
208  DPRINTF(Drain, "MinorCPU drain done\n");
210 }
211 
212 void
214 {
215  /* When taking over from another cpu make sure lastStopped
216  * is reset since it might have not been defined previously
217  * and might lead to a stats corruption */
218  pipeline->resetLastStopped();
219 
220  if (switchedOut()) {
221  DPRINTF(Drain, "drainResume while switched out. Ignoring\n");
222  return;
223  }
224 
225  DPRINTF(Drain, "MinorCPU drainResume\n");
226 
227  if (!system->isTimingMode()) {
228  fatal("The Minor CPU requires the memory system to be in "
229  "'timing' mode.\n");
230  }
231 
232  for (ThreadID tid = 0; tid < numThreads; tid++){
233  wakeup(tid);
234  }
235 
236  pipeline->drainResume();
237 
238  // Reschedule any power gating event (if any)
240 }
241 
242 void
244 {
245  DPRINTF(Drain, "MinorCPU memWriteback\n");
246 }
247 
248 void
250 {
251  DPRINTF(MinorCPU, "MinorCPU switchOut\n");
252 
253  assert(!switchedOut());
255 
256  /* Check that the CPU is drained? */
258 }
259 
260 void
262 {
263  DPRINTF(MinorCPU, "MinorCPU takeOverFrom\n");
264 
265  BaseCPU::takeOverFrom(old_cpu);
266 }
267 
268 void
270 {
271  DPRINTF(MinorCPU, "ActivateContext thread: %d\n", thread_id);
272 
273  /* Do some cycle accounting. lastStopped is reset to stop the
274  * wakeup call on the pipeline from adding the quiesce period
275  * to BaseCPU::numCycles */
276  stats.quiesceCycles += pipeline->cyclesSinceLastStopped();
277  pipeline->resetLastStopped();
278 
279  /* Wake up the thread, wakeup the pipeline tick */
280  threads[thread_id]->activate();
282  pipeline->wakeupFetch(thread_id);
283 
284  BaseCPU::activateContext(thread_id);
285 }
286 
287 void
289 {
290  DPRINTF(MinorCPU, "SuspendContext %d\n", thread_id);
291 
292  threads[thread_id]->suspend();
293 
294  BaseCPU::suspendContext(thread_id);
295 }
296 
297 void
298 MinorCPU::wakeupOnEvent(unsigned int stage_id)
299 {
300  DPRINTF(Quiesce, "Event wakeup from stage %d\n", stage_id);
301 
302  /* Mark that some activity has taken place and start the pipeline */
303  activityRecorder->activateStage(stage_id);
304  pipeline->start();
305 }
306 
307 MinorCPU *
308 MinorCPUParams::create()
309 {
310  return new MinorCPU(this);
311 }
312 
313 Port &
315 {
316  return pipeline->getInstPort();
317 }
318 
319 Port &
321 {
322  return pipeline->getDataPort();
323 }
324 
325 Counter
327 {
328  Counter ret = 0;
329 
330  for (auto i = threads.begin(); i != threads.end(); i ++)
331  ret += (*i)->numInst;
332 
333  return ret;
334 }
335 
336 Counter
338 {
339  Counter ret = 0;
340 
341  for (auto i = threads.begin(); i != threads.end(); i ++)
342  ret += (*i)->numOp;
343 
344  return ret;
345 }
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:167
void signalDrainDone()
Signal from Pipeline that MinorCPU should signal that a drain is complete and set its drainState...
Definition: cpu.cc:206
#define DPRINTF(x,...)
Definition: trace.hh:229
Ports are used to interface objects to each other.
Definition: port.hh:60
void regStats(const std::string &name, BaseCPU &baseCpu)
Definition: stats.cc:49
Port & getInstPort() override
Return a reference to the instruction port.
Definition: cpu.cc:314
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:175
Stats::Scalar quiesceCycles
Number of cycles in quiescent state.
Definition: stats.hh:73
Bitfield< 7 > i
DrainState
Object drain/handover states.
Definition: drain.hh:71
ThreadID numThreads
Number of threads we&#39;re actually simulating (<= SMT_MAX_THREADS).
Definition: base.hh:378
Running normally.
Counter totalOps() const override
Definition: cpu.cc:337
void wakeupOnEvent(unsigned int stage_id)
Interface for stages to signal that they have become active after a callback or eventq event where th...
Definition: cpu.cc:298
void startup() override
startup() is the final initialization call before simulation.
Definition: cpu.cc:169
ip6_addr_t addr
Definition: inet.hh:335
virtual void activateContext(ThreadID thread_num)
Notify the CPU that the indicated context is now active.
Definition: base.cc:491
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:136
void signalDrainDone() const
Signal that an object is drained.
Definition: drain.hh:267
bool switchedOut() const
Determine if the CPU is switched out.
Definition: base.hh:367
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
void setStatus(Status newStatus) override
Minor::Pipeline * pipeline
pipeline is a container for the clockable pipeline stage objects.
Definition: cpu.hh:84
void unserialize(CheckpointIn &cp) override
Reconstruct the state of this object from a checkpoint.
Definition: base.cc:704
void reset()
Clears the time buffer and the activity count.
Definition: activity.cc:126
System * system
Definition: base.hh:386
Definition: cprintf.cc:42
void drainResume() override
Resume execution after a successful drain.
Definition: cpu.cc:213
ThreadContext is the external interface to all thread state for anything outside of the CPU...
DrainState drain() override
Drain interface.
Definition: cpu.cc:182
void regStats() override
Callback to set stat parameters.
Definition: base.cc:388
Bitfield< 5, 0 > status
std::vector< ThreadContext * > threadContexts
Definition: base.hh:267
void unserialize(CheckpointIn &cp) override
Reconstruct the state of this object from a checkpoint.
Definition: cpu.cc:142
Addr dbg_vtophys(Addr addr)
Definition: cpu.cc:149
void schedulePowerGatingEvent()
Definition: base.cc:463
void init() override
Starting, waking and initialisation.
Definition: cpu.cc:94
virtual void takeOverFrom(BaseCPU *cpu)
Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be sw...
Definition: base.cc:559
void unserializeThread(CheckpointIn &cp, ThreadID tid) override
Unserialize one thread.
Definition: cpu.cc:129
void serialize(CheckpointOut &cp) const override
Serialize pipeline data.
Definition: cpu.cc:135
SimpleThread MinorThread
Minor will use the SimpleThread state for now.
Definition: cpu.hh:60
void activateStage(const int idx)
Marks a stage as active.
Definition: activity.cc:92
void startup() override
startup() is the final initialization call before simulation.
Definition: base.cc:324
void memWriteback() override
Write back dirty buffers to memory using functional writes.
Definition: cpu.cc:243
Minor::MinorActivityRecorder * activityRecorder
Activity recording for pipeline.
Definition: cpu.hh:90
static void init()
Initialise the class.
Definition: dyn_inst.cc:81
Enums::MemoryMode getMemoryMode() const
Get the memory mode of the system.
Definition: system.hh:173
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
ThreadContext * getTC()
Returns the pointer to this SimpleThread&#39;s ThreadContext.
Draining buffers pending serialization/handover.
virtual const std::string name() const
Definition: sim_object.hh:120
int64_t Counter
Statistics counter type.
Definition: types.hh:58
void takeOverFrom(BaseCPU *old_cpu) override
Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be sw...
Definition: cpu.cc:261
Port & getDataPort() override
Return a reference to the data port.
Definition: cpu.cc:320
virtual void switchOut()
Prepare for another CPU to take over execution.
Definition: base.cc:543
Fetch1 is responsible for fetching "lines" from memory and passing them to Fetch2.
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:227
MinorCPU(MinorCPUParams *params)
Definition: cpu.cc:50
std::ostream CheckpointOut
Definition: serialize.hh:68
Permanently shut down.
void deschedulePowerGatingEvent()
Definition: base.cc:455
void suspendContext(ThreadID thread_id) override
Notify the CPU that the indicated context is now suspended.
Definition: cpu.cc:288
Top level definition of the Minor in-order CPU model.
void wakeup(ThreadID tid) override
Definition: cpu.cc:158
The dynamic instruction and instruction/line id (sequence numbers) definition for Minor...
virtual ThreadContext * getContext(int tn)
Given a thread num get tho thread context for it.
Definition: base.hh:298
std::vector< Minor::MinorThread * > threads
These are thread state-representing objects for this CPU.
Definition: cpu.hh:95
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: base.cc:281
The constructed pipeline.
void serialize(CheckpointOut &cp) const override
Serialize this object to the given output stream.
Definition: base.cc:683
Temporarily inactive.
MinorCPU is an in-order CPU model with four fixed pipeline stages:
Definition: cpu.hh:79
bool isTimingMode() const
Is the system in timing mode?
Definition: system.hh:150
Minor::MinorStats stats
Processor-specific statistics.
Definition: cpu.hh:136
void activateContext(ThreadID thread_id) override
Thread activation interface from BaseCPU.
Definition: cpu.cc:269
virtual void initMemProxies(ThreadContext *tc)=0
Initialise the physical and virtual port proxies and tie them to the data port of the CPU...
The constructed pipeline.
Definition: pipeline.hh:71
void serializeThread(CheckpointOut &cp, ThreadID tid) const override
Serialize a single thread.
Definition: cpu.cc:123
const Params * params() const
Definition: base.hh:311
void switchOut() override
Switching interface from BaseCPU.
Definition: cpu.cc:249
void regStats() override
Stats interface from SimObject (by way of BaseCPU)
Definition: cpu.cc:115
Counter totalInsts() const override
Simple inst count interface from BaseCPU.
Definition: cpu.cc:326
~MinorCPU()
Definition: cpu.cc:84
virtual void suspendContext(ThreadID thread_num)
Notify the CPU that the indicated context is now suspended.
Definition: base.cc:505

Generated on Fri Feb 28 2020 16:26:56 for gem5 by doxygen 1.8.13