43 #ifndef __CPU_O3_DYN_INST_IMPL_HH__ 44 #define __CPU_O3_DYN_INST_IMPL_HH__ 48 #include "debug/O3PipeView.hh" 55 :
BaseDynInst<Impl>(staticInst, macroop, pc, predPC, seq_num, cpu)
72 Tick fetch = this->fetchTick;
77 DPRINTFR(O3PipeView,
"O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n",
84 val = (this->decodeTick == -1) ? 0 : fetch + this->decodeTick;
85 DPRINTFR(O3PipeView,
"O3PipeView:decode:%llu\n", val);
86 val = (this->renameTick == -1) ? 0 : fetch + this->renameTick;
87 DPRINTFR(O3PipeView,
"O3PipeView:rename:%llu\n", val);
88 val = (this->dispatchTick == -1) ? 0 : fetch + this->dispatchTick;
89 DPRINTFR(O3PipeView,
"O3PipeView:dispatch:%llu\n", val);
90 val = (this->issueTick == -1) ? 0 : fetch + this->issueTick;
91 DPRINTFR(O3PipeView,
"O3PipeView:issue:%llu\n", val);
92 val = (this->completeTick == -1) ? 0 : fetch + this->completeTick;
93 DPRINTFR(O3PipeView,
"O3PipeView:complete:%llu\n", val);
94 val = (this->commitTick == -1) ? 0 : fetch + this->commitTick;
96 Tick valS = (this->storeTick == -1) ? 0 : fetch + this->storeTick;
97 DPRINTFR(O3PipeView,
"O3PipeView:retire:%llu:store:%llu\n", val, valS);
104 template <
class Impl>
126 template <
class Impl>
134 bool no_squash_from_TC = this->
thread->noSquashFromTC;
135 this->
thread->noSquashFromTC =
true;
139 this->
thread->noSquashFromTC = no_squash_from_TC;
144 template <
class Impl>
152 bool no_squash_from_TC = this->
thread->noSquashFromTC;
153 this->
thread->noSquashFromTC =
true;
157 this->
thread->noSquashFromTC = no_squash_from_TC;
162 template <
class Impl>
170 bool no_squash_from_TC = this->
thread->noSquashFromTC;
171 this->
thread->noSquashFromTC =
true;
173 if (this->
cpu->checker) {
181 this->
thread->noSquashFromTC = no_squash_from_TC;
186 template <
class Impl>
193 template <
class Impl>
203 if (!(curPC == newPC)) {
208 #endif//__CPU_O3_DYN_INST_IMPL_HH__
InstSeqNum seqNum
The sequence number of the instruction.
virtual Fault completeAcc(Packet *pkt, ExecContext *xc, Trace::InstRecord *traceData) const
Fault fault
The kind of fault this instruction has generated.
virtual const std::string & disassemble(Addr pc, const SymbolTable *symtab=0) const
Return string representation of disassembled instruction.
virtual Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const =0
Trace::InstRecord * traceData
InstRecord that tracks this instructions.
Fault completeAcc(PacketPtr pkt)
Completes the access.
void trap(const Fault &fault)
Traps to handle specified fault.
virtual Fault initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const
RequestPtr req
A pointer to the original request.
void syscall(Fault *fault) override
Emulates a syscall.
uint8_t _numDestMiscRegs
Number of destination misc.
uint64_t Tick
Tick count type.
bool isStoreConditional() const
BaseO3DynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop, TheISA::PCState pc, TheISA::PCState predPC, InstSeqNum seq_num, O3CPU *cpu)
BaseDynInst constructor given a binary instruction.
const StaticInstPtr staticInst
The StaticInst used by this BaseDynInst.
Fault execute()
Executes the instruction.
std::bitset< MaxInstSrcRegs > _readySrcRegIdx
Whether or not the source register is ready.
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
Addr microPC() const
Read the micro PC of this instruction.
ImplCPU * cpu
Pointer to the Impl's CPU object.
Impl::O3CPU O3CPU
Typedef for the CPU.
GenericISA::SimplePCState< MachInst > PCState
Addr instAddr() const
Read the PC of this instruction.
TheISA::PCState pcState() const
Read the PC state of this instruction.
ThreadID threadNumber
The thread this instruction is from.
std::shared_ptr< FaultBase > Fault
ImplState * thread
Pointer to the thread state.
void initVars()
Initializes variables.
Fault initiateAcc()
Initiates the access.