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dyn_inst_impl.hh
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42 
43 #ifndef __CPU_O3_DYN_INST_IMPL_HH__
44 #define __CPU_O3_DYN_INST_IMPL_HH__
45 
46 #include "base/cp_annotate.hh"
47 #include "cpu/o3/dyn_inst.hh"
48 #include "debug/O3PipeView.hh"
49 
50 template <class Impl>
52  const StaticInstPtr &macroop,
54  InstSeqNum seq_num, O3CPU *cpu)
55  : BaseDynInst<Impl>(staticInst, macroop, pc, predPC, seq_num, cpu)
56 {
57  initVars();
58 }
59 
60 template <class Impl>
62  const StaticInstPtr &_macroop)
63  : BaseDynInst<Impl>(_staticInst, _macroop)
64 {
65  initVars();
66 }
67 
69 {
70 #if TRACING_ON
71  if (DTRACE(O3PipeView)) {
72  Tick fetch = this->fetchTick;
73  // fetchTick can be -1 if the instruction fetched outside the trace window.
74  if (fetch != -1) {
75  Tick val;
76  // Print info needed by the pipeline activity viewer.
77  DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n",
78  fetch,
79  this->instAddr(),
80  this->microPC(),
81  this->seqNum,
82  this->staticInst->disassemble(this->instAddr()));
83 
84  val = (this->decodeTick == -1) ? 0 : fetch + this->decodeTick;
85  DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", val);
86  val = (this->renameTick == -1) ? 0 : fetch + this->renameTick;
87  DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", val);
88  val = (this->dispatchTick == -1) ? 0 : fetch + this->dispatchTick;
89  DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", val);
90  val = (this->issueTick == -1) ? 0 : fetch + this->issueTick;
91  DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", val);
92  val = (this->completeTick == -1) ? 0 : fetch + this->completeTick;
93  DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", val);
94  val = (this->commitTick == -1) ? 0 : fetch + this->commitTick;
95 
96  Tick valS = (this->storeTick == -1) ? 0 : fetch + this->storeTick;
97  DPRINTFR(O3PipeView, "O3PipeView:retire:%llu:store:%llu\n", val, valS);
98  }
99  }
100 #endif
101 };
102 
103 
104 template <class Impl>
105 void
107 {
108  this->_readySrcRegIdx.reset();
109 
110  _numDestMiscRegs = 0;
111 
112 #if TRACING_ON
113  // Value -1 indicates that particular phase
114  // hasn't happened (yet).
115  fetchTick = -1;
116  decodeTick = -1;
117  renameTick = -1;
118  dispatchTick = -1;
119  issueTick = -1;
120  completeTick = -1;
121  commitTick = -1;
122  storeTick = -1;
123 #endif
124 }
125 
126 template <class Impl>
127 Fault
129 {
130  // @todo: Pretty convoluted way to avoid squashing from happening
131  // when using the TC during an instruction's execution
132  // (specifically for instructions that have side-effects that use
133  // the TC). Fix this.
134  bool no_squash_from_TC = this->thread->noSquashFromTC;
135  this->thread->noSquashFromTC = true;
136 
137  this->fault = this->staticInst->execute(this, this->traceData);
138 
139  this->thread->noSquashFromTC = no_squash_from_TC;
140 
141  return this->fault;
142 }
143 
144 template <class Impl>
145 Fault
147 {
148  // @todo: Pretty convoluted way to avoid squashing from happening
149  // when using the TC during an instruction's execution
150  // (specifically for instructions that have side-effects that use
151  // the TC). Fix this.
152  bool no_squash_from_TC = this->thread->noSquashFromTC;
153  this->thread->noSquashFromTC = true;
154 
155  this->fault = this->staticInst->initiateAcc(this, this->traceData);
156 
157  this->thread->noSquashFromTC = no_squash_from_TC;
158 
159  return this->fault;
160 }
161 
162 template <class Impl>
163 Fault
165 {
166  // @todo: Pretty convoluted way to avoid squashing from happening
167  // when using the TC during an instruction's execution
168  // (specifically for instructions that have side-effects that use
169  // the TC). Fix this.
170  bool no_squash_from_TC = this->thread->noSquashFromTC;
171  this->thread->noSquashFromTC = true;
172 
173  if (this->cpu->checker) {
174  if (this->isStoreConditional()) {
175  this->reqToVerify->setExtraData(pkt->req->getExtraData());
176  }
177  }
178 
179  this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
180 
181  this->thread->noSquashFromTC = no_squash_from_TC;
182 
183  return this->fault;
184 }
185 
186 template <class Impl>
187 void
189 {
190  this->cpu->trap(fault, this->threadNumber, this->staticInst);
191 }
192 
193 template <class Impl>
194 void
196 {
197  // HACK: check CPU's nextPC before and after syscall. If it
198  // changes, update this instruction's nextPC because the syscall
199  // must have changed the nextPC.
200  TheISA::PCState curPC = this->cpu->pcState(this->threadNumber);
201  this->cpu->syscall(this->threadNumber, fault);
202  TheISA::PCState newPC = this->cpu->pcState(this->threadNumber);
203  if (!(curPC == newPC)) {
204  this->pcState(newPC);
205  }
206 }
207 
208 #endif//__CPU_O3_DYN_INST_IMPL_HH__
RequestPtr reqToVerify
InstSeqNum seqNum
The sequence number of the instruction.
virtual Fault completeAcc(Packet *pkt, ExecContext *xc, Trace::InstRecord *traceData) const
Definition: static_inst.hh:282
Fault fault
The kind of fault this instruction has generated.
virtual const std::string & disassemble(Addr pc, const SymbolTable *symtab=0) const
Return string representation of disassembled instruction.
Definition: static_inst.cc:123
virtual Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const =0
Trace::InstRecord * traceData
InstRecord that tracks this instructions.
Fault completeAcc(PacketPtr pkt)
Completes the access.
void trap(const Fault &fault)
Traps to handle specified fault.
virtual Fault initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const
Definition: static_inst.hh:276
Bitfield< 63 > val
Definition: misc.hh:771
RequestPtr req
A pointer to the original request.
Definition: packet.hh:327
void syscall(Fault *fault) override
Emulates a syscall.
uint8_t _numDestMiscRegs
Number of destination misc.
Definition: dyn_inst.hh:120
Bitfield< 4 > pc
#define DTRACE(x)
Definition: trace.hh:227
uint64_t Tick
Tick count type.
Definition: types.hh:63
bool isStoreConditional() const
uint64_t InstSeqNum
Definition: inst_seq.hh:40
BaseO3DynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop, TheISA::PCState pc, TheISA::PCState predPC, InstSeqNum seq_num, O3CPU *cpu)
BaseDynInst constructor given a binary instruction.
const StaticInstPtr staticInst
The StaticInst used by this BaseDynInst.
Fault execute()
Executes the instruction.
std::bitset< MaxInstSrcRegs > _readySrcRegIdx
Whether or not the source register is ready.
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
Definition: packet.hh:255
Addr microPC() const
Read the micro PC of this instruction.
ImplCPU * cpu
Pointer to the Impl&#39;s CPU object.
Impl::O3CPU O3CPU
Typedef for the CPU.
Definition: dyn_inst.hh:64
GenericISA::SimplePCState< MachInst > PCState
Definition: types.hh:43
Addr instAddr() const
Read the PC of this instruction.
TheISA::PCState pcState() const
Read the PC state of this instruction.
ThreadID threadNumber
The thread this instruction is from.
std::shared_ptr< FaultBase > Fault
Definition: types.hh:240
ImplState * thread
Pointer to the thread state.
void initVars()
Initializes variables.
#define DPRINTFR(...)
Definition: trace.hh:231
Fault initiateAcc()
Initiates the access.

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