base_dyn_inst.hh

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/*
 * Copyright (c) 2011, 2013, 2016-2019 ARM Limited
 * Copyright (c) 2013 Advanced Micro Devices, Inc.
 * All rights reserved.
 *
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 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
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 *
 * Copyright (c) 2004-2006 The Regents of The University of Michigan
 * Copyright (c) 2009 The University of Edinburgh
 * All rights reserved.
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 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
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 * this software without specific prior written permission.
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 * Authors: Kevin Lim
 *          Timothy M. Jones
 */

#ifndef __CPU_BASE_DYN_INST_HH__
#define __CPU_BASE_DYN_INST_HH__

#include <array>
#include <bitset>
#include <deque>
#include <list>
#include <string>

#include "arch/generic/tlb.hh"
#include "arch/utility.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
#include "cpu/checker/cpu.hh"
#include "cpu/exec_context.hh"
#include "cpu/exetrace.hh"
#include "cpu/inst_res.hh"
#include "cpu/inst_seq.hh"
#include "cpu/op_class.hh"
#include "cpu/static_inst.hh"
#include "cpu/translation.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
#include "sim/byteswap.hh"
#include "sim/system.hh"

template <class Impl>
class BaseDynInst : public ExecContext, public RefCounted
{
  public:
    // Typedef for the CPU.
    typedef typename Impl::CPUType ImplCPU;
    typedef typename ImplCPU::ImplState ImplState;
    using VecRegContainer = TheISA::VecRegContainer;

    using LSQRequestPtr = typename Impl::CPUPol::LSQ::LSQRequest*;
    using LQIterator = typename Impl::CPUPol::LSQUnit::LQIterator;
    using SQIterator = typename Impl::CPUPol::LSQUnit::SQIterator;

    // The DynInstPtr type.
    typedef typename Impl::DynInstPtr DynInstPtr;
    typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr;

    // The list of instructions iterator type.
    typedef typename std::list<DynInstPtr>::iterator ListIt;

    enum {
        MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        
        MaxInstDestRegs = TheISA::MaxInstDestRegs       
    };

  protected:
    enum Status {
        IqEntry,                 
        RobEntry,                
        LsqEntry,                
        Completed,               
        ResultReady,             
        CanIssue,                
        Issued,                  
        Executed,                
        CanCommit,               
        AtCommit,                
        Committed,               
        Squashed,                
        SquashedInIQ,            
        SquashedInLSQ,           
        SquashedInROB,           
        PinnedRegsRenamed,       
        PinnedRegsWritten,       
        PinnedRegsSquashDone,    
        RecoverInst,             
        BlockingInst,            
        ThreadsyncWait,          
        SerializeBefore,         
        SerializeAfter,          
        SerializeHandled,        
        NumStatus
    };

    enum Flags {
        NotAnInst,
        TranslationStarted,
        TranslationCompleted,
        PossibleLoadViolation,
        HitExternalSnoop,
        EffAddrValid,
        RecordResult,
        Predicate,
        MemAccPredicate,
        PredTaken,
        IsStrictlyOrdered,
        ReqMade,
        MemOpDone,
        MaxFlags
    };

  public:
    InstSeqNum seqNum;

    const StaticInstPtr staticInst;

    ImplCPU *cpu;

    BaseCPU *getCpuPtr() { return cpu; }

    ImplState *thread;

    Fault fault;

    Trace::InstRecord *traceData;

  protected:
    std::queue<InstResult> instResult;

    TheISA::PCState pc;

  private:
    /* An amalgamation of a lot of boolean values into one */
    std::bitset<MaxFlags> instFlags;

    std::bitset<NumStatus> status;

  protected:
    std::bitset<MaxInstSrcRegs> _readySrcRegIdx;

  public:
    ThreadID threadNumber;

    ListIt instListIt;


    TheISA::PCState predPC;

    const StaticInstPtr macroop;

    uint8_t readyRegs;

  public:

    Addr effAddr;

    Addr physEffAddr;

    unsigned memReqFlags;

    short asid;

    unsigned effSize;

    uint8_t *memData;

    int16_t lqIdx;
    LQIterator lqIt;

    int16_t sqIdx;
    SQIterator sqIt;



    LSQRequestPtr savedReq;

    // Need a copy of main request pointer to verify on writes.
    RequestPtr reqToVerify;

  protected:
    std::array<RegId, TheISA::MaxInstDestRegs> _flatDestRegIdx;

    std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _destRegIdx;

    std::array<PhysRegIdPtr, TheISA::MaxInstSrcRegs> _srcRegIdx;

    std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _prevDestRegIdx;


  public:
    void recordResult(bool f) { instFlags[RecordResult] = f; }

    bool effAddrValid() const { return instFlags[EffAddrValid]; }
    void effAddrValid(bool b) { instFlags[EffAddrValid] = b; }

    bool memOpDone() const { return instFlags[MemOpDone]; }
    void memOpDone(bool f) { instFlags[MemOpDone] = f; }

    bool notAnInst() const { return instFlags[NotAnInst]; }
    void setNotAnInst() { instFlags[NotAnInst] = true; }


    //
    // INSTRUCTION EXECUTION
    //

    void demapPage(Addr vaddr, uint64_t asn)
    {
        cpu->demapPage(vaddr, asn);
    }
    void demapInstPage(Addr vaddr, uint64_t asn)
    {
        cpu->demapPage(vaddr, asn);
    }
    void demapDataPage(Addr vaddr, uint64_t asn)
    {
        cpu->demapPage(vaddr, asn);
    }

    Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags,
            const std::vector<bool>& byte_enable = std::vector<bool>());

    Fault writeMem(uint8_t *data, unsigned size, Addr addr,
                   Request::Flags flags, uint64_t *res,
                   const std::vector<bool>& byte_enable = std::vector<bool>());

    Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags,
                         AtomicOpFunctorPtr amo_op);

    bool translationStarted() const { return instFlags[TranslationStarted]; }
    void translationStarted(bool f) { instFlags[TranslationStarted] = f; }

    bool translationCompleted() const { return instFlags[TranslationCompleted]; }
    void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; }

    bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; }
    void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; }

    bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; }
    void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; }

    bool isTranslationDelayed() const
    {
        return (translationStarted() && !translationCompleted());
    }

  public:
#ifdef DEBUG
    void dumpSNList();
#endif

    PhysRegIdPtr renamedDestRegIdx(int idx) const
    {
        return _destRegIdx[idx];
    }

    PhysRegIdPtr renamedSrcRegIdx(int idx) const
    {
        assert(TheISA::MaxInstSrcRegs > idx);
        return _srcRegIdx[idx];
    }

    const RegId& flattenedDestRegIdx(int idx) const
    {
        return _flatDestRegIdx[idx];
    }

    PhysRegIdPtr prevDestRegIdx(int idx) const
    {
        return _prevDestRegIdx[idx];
    }

    void renameDestReg(int idx,
                       PhysRegIdPtr renamed_dest,
                       PhysRegIdPtr previous_rename)
    {
        _destRegIdx[idx] = renamed_dest;
        _prevDestRegIdx[idx] = previous_rename;
        if (renamed_dest->isPinned())
            setPinnedRegsRenamed();
    }

    void renameSrcReg(int idx, PhysRegIdPtr renamed_src)
    {
        _srcRegIdx[idx] = renamed_src;
    }

    void flattenDestReg(int idx, const RegId& flattened_dest)
    {
        _flatDestRegIdx[idx] = flattened_dest;
    }
    BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop,
                TheISA::PCState pc, TheISA::PCState predPC,
                InstSeqNum seq_num, ImplCPU *cpu);

    BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop);

    ~BaseDynInst();

  private:
    void initVars();

  public:
    void dump();

    void dump(std::string &outstring);

    int cpuId() const { return cpu->cpuId(); }

    uint32_t socketId() const { return cpu->socketId(); }

    MasterID masterId() const { return cpu->dataMasterId(); }

    ContextID contextId() const { return thread->contextId(); }

    Fault getFault() const { return fault; }
    Fault& getFault() { return fault; }

    bool doneTargCalc() { return false; }

    void setPredTarg(const TheISA::PCState &_predPC)
    {
        predPC = _predPC;
    }

    const TheISA::PCState &readPredTarg() { return predPC; }

    Addr predInstAddr() { return predPC.instAddr(); }

    Addr predNextInstAddr() { return predPC.nextInstAddr(); }

    Addr predMicroPC() { return predPC.microPC(); }

    bool readPredTaken()
    {
        return instFlags[PredTaken];
    }

    void setPredTaken(bool predicted_taken)
    {
        instFlags[PredTaken] = predicted_taken;
    }

    bool mispredicted()
    {
        TheISA::PCState tempPC = pc;
        TheISA::advancePC(tempPC, staticInst);
        return !(tempPC == predPC);
    }

    //
    //  Instruction types.  Forward checks to StaticInst object.
    //
    bool isNop()          const { return staticInst->isNop(); }
    bool isMemRef()       const { return staticInst->isMemRef(); }
    bool isLoad()         const { return staticInst->isLoad(); }
    bool isStore()        const { return staticInst->isStore(); }
    bool isAtomic()       const { return staticInst->isAtomic(); }
    bool isStoreConditional() const
    { return staticInst->isStoreConditional(); }
    bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
    bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
    bool isInteger()      const { return staticInst->isInteger(); }
    bool isFloating()     const { return staticInst->isFloating(); }
    bool isVector()       const { return staticInst->isVector(); }
    bool isControl()      const { return staticInst->isControl(); }
    bool isCall()         const { return staticInst->isCall(); }
    bool isReturn()       const { return staticInst->isReturn(); }
    bool isDirectCtrl()   const { return staticInst->isDirectCtrl(); }
    bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
    bool isCondCtrl()     const { return staticInst->isCondCtrl(); }
    bool isUncondCtrl()   const { return staticInst->isUncondCtrl(); }
    bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
    bool isThreadSync()   const { return staticInst->isThreadSync(); }
    bool isSerializing()  const { return staticInst->isSerializing(); }
    bool isSerializeBefore() const
    { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
    bool isSerializeAfter() const
    { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
    bool isSquashAfter() const { return staticInst->isSquashAfter(); }
    bool isMemBarrier()   const { return staticInst->isMemBarrier(); }
    bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
    bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
    bool isQuiesce() const { return staticInst->isQuiesce(); }
    bool isIprAccess() const { return staticInst->isIprAccess(); }
    bool isUnverifiable() const { return staticInst->isUnverifiable(); }
    bool isSyscall() const { return staticInst->isSyscall(); }
    bool isMacroop() const { return staticInst->isMacroop(); }
    bool isMicroop() const { return staticInst->isMicroop(); }
    bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
    bool isLastMicroop() const { return staticInst->isLastMicroop(); }
    bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
    bool isMicroBranch() const { return staticInst->isMicroBranch(); }

    void setSerializeBefore() { status.set(SerializeBefore); }

    void clearSerializeBefore() { status.reset(SerializeBefore); }

    bool isTempSerializeBefore() { return status[SerializeBefore]; }

    void setSerializeAfter() { status.set(SerializeAfter); }

    void clearSerializeAfter() { status.reset(SerializeAfter); }

    bool isTempSerializeAfter() { return status[SerializeAfter]; }

    void setSerializeHandled() { status.set(SerializeHandled); }

    bool isSerializeHandled() { return status[SerializeHandled]; }

    OpClass opClass() const { return staticInst->opClass(); }

    TheISA::PCState branchTarget() const
    { return staticInst->branchTarget(pc); }

    int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }

    int8_t numDestRegs() const { return staticInst->numDestRegs(); }

    // the following are used to track physical register usage
    // for machines with separate int & FP reg files
    int8_t numFPDestRegs()  const { return staticInst->numFPDestRegs(); }
    int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
    int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); }
    int8_t numVecDestRegs() const { return staticInst->numVecDestRegs(); }
    int8_t numVecElemDestRegs() const
    {
        return staticInst->numVecElemDestRegs();
    }
    int8_t
    numVecPredDestRegs() const
    {
        return staticInst->numVecPredDestRegs();
    }

    const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); }

    const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }

    uint8_t resultSize() { return instResult.size(); }

    InstResult popResult(InstResult dflt = InstResult())
    {
        if (!instResult.empty()) {
            InstResult t = instResult.front();
            instResult.pop();
            return t;
        }
        return dflt;
    }

    template<typename T>
    void setScalarResult(T&& t)
    {
        if (instFlags[RecordResult]) {
            instResult.push(InstResult(std::forward<T>(t),
                        InstResult::ResultType::Scalar));
        }
    }

    template<typename T>
    void setVecResult(T&& t)
    {
        if (instFlags[RecordResult]) {
            instResult.push(InstResult(std::forward<T>(t),
                        InstResult::ResultType::VecReg));
        }
    }

    template<typename T>
    void setVecElemResult(T&& t)
    {
        if (instFlags[RecordResult]) {
            instResult.push(InstResult(std::forward<T>(t),
                        InstResult::ResultType::VecElem));
        }
    }

    template<typename T>
    void setVecPredResult(T&& t)
    {
        if (instFlags[RecordResult]) {
            instResult.push(InstResult(std::forward<T>(t),
                            InstResult::ResultType::VecPredReg));
        }
    }
    void setIntRegOperand(const StaticInst *si, int idx, RegVal val)
    {
        setScalarResult(val);
    }

    void setCCRegOperand(const StaticInst *si, int idx, RegVal val)
    {
        setScalarResult(val);
    }

    void setVecRegOperand(const StaticInst *si, int idx,
            const VecRegContainer& val)
    {
        setVecResult(val);
    }

    void
    setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val)
    {
        setScalarResult(val);
    }

    void setVecElemOperand(const StaticInst *si, int idx, const VecElem val)
    {
        setVecElemResult(val);
    }

    void setVecPredRegOperand(const StaticInst *si, int idx,
                              const VecPredRegContainer& val)
    {
        setVecPredResult(val);
    }

    void markSrcRegReady();

    void markSrcRegReady(RegIndex src_idx);

    bool isReadySrcRegIdx(int idx) const
    {
        return this->_readySrcRegIdx[idx];
    }

    void setCompleted() { status.set(Completed); }

    bool isCompleted() const { return status[Completed]; }

    void setResultReady() { status.set(ResultReady); }

    bool isResultReady() const { return status[ResultReady]; }

    void setCanIssue() { status.set(CanIssue); }

    bool readyToIssue() const { return status[CanIssue]; }

    void clearCanIssue() { status.reset(CanIssue); }

    void setIssued() { status.set(Issued); }

    bool isIssued() const { return status[Issued]; }

    void clearIssued() { status.reset(Issued); }

    void setExecuted() { status.set(Executed); }

    bool isExecuted() const { return status[Executed]; }

    void setCanCommit() { status.set(CanCommit); }

    void clearCanCommit() { status.reset(CanCommit); }

    bool readyToCommit() const { return status[CanCommit]; }

    void setAtCommit() { status.set(AtCommit); }

    bool isAtCommit() { return status[AtCommit]; }

    void setCommitted() { status.set(Committed); }

    bool isCommitted() const { return status[Committed]; }

    void setSquashed();

    bool isSquashed() const { return status[Squashed]; }

    //Instruction Queue Entry
    //-----------------------
    void setInIQ() { status.set(IqEntry); }

    void clearInIQ() { status.reset(IqEntry); }

    bool isInIQ() const { return status[IqEntry]; }

    void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}

    bool isSquashedInIQ() const { return status[SquashedInIQ]; }


    //Load / Store Queue Functions
    //-----------------------
    void setInLSQ() { status.set(LsqEntry); }

    void removeInLSQ() { status.reset(LsqEntry); }

    bool isInLSQ() const { return status[LsqEntry]; }

    void setSquashedInLSQ() { status.set(SquashedInLSQ); status.set(Squashed);}

    bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }


    //Reorder Buffer Functions
    //-----------------------
    void setInROB() { status.set(RobEntry); }

    void clearInROB() { status.reset(RobEntry); }

    bool isInROB() const { return status[RobEntry]; }

    void setSquashedInROB() { status.set(SquashedInROB); }

    bool isSquashedInROB() const { return status[SquashedInROB]; }

    bool isPinnedRegsRenamed() const { return status[PinnedRegsRenamed]; }

    void
    setPinnedRegsRenamed()
    {
        assert(!status[PinnedRegsSquashDone]);
        assert(!status[PinnedRegsWritten]);
        status.set(PinnedRegsRenamed);
    }

    bool isPinnedRegsWritten() const { return status[PinnedRegsWritten]; }

    void
    setPinnedRegsWritten()
    {
        assert(!status[PinnedRegsSquashDone]);
        assert(status[PinnedRegsRenamed]);
        status.set(PinnedRegsWritten);
    }

    bool
    isPinnedRegsSquashDone() const { return status[PinnedRegsSquashDone]; }

    void
    setPinnedRegsSquashDone() {
        assert(!status[PinnedRegsSquashDone]);
        status.set(PinnedRegsSquashDone);
    }

    TheISA::PCState pcState() const { return pc; }

    void pcState(const TheISA::PCState &val) { pc = val; }

    Addr instAddr() const { return pc.instAddr(); }

    Addr nextInstAddr() const { return pc.nextInstAddr(); }

    Addr microPC() const { return pc.microPC(); }

    bool readPredicate() const
    {
        return instFlags[Predicate];
    }

    void setPredicate(bool val)
    {
        instFlags[Predicate] = val;

        if (traceData) {
            traceData->setPredicate(val);
        }
    }

    bool
    readMemAccPredicate() const
    {
        return instFlags[MemAccPredicate];
    }

    void
    setMemAccPredicate(bool val)
    {
        instFlags[MemAccPredicate] = val;
    }

    void setASID(short addr_space_id) { asid = addr_space_id; }
    short getASID() { return asid; }

    void setTid(ThreadID tid) { threadNumber = tid; }

    void setThreadState(ImplState *state) { thread = state; }

    ThreadContext *tcBase() { return thread->getTC(); }

  public:
    bool eaSrcsReady() const;

    bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; }
    void strictlyOrdered(bool so) { instFlags[IsStrictlyOrdered] = so; }

    bool hasRequest() const { return instFlags[ReqMade]; }
    void setRequest() { instFlags[ReqMade] = true; }

    ListIt &getInstListIt() { return instListIt; }

    void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }

  public:
    unsigned int readStCondFailures() const
    { return thread->storeCondFailures; }

    void setStCondFailures(unsigned int sc_failures)
    { thread->storeCondFailures = sc_failures; }

  public:
    // monitor/mwait funtions
    void armMonitor(Addr address) { cpu->armMonitor(threadNumber, address); }
    bool mwait(PacketPtr pkt) { return cpu->mwait(threadNumber, pkt); }
    void mwaitAtomic(ThreadContext *tc)
    { return cpu->mwaitAtomic(threadNumber, tc, cpu->dtb); }
    AddressMonitor *getAddrMonitor()
    { return cpu->getCpuAddrMonitor(threadNumber); }
};

template<class Impl>
Fault
BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size,
                                   Request::Flags flags,
                                   const std::vector<bool>& byte_enable)
{
    assert(byte_enable.empty() || byte_enable.size() == size);
    return cpu->pushRequest(
            dynamic_cast<typename DynInstPtr::PtrType>(this),
            /* ld */ true, nullptr, size, addr, flags, nullptr, nullptr,
            byte_enable);
}

template<class Impl>
Fault
BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr,
                            Request::Flags flags, uint64_t *res,
                            const std::vector<bool>& byte_enable)
{
    assert(byte_enable.empty() || byte_enable.size() == size);
    return cpu->pushRequest(
            dynamic_cast<typename DynInstPtr::PtrType>(this),
            /* st */ false, data, size, addr, flags, res, nullptr,
            byte_enable);
}

template<class Impl>
Fault
BaseDynInst<Impl>::initiateMemAMO(Addr addr, unsigned size,
                                  Request::Flags flags,
                                  AtomicOpFunctorPtr amo_op)
{
    // atomic memory instructions do not have data to be written to memory yet
    // since the atomic operations will be executed directly in cache/memory.
    // Therefore, its `data` field is nullptr.
    // Atomic memory requests need to carry their `amo_op` fields to cache/
    // memory
    return cpu->pushRequest(
            dynamic_cast<typename DynInstPtr::PtrType>(this),
            /* atomic */ false, nullptr, size, addr, flags, nullptr,
            std::move(amo_op));
}

#endif // __CPU_BASE_DYN_INST_HH__