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ltage.cc
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1 /*
2  * Copyright (c) 2014 The University of Wisconsin
3  *
4  * Copyright (c) 2006 INRIA (Institut National de Recherche en
5  * Informatique et en Automatique / French National Research Institute
6  * for Computer Science and Applied Mathematics)
7  *
8  * All rights reserved.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions are
12  * met: redistributions of source code must retain the above copyright
13  * notice, this list of conditions and the following disclaimer;
14  * redistributions in binary form must reproduce the above copyright
15  * notice, this list of conditions and the following disclaimer in the
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17  * neither the name of the copyright holders nor the names of its
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19  * this software without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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27  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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31  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  *
33  * Authors: Vignyan Reddy, Dibakar Gope and Arthur Perais,
34  * from André Seznec's code.
35  */
36 
37 /* @file
38  * Implementation of a L-TAGE branch predictor
39  */
40 
41 #include "cpu/pred/ltage.hh"
42 
43 #include "base/intmath.hh"
44 #include "base/logging.hh"
45 #include "base/random.hh"
46 #include "base/trace.hh"
47 #include "debug/Fetch.hh"
48 #include "debug/LTage.hh"
49 
50 LTAGE::LTAGE(const LTAGEParams *params)
51  : TAGE(params), loopPredictor(params->loop_predictor)
52 {
53 }
54 
55 void
57 {
58  TAGE::init();
59 }
60 
61 //prediction
62 bool
63 LTAGE::predict(ThreadID tid, Addr branch_pc, bool cond_branch, void* &b)
64 {
66  b = (void*)(bi);
67 
68  bool pred_taken = tage->tagePredict(tid, branch_pc, cond_branch,
69  bi->tageBranchInfo);
70 
71  pred_taken = loopPredictor->loopPredict(tid, branch_pc, cond_branch,
72  bi->lpBranchInfo, pred_taken,
73  instShiftAmt);
74  if (cond_branch) {
75  if (bi->lpBranchInfo->loopPredUsed) {
76  bi->tageBranchInfo->provider = LOOP;
77  }
78  DPRINTF(LTage, "Predict for %lx: taken?:%d, loopTaken?:%d, "
79  "loopValid?:%d, loopUseCounter:%d, tagePred:%d, altPred:%d\n",
80  branch_pc, pred_taken, bi->lpBranchInfo->loopPred,
83  bi->tageBranchInfo->tagePred, bi->tageBranchInfo->altTaken);
84  }
85 
86  // record final prediction
87  bi->lpBranchInfo->predTaken = pred_taken;
88 
89  return pred_taken;
90 }
91 
92 // PREDICTOR UPDATE
93 void
94 LTAGE::update(ThreadID tid, Addr branch_pc, bool taken, void* bp_history,
95  bool squashed, const StaticInstPtr & inst, Addr corrTarget)
96 {
97  assert(bp_history);
98 
99  LTageBranchInfo* bi = static_cast<LTageBranchInfo*>(bp_history);
100 
101  assert(corrTarget != MaxAddr);
102 
103  if (squashed) {
105  // This restores the global history, then update it
106  // and recomputes the folded histories.
107  tage->squash(tid, taken, bi->tageBranchInfo, corrTarget);
108 
109  if (bi->tageBranchInfo->condBranch) {
111  }
112  }
113  return;
114  }
115 
116  int nrand = random_mt.random<int>() & 3;
117  if (bi->tageBranchInfo->condBranch) {
118  DPRINTF(LTage, "Updating tables for branch:%lx; taken?:%d\n",
119  branch_pc, taken);
120  tage->updateStats(taken, bi->tageBranchInfo);
121 
123 
124  loopPredictor->condBranchUpdate(tid, branch_pc, taken,
125  bi->tageBranchInfo->tagePred, bi->lpBranchInfo, instShiftAmt);
126 
127  tage->condBranchUpdate(tid, branch_pc, taken, bi->tageBranchInfo,
128  nrand, corrTarget, bi->lpBranchInfo->predTaken);
129  }
130 
131  tage->updateHistories(tid, branch_pc, taken, bi->tageBranchInfo, false,
132  inst, corrTarget);
133 
134  delete bi;
135 }
136 
137 void
138 LTAGE::squash(ThreadID tid, void *bp_history)
139 {
140  LTageBranchInfo* bi = (LTageBranchInfo*)(bp_history);
141 
142  if (bi->tageBranchInfo->condBranch) {
143  loopPredictor->squash(tid, bi->lpBranchInfo);
144  }
145 
146  TAGE::squash(tid, bp_history);
147 }
148 
149 void
151 {
152  TAGE::regStats();
153 }
154 
155 LTAGE*
156 LTAGEParams::create()
157 {
158  return new LTAGE(this);
159 }
LoopPredictor::BranchInfo * lpBranchInfo
Definition: ltage.hh:90
#define DPRINTF(x,...)
Definition: trace.hh:229
void squashLoop(BranchInfo *bi)
LTAGE(const LTAGEParams *params)
Definition: ltage.cc:50
void squash(ThreadID tid, BranchInfo *bi)
Definition: ltage.hh:63
const Addr MaxAddr
Definition: types.hh:166
void condBranchUpdate(ThreadID tid, Addr branch_pc, bool taken, bool tage_pred, BranchInfo *bi, unsigned instShiftAmt)
Update LTAGE for conditional branches.
bool isSpeculativeUpdateEnabled() const
Definition: tage_base.cc:801
virtual void updateStats(bool taken, BranchInfo *bi)
Update the stats.
Definition: tage_base.cc:657
virtual void condBranchUpdate(ThreadID tid, Addr branch_pc, bool taken, BranchInfo *bi, int nrand, Addr corrTarget, bool pred, bool preAdjustAlloc=false)
Update TAGE for conditional branches.
Definition: tage_base.cc:509
virtual void regStats() override
Registers statistics.
Definition: ltage.cc:150
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: ltage.cc:56
Bitfield< 20, 16 > bi
Definition: types.hh:65
std::enable_if< std::is_integral< T >::value, T >::type random()
Use the SFINAE idiom to choose an implementation based on whether the type is integral or floating po...
Definition: random.hh:83
Bitfield< 7 > b
virtual void init()
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: sim_object.cc:76
virtual void squash(ThreadID tid, bool taken, BranchInfo *bi, Addr target)
Restores speculatively updated path and direction histories.
Definition: tage_base.cc:624
void squash(ThreadID tid, void *bp_history) override
Definition: ltage.cc:138
Definition: tage.hh:61
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
void regStats() override
Registers statistics.
Definition: bpred_unit.cc:73
bool tagePredict(ThreadID tid, Addr branch_pc, bool cond_branch, BranchInfo *bi)
TAGE prediction called from TAGE::predict.
Definition: tage_base.cc:355
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:227
virtual void squash(ThreadID tid, void *bp_history) override
Definition: tage.cc:89
bool predict(ThreadID tid, Addr branch_pc, bool cond_branch, void *&b) override
Get a branch prediction from LTAGE.
Definition: ltage.cc:63
Random random_mt
Definition: random.cc:100
void update(ThreadID tid, Addr branch_addr, bool taken, void *bp_history, bool squashed, const StaticInstPtr &inst, Addr corrTarget=MaxAddr) override
Updates the BP with taken/not taken information.
Definition: ltage.cc:94
const unsigned instShiftAmt
Number of bits to shift instructions by for predictor addresses.
Definition: bpred_unit.hh:321
LoopPredictor * loopPredictor
The loop predictor object.
Definition: ltage.hh:79
int8_t getLoopUseCounter() const
Gets the value of the loop use counter.
bool loopPredict(ThreadID tid, Addr branch_pc, bool cond_branch, BranchInfo *bi, bool prev_pred_taken, unsigned instShiftAmt)
Get the loop prediction.
virtual void updateHistories(ThreadID tid, Addr branch_pc, bool taken, BranchInfo *b, bool speculative, const StaticInstPtr &inst=StaticInst::nullStaticInstPtr, Addr target=MaxAddr)
(Speculatively) updates global histories (path and direction).
Definition: tage_base.cc:583
void updateStats(bool taken, BranchInfo *bi)
Update the stats.
TAGEBase * tage
Definition: tage.hh:64

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