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noncaching.hh
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39 
40 #ifndef __CPU_SIMPLE_NONCACHING_HH__
41 #define __CPU_SIMPLE_NONCACHING_HH__
42 
43 #include "cpu/simple/atomic.hh"
44 #include "params/NonCachingSimpleCPU.hh"
45 
51 {
52  public:
53  NonCachingSimpleCPU(NonCachingSimpleCPUParams *p);
54 
55  void verifyMemoryMode() const override;
56 
57  protected:
58  Tick sendPacket(MasterPort &port, const PacketPtr &pkt) override;
59 };
60 
61 #endif // __CPU_SIMPLE_NONCACHING_HH__
A MasterPort is a specialisation of a BaseMasterPort, which implements the default protocol for the t...
Definition: port.hh:75
NonCachingSimpleCPU(NonCachingSimpleCPUParams *p)
Definition: noncaching.cc:42
Tick sendPacket(MasterPort &port, const PacketPtr &pkt) override
Definition: noncaching.cc:57
The NonCachingSimpleCPU is an AtomicSimpleCPU using the 'atomic_noncaching' memory mode instead of ju...
Definition: noncaching.hh:50
void verifyMemoryMode() const override
Verify that the system is in a memory mode supported by the CPU.
Definition: noncaching.cc:48
uint64_t Tick
Tick count type.
Definition: types.hh:63
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
Definition: packet.hh:255
Bitfield< 0 > p

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