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noncaching.cc
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37  * Authors: Andreas Sandberg
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39 
40 #include "cpu/simple/noncaching.hh"
41 
42 NonCachingSimpleCPU::NonCachingSimpleCPU(NonCachingSimpleCPUParams *p)
43  : AtomicSimpleCPU(p)
44 {
45 }
46 
47 void
49 {
50  if (!(system->isAtomicMode() && system->bypassCaches())) {
51  fatal("The direct CPU requires the memory system to be in the "
52  "'atomic_noncaching' mode.\n");
53  }
54 }
55 
56 Tick
58 {
59  if (system->isMemAddr(pkt->getAddr())) {
60  system->getPhysMem().access(pkt);
61  return 0;
62  } else {
63  return port.sendAtomic(pkt);
64  }
65 }
66 
68 NonCachingSimpleCPUParams::create()
69 {
70  numThreads = 1;
71  if (!FullSystem && workload.size() != 1)
72  fatal("only one workload allowed");
73  return new NonCachingSimpleCPU(this);
74 }
A MasterPort is a specialisation of a BaseMasterPort, which implements the default protocol for the t...
Definition: port.hh:75
NonCachingSimpleCPU(NonCachingSimpleCPUParams *p)
Definition: noncaching.cc:42
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:175
Tick sendPacket(MasterPort &port, const PacketPtr &pkt) override
Definition: noncaching.cc:57
ThreadID numThreads
Number of threads we&#39;re actually simulating (<= SMT_MAX_THREADS).
Definition: base.hh:378
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:136
System * system
Definition: base.hh:386
The NonCachingSimpleCPU is an AtomicSimpleCPU using the &#39;atomic_noncaching&#39; memory mode instead of ju...
Definition: noncaching.hh:50
bool isAtomicMode() const
Is the system in atomic mode?
Definition: system.hh:139
void verifyMemoryMode() const override
Verify that the system is in a memory mode supported by the CPU.
Definition: noncaching.cc:48
bool isMemAddr(Addr addr) const
Check if a physical address is within a range of a memory that is part of the global address map...
Definition: system.cc:459
uint64_t Tick
Tick count type.
Definition: types.hh:63
Addr getAddr() const
Definition: packet.hh:726
void access(PacketPtr pkt)
Perform an untimed memory access and update all the state (e.g.
Definition: physical.cc:278
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
Definition: packet.hh:255
bool bypassCaches() const
Should caches be bypassed?
Definition: system.hh:160
PhysicalMemory & getPhysMem()
Get a pointer to access the physical memory of the system.
Definition: system.hh:267
Tick sendAtomic(PacketPtr pkt)
Send an atomic request packet, where the data is moved and the state is updated in zero time...
Definition: port.hh:427
Bitfield< 0 > p

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