root.cc File Reference

#include "base/logging.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
#include "debug/TimeSync.hh"
#include "sim/eventq_impl.hh"
#include "sim/full_system.hh"
#include "sim/root.hh"

Go to the source code of this file.

Variables
bool	FullSystem
	The FullSystem variable can be used to determine the current mode of simulation. More...
unsigned int	FullSystemInt
	In addition to the boolean flag we make use of an unsigned int since the CPU instruction decoder makes use of the variable in switch statements. More...

Variable Documentation

FullSystem

bool FullSystem

The FullSystem variable can be used to determine the current mode of simulation.

Definition at line 136 of file root.cc.

Referenced by SparcISA::RemoteGDB::acc(), MipsISA::RemoteGDB::acc(), PowerISA::RemoteGDB::acc(), AlphaISA::RemoteGDB::acc(), RiscvISA::RemoteGDB::acc(), X86ISA::RemoteGDB::acc(), ArmISA::RemoteGDB::acc(), PseudoInst::addsymbol(), PseudoInst::arm(), BaseCPU::BaseCPU(), BaseKvmCPU::BaseKvmCPU(), BaseSimpleCPU::BaseSimpleCPU(), ArmISA::canWriteAArch64SysReg(), BaseCPU::checkInterrupts(), Minor::Execute::checkInterrupts(), ArmISA::ISA::clear(), ArmISA::ISA::clear32(), DefaultCommit< Impl >::commit(), DefaultCommit< Impl >::commitHead(), O3ThreadContext< Impl >::copyArchRegs(), SimpleThread::copyState(), X86ISA::TLB::finalizePhysical(), FullO3CPU< O3CPUImpl >::FullO3CPU(), AlphaISA::getArgument(), SparcISA::getArgument(), ArmISA::getArgument(), ArmISA::ISA::getCurSveVecLenInBits(), ThreadState::getPhysProxy(), Minor::Execute::hasInterrupt(), ArmSystem::haveLPAE(), ArmSystem::haveSecurity(), ArmSystem::haveSemihosting(), ArmSystem::haveVirtualization(), ArmISA::ISA::MiscRegLUTEntryInitializer::highest(), ArmSystem::highestEL(), ArmSystem::highestELIs64(), ArmISA::ISA::initializeMiscRegMetadata(), ThreadState::initMemProxies(), Iris::ThreadContext::initMemProxies(), PseudoInst::initParam(), System::initState(), FullO3CPU< O3CPUImpl >::insertThread(), X86ISA::inUserMode(), FaultBase::invoke(), AlphaISA::AlphaFault::invoke(), SparcISA::SparcFaultBase::invoke(), X86ISA::X86FaultBase::invoke(), GenericPageTableFault::invoke(), MipsISA::MipsFaultBase::invoke(), RiscvISA::RiscvFault::invoke(), AlphaISA::ArithmeticFault::invoke(), X86ISA::X86Trap::invoke(), MipsISA::ResetFault::invoke(), AlphaISA::DtbFault::invoke(), AlphaISA::NDtbMissFault::invoke(), MipsISA::CoprocessorUnusableFault::invoke(), MipsISA::AddressFault< TlbInvalidFault >::invoke(), SparcISA::FastInstructionAccessMMUMiss::invoke(), ArmISA::ArmFault::invoke(), SparcISA::FastDataAccessMMUMiss::invoke(), AlphaISA::ItbFault::invoke(), SparcISA::SpillNNormal::invoke(), X86ISA::InvalidOpcode::invoke(), MipsISA::TlbFault< TlbInvalidFault >::invoke(), AlphaISA::ItbPageFault::invoke(), SparcISA::FillNNormal::invoke(), SparcISA::TrapInstruction::invoke(), ArmISA::Reset::invoke(), ArmISA::UndefinedInstruction::invoke(), ArmISA::SupervisorCall::invoke(), X86ISA::PageFault::invoke(), ArmISA::SecureMonitorCall::invoke(), ArmISA::ArmSev::invoke(), ArmISA::ISA::ISA(), PseudoInst::loadsymbol(), MinorCPU::MinorCPU(), AlphaISA::Decoder::moreBytes(), O3ThreadState< Impl >::O3ThreadState(), BaseSimpleCPU::postExecute(), BaseCPU::postInterrupt(), PseudoInst::readfile(), RubyPort::PioMasterPort::recvRangeChange(), BaseCPU::registerThreadContexts(), SimpleThread::regStats(), O3ThreadContext< Impl >::regStats(), X86ISA::Interrupts::requestInterrupt(), NonCachingSimpleCPU::sendPacket(), ThreadState::serialize(), Root::serialize(), System::serialize(), SparcISA::ISA::setFSReg(), CheckerCPU::setSystem(), DefaultDecode< Impl >::squash(), BaseCPU::startup(), System::System(), ArmISA::TableWalker::TableWalker(), BaseCPU::takeOverFrom(), takeOverFrom(), FullO3CPU< O3CPUImpl >::tick(), DefaultFetch< Impl >::tick(), Trace::ExeTracerRecord::traceInst(), X86ISA::TLB::translate(), X86ISA::GpuTLB::translate(), PowerISA::TLB::translateAtomic(), ArmISA::TLB::translateAtomic(), ArmISA::TLB::translateComplete(), RiscvISA::TLB::translateData(), MipsISA::TLB::translateData(), SparcISA::TLB::translateData(), ArmISA::TLB::translateFunctional(), RiscvISA::TLB::translateInst(), MipsISA::TLB::translateInst(), AlphaISA::TLB::translateInst(), SparcISA::TLB::translateInst(), ThreadState::unserialize(), System::unserialize(), and Checker< O3CPUImpl >::verify().

FullSystemInt

unsigned int FullSystemInt

In addition to the boolean flag we make use of an unsigned int since the CPU instruction decoder makes use of the variable in switch statements.

A value of 0 signifies syscall emulation, and any other value full system.

Definition at line 137 of file root.cc.