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arch
sparc
utility.hh
Go to the documentation of this file.
1
/*
2
* Copyright (c) 2003-2005 The Regents of The University of Michigan
3
* All rights reserved.
4
*
5
* Redistribution and use in source and binary forms, with or without
6
* modification, are permitted provided that the following conditions are
7
* met: redistributions of source code must retain the above copyright
8
* notice, this list of conditions and the following disclaimer;
9
* redistributions in binary form must reproduce the above copyright
10
* notice, this list of conditions and the following disclaimer in the
11
* documentation and/or other materials provided with the distribution;
12
* neither the name of the copyright holders nor the names of its
13
* contributors may be used to endorse or promote products derived from
14
* this software without specific prior written permission.
15
*
16
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
*
28
* Authors: Gabe Black
29
*/
30
31
#ifndef __ARCH_SPARC_UTILITY_HH__
32
#define __ARCH_SPARC_UTILITY_HH__
33
34
#include "
arch/sparc/isa_traits.hh
"
35
#include "
arch/sparc/registers.hh
"
36
#include "
arch/sparc/tlb.hh
"
37
#include "
base/bitfield.hh
"
38
#include "
base/logging.hh
"
39
#include "
cpu/static_inst.hh
"
40
#include "
cpu/thread_context.hh
"
41
#include "
sim/full_system.hh
"
42
43
namespace
SparcISA
44
{
45
46
inline
PCState
47
buildRetPC
(
const
PCState
&curPC,
const
PCState
&callPC)
48
{
49
PCState
ret = callPC;
50
ret.
uEnd
();
51
ret.
pc
(curPC.
npc
());
52
return
ret;
53
}
54
55
uint64_t
getArgument
(
ThreadContext
*tc,
int
&number, uint16_t size,
bool
fp
);
56
57
static
inline
bool
58
inUserMode
(
ThreadContext
*tc)
59
{
60
PSTATE pstate = tc->
readMiscRegNoEffect
(
MISCREG_PSTATE
);
61
HPSTATE hpstate = tc->
readMiscRegNoEffect
(
MISCREG_HPSTATE
);
62
return
!(pstate.priv || hpstate.hpriv);
63
}
64
65
void
copyRegs
(
ThreadContext
*src,
ThreadContext
*dest);
66
67
void
copyMiscRegs
(
ThreadContext
*src,
ThreadContext
*dest);
68
69
void
skipFunction
(
ThreadContext
*tc);
70
71
inline
void
72
advancePC
(
PCState
&
pc
,
const
StaticInstPtr
&inst)
73
{
74
inst->
advancePC
(pc);
75
}
76
77
inline
uint64_t
78
getExecutingAsid
(
ThreadContext
*tc)
79
{
80
return
tc->
readMiscRegNoEffect
(
MISCREG_MMU_P_CONTEXT
);
81
}
82
83
}
// namespace SparcISA
84
85
#endif
logging.hh
SparcISA::getExecutingAsid
uint64_t getExecutingAsid(ThreadContext *tc)
Definition:
utility.hh:78
GenericISA::DelaySlotUPCState::uEnd
void uEnd()
Definition:
types.hh:422
SparcISA::MISCREG_MMU_P_CONTEXT
MMU Internal Registers.
Definition:
miscregs.hh:89
RefCountingPtr< StaticInst >
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU...
Definition:
thread_context.hh:93
SparcISA::MISCREG_PSTATE
Definition:
miscregs.hh:65
GenericISA::SimplePCState::pc
Addr pc() const
Definition:
types.hh:148
SparcISA::buildRetPC
PCState buildRetPC(const PCState &curPC, const PCState &callPC)
Definition:
utility.hh:47
SparcISA::skipFunction
void skipFunction(ThreadContext *tc)
Definition:
utility.cc:249
SparcISA::copyRegs
void copyRegs(ThreadContext *src, ThreadContext *dest)
Definition:
utility.cc:204
SparcISA::getArgument
uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
Definition:
utility.cc:48
MipsISA::pc
Bitfield< 4 > pc
Definition:
pra_constants.hh:242
static_inst.hh
SparcISA::PCState
GenericISA::DelaySlotUPCState< MachInst > PCState
Definition:
types.hh:43
SparcISA::MISCREG_HPSTATE
Hyper privileged registers.
Definition:
miscregs.hh:77
bitfield.hh
isa_traits.hh
SparcISA::inUserMode
static bool inUserMode(ThreadContext *tc)
Definition:
utility.hh:58
GenericISA::SimplePCState::npc
Addr npc() const
Definition:
types.hh:151
SparcISA::advancePC
void advancePC(PCState &pc, const StaticInstPtr &inst)
Definition:
utility.hh:72
registers.hh
thread_context.hh
ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
GenericISA::DelaySlotUPCState
Definition:
types.hh:373
SparcISA
Definition:
asi.cc:34
StaticInst::advancePC
virtual void advancePC(TheISA::PCState &pcState) const =0
tlb.hh
SparcISA::copyMiscRegs
void copyMiscRegs(ThreadContext *src, ThreadContext *dest)
Definition:
utility.cc:68
ArmISA::fp
Bitfield< 19, 16 > fp
Definition:
miscregs_types.hh:175
full_system.hh
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